1. Describe how virtual memory functions in a modern computer system.

2. Differentiate between arithmetic pipelining and instruction pipelining.

3. Explain how pipelining lowers the latency of memory access.
4. Determine the primary benefit of data transport using DMA.
5. What is the difference between the Booth multiplier algorithm and conventional
multiplication?
6. Describe the handling of signed numbers in the Booth multiplication process.
7. Talk about the benefits of the non-restoring division algorithm over the restoring division
method.
8. Describe the difficulties in developing hardware for division functions, particularly for non-
restoring division.
9. Give an example of floating-point representation and explain its significance for numerical
computing.
10. Describe the sign, exponent, and mantissa of a floating-point number in detail.
11. Describe the distinction between exceptions and software interruptions.
12. Using a NOR gate, implement AND and OR gate.
13. Learn how to subtract 11101001 from 1011001 by applying the direct and two's complement
methods.
14. Talk about cache memory and its significance for memory organization.
15. Explain write policies and their significance in cache management.
16. Talk about the cache write policies for write-through and write-back.
17. Describe the cache mapping function and its need.
18. Describe the meaning index, tag, and offset in cache mapping.
19. Describe the problems with cache coherency that might occur in systems that have several
tiers of.
20. Determine the pipeline processing performance?
21. List the benefits and drawbacks of the pipeline.
22. Write down Cache Memory operation.
23. List the purposes of the various input/output commands found in a simple computer.
24. Provide pros and downsides of the multiple-bus system.
25. Describe the meaning of the CPU pipeline's fetch-deccode-execute cycle.
26. Describe the benefits of static RAM versus dynamic RAM.
27. Explain the function of Direct Memory Access (DMA) in input/output transfers.
28. Talk about the benefits of interrupt-driven I/O transfer.
29. Describe the constraints of program-controlled I/O transfer.
30. Implement three fundamental gates from the universal NAND gate, discuss the circuit design.
31. Describe a flowchart that uses the Booth algorithm to multiply two values.
32. Distinctions between RAW and WAR in pipeline processoring.
33. Describe different kinds of latches.
34. Determine the pipeline processing performance that is being measured?
35. Explain the role of I/O device interfaces in connecting peripheral devices to a computer.
36. Describe the input-output subsystem and the reasons behind its importance in computer
architecture.
37. Describe the problems that might occur with cache coherency in systems that have several
cache layers.
38. Describe memory interleaving and how it enhances computer systems' ability to access
memory efficiently.
39. Describe the throughput in terms of pipelining and explain how it differs from speedup.
40. What is the process by which cache memory enhances system performance?
41. Explain memory hierarchy and its significance for computer systems.
42. Estimate the easiest way to determine cache locations in which to store memory addresses.
43. A block-set associative cache memory consists of 128 blocks divided into four block sets. The
main memory consists of 16,384 blocks and each block contains 256 eight-bit words. Assess
the following- 1. How many bits are required for addressing the main memory? 2. How many
bits are needed to represent the TAG, SET and WORD fields?
44. A computer has a 256 KB, 4-way set associative, write back data cache with block size of 32
bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory
entry contains in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.
Estimate the number of bits in the tag field of an address.
45. Show how an interrupt service function and a subroutine vary from each other.
46. Write the steps involved in an instruction cycle?
47. Explain write-through approach.
48. Define Addressing modes with examples.
49. Give illustration of Von Neumann architecture with diagram.
50. what ISA is. Describe the ISA categorization with an example.
51. Show how associative mapping differs from set associative mapping.
52. Explain different types of hazards in pipelining Architecture?
53. Create a block diagram of a digital computer and explain it.
54. lists the many kinds of ROMs.
55. Block diagram of state Von Neumann architecture.
56. Explain the distinctions between RISC and CISC.
57. What distinguishes computer architecture from computer organization?
58. Draw and explain the digital computer's block diagram.
59. lists the different kinds of ROMs.
60. Block diagram of Von Neumann architecture.
61. Describe Harvard architecture
62. Learn how to subtract 11101001 from 1011001 by applying the direct and two's complement
methods.
63. Describe Ripple Carry Adder with its drawback.
64. Implement three fundamental gates from the universal NAND gate, discuss the circuit design.
65. Describe in details various kinds of special purpose registers.
66. what is it Propagation Delay? How carry look ahead adder reduces it.
67. Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per
instruction of 4. The same processor is upgraded to a pipelined processor with five stages but
due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume there
are no stalls in the pipeline. Then estimate the speed up achieved in this pipelined processor?
68. The two numbers given below are multiplied using the Booth’s algorithm. Multiplicand : 0101
1010 1110 1110 Multiplier: 0111 0111 1011 1101 How many additions/Subtractions are
required for the multiplication of the above two numbers?
69. Describe pipeline hazard.
70. Describe how parallel processing works.
71. Describe direct memory access.
72. Describe the various performance metrics of the pipeline design.
73. Explain the fixed- and floating-point representation of numbers.
74. Provide examples of the various interrupt kinds.
75. Explain data dependencies in pipelining.
76. Which kinds of dependencies are possible when instructions are executed in a pipeline?
77. Explain a structural dependency along with its solution in pipelining?
78. Imagine a pipeline with four stages that last 60, 50, 90, and 80 nanoseconds each. 10 ns is the
given latch delay. The following has to be estimated: a) pipeline cycle time; b) non-pipeline
execution time; c) speed up ratio; and d) pipeline time for 1000 jobs. g) Time in steps for a
thousand tasks f) Throughput.
79. The stage delays for a four-stage pipeline are 150, 120, 160, and 140 ns, respectively.
Between each step, there is a 5-ns delay in a register. Assuming constant clocking rate. Next,
calculate how long it will take the pipeline to handle 1000 data items in total.

80. Explain 0 address, 1 address, 2 address and 3 address instruction.

81. Examine the carry look ahead adder's operation.
82. With example explain advantage and disadvantage of different cache mapping technique.
83. Examine and contrast the features of DRAM (dynamic RAM) and SRAM (static RAM).
84. Talk about the Branch Prediction technique's function in pipelined processors .
85. Examine the page reference string that has three-page frames: 1, 3, 0, 3, 5, 6, 3. Calculate no
of page faults that happen with FIFO, LRU, and OPR.
86. Describe how associative mapping is superior to direct mapping.
87. The page reference string 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 3 with 4 page frames is an example
to consider. Use FIFO to write the number of page faults.
88. Describe the benefits and drawbacks of associative mapping.
89. The page reference string 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 3 with 4 page frames is an example
to consider. Enter the number of page fault using OPR.
90. List the benefits and drawbacks of direct mapping in brief.
91. Explain Locality of reference along with its types.
92. Justify which page replacement algorithm is better FIFO or LRU?
93. Write advantage and disadvantages of Optimal page replacement algorithm.
94. Explain Belady's anomaly along with a suitable example.
95. Consider the page reference string as 3, 1, 2, 1, 6, 5, 1, 3 with 3-page frames.
Evaluate the number of page faults using FIFO, LRU
96. Multiply -5 and 2 using Booth’s multiplication algorithm.
97. Divide Unsigned Integer Dividend (Q)=10, Divisor (M)=3 using Non-Restoring Division.
98. Divide Unsigned Integer Dividend (Q)=10, Divisor (M)=3 using Restoring Division.
99. Explain the flowchart for Booth’s multiplication algorithm.
100. What is parallel processing?
 (46)8
(2A2)H
(36)10
1 (100110)2 is equivalent to (26)10
10
100
Access time of auxiliary that is generally ________ times that of the main 1000
2 memory 10000
Produces the same result as obtained with logical shift left operation
Causes the sign bit to remain always unchanged
Needs additional hardware to preserve the sign bit
3 Arithmetic shift left operation is Needs additional hardware to preserve the sign bit
Magnetic disks
Tapes
Flash memory
4 Auxiliary Memory is Both A and B
In the same way as we perform subtraction in decimal number
Using 2’s complement method
Using 9’s complement method
5 Method for performing binary subtraction in a digital computer Using 10’s complement method
10111
110111
101000
6 2’s complement representation of (-23) is 101001
It can add as well as subtract two numbers
At a time, it either adds or subtracts
It mainly operates with parallel adder
7 Adder-subtractor composite unit - All of these
CPA
CLA
Both
8 In which type of adder all intermediate carry generated at first stage None of these
Adder
Subtractor
Multiplier
9 Addition is performed with the help of _____ in ALU By program only
Cache
DRAM's
SRAM's
10 Fastest data access is provided by ______ Registers +B53:C80
Secondary storage
Main memory
Register
11 Next level of memory hierarchy after the L2 cache is _______ TLB
Registers
Cache
Main memory
12 Fastest means of memory access for CPU determine Virtual Memory
Cache
Main
Secondary
13 Memory implemented using the semiconductor chips is _________ Registers
Main
Virtual
Secondary
14 Size of the ________ memory mainly depends on the size of the address bus Cache
Secondary memory
Main memory
Onboard memory
15 Which of the following is independent of the address bus devise? Cache memory
M*N
M+N
If M denotes the number of memory locations and N denotes the word size, then 2M+N
16 evaluate the storage capacity is ______________ 2M-N
RAM
ROM
Cache
17 Which of the following memory is non-volatile? ROM and Cache
Cache
RAM
Secondary memory
18 Which of the following is the lowest in the computer memory hierarchy? CPU registers
Cache
Register in CPU
Main memory
19 Which of the following has the fastest speed in the computer memory hierarchy? Disk cache
 Printer
Desktop
ALU
20 Which of the following is a part of the Central Processing Unit? Mouse
In IEEE 32-bit representations, the mantissa of the fraction is said to occupy 24
23
18
21 32
Height factors
Size factors
Representation of decimal numbers when numbers are written to the power of Scale factor
22 10 None of these
1010
F0F0
Convert (1111000011110000) to hexadecimal number
7070
23 5050
Double-precision
Single-precision
Extended format
24 32-bit representation of the decimal number is known as None of these
Hexadecimal
Octal
Binary
25 Data is usually stored in Decimal
2
8
10
26 The base of Hexadecimal number system 16
Non-Volatile Memory
Volatile Memory
Both of these
27 When power is switched off which memory loses its data None of these
10100
100
Apply signed-magnitude binary division and find the result if the dividend is 11001
28 (11100 )2 and divisor is (10011)2 1100
Hit/(Hit + Miss)
Miss/(Hit + Miss)
(Hit + Miss)/Miss
29 Hit Ratio is (Hit + Miss)/Hit
2
3
4
30 memory is classified in 5
arithmetic operations
logical operations
Both of these
31 Arithmetic Logic Unit (ALU) is used in computer for performing none of these
Sign-magnitude
2’s compliment
Which representation is most efficient to perform arithmetic operations on 1’s compliment
32 binary numbers None of These
Conditional codes
Multiplexer
Control unit
33 Which is used between incrementing the PC or performing ALU operations. None of these
Special memory locations
Special purpose registers
Cache
34 Which is used to increase the speed of memory access in pipelining Buffers
Block diagram
Time diagram
Space time diagram
35 Which is used to represent segment utilization as a function of time in pipelining. Space diagram
Superscalar operation
Assembly line operation
Von Neumann cycle
36 Another name for the pipelining process None of the mentioned
k-n-1
k+n-1
Total number of clock cycles in pipelining (where n = number of instruction and k k-n+1
37 = number of stages) k+n+1
pipelining
sequential processing
parallel processing
38 Select the concept of overlapping stages in pipelining. All of these
 instruction
arithmetic
Both of these
39 Which of the following is/are type of pipelining none of these
Utility software
Speed up utilities
Optimizing compilers
40 What has been developed specifically for pipelined systems None of the mentioned
Modification in processor architecture
Clock
Special unit
41 What is necessary for the fetch and execution cycles to be interleaved Control unit
1
2
Write the number of cycle(s) that should be completed for each stage in 3
42 pipelining 4
Structural hazard
Stalk
Deadlock
43 Contention for the usage of a hardware device is called None of the mentioned
Data hazard
Stock
Deadlock
44 Name of the situation wherein the data of operands are not available is called Structural hazard
To define the high-level programming language
To design the memory hierarchy
o specify how instructions are executed at the hardware level
45 Primary purpose of RTL interpretation of instructions in computer architecture To manage input/output devices
It represents the behavior of the entire system.
It describes the operation of the processor at the instruction level.
It specifies the logic gates used in the processor.
46 Which of the following best describes RTL level of abstraction in digital design It is used for high-level software design.
A single instruction executed by the processor
A sequence of instructions executed by the processor
A basic operation that transfers data between registers or performs
47 What does a microoperation refer to in RTL interpretation A high-level programming statement
Arithmetic Logic Unit (ALU)
Control Unit (CU)
Which component of a processor that is primarily responsible for performing Memory Unit
48 microoperations Input/Output Unit
It performs arithmetic and logical operations.
It manages the input and output devices.
It generates control signals to execute microoperations as per the
49 The role of the Control Unit in RTL interpretation? It stores data and instructions.
Control signals
Arithmetic Logic Unit (ALU)
Which is the RTL element that is responsible for specifying the source and Memory Unit
50 destination registers for a microoperation Clock cycle
Load A, Load B, Add, Store Result
Fetch Instruction, Decode, Execute, Store Result
write the sequences of microoperations that might be performed for an add Read from Memory, Write to Memory
51 instruction, in a simplified RTL interpretation None of the above
Fetch
Decode
Execute
52 What is the first step in the instruction execution cycle Writeback
Fetching the instruction from memory
Determining the address of the next instruction
Translating the instruction into a series of micro-operations
53 Decoding step that is primarily involved in the instruction execution cycle Writing the result of the operation to memory
Fetch the next instruction
Calculate the result of the instruction
Decode the instruction
54 What does the CPU do during the Execute step of the instruction execution cycle Write the result to the register file
Storing the result of the executed instruction in memory
Transferring the result of the executed instruction to a register
Fetching the next instruction
55 Responsibility of the Writeback step in the instruction execution cycle Decoding the instruction
2
3
4
56 Number of stages are there in a typical 5-stage instruction execution pipeline 5
Decoding the instruction
Calculating the result of the instruction
Fetching the next instruction
57 What is the purpose of Fetch stage in a pipelined CPU Writing the result to memory
 Fetching the next instruction
Translating the instruction into micro-operations
Executing the instruction
58 The responsibility of the Decode stage in a pipelined CPU Writing the result to memory
Reducing the clock speed of the CPU
Increasing the number of instructions executed per clock cycle
Decreasing the number of pipeline stages
59 Write Down primary benefit of pipelining in CPU design Eliminating the need for instruction execution cycles
Main memory
Registers
The Instruction Fetch stage in a pipelined CPU involves retrieving instructions Cache memory
60 from_____. Select the correct options Secondary storage (e.g., hard drive)
Bottlenecks in the pipeline that can slow down execution
A security threat to the pipeline
An error in the decoding stage
61 Pipelining hazard refer to The absence of a pipeline in modern CPUs
ISA defines the hardware architecture of the CPU.
ISA is responsible for managing the operating system.
ISA determines the speed of the CPU.
62 The true statement about the instruction set architecture (ISA) of a CPU ISA is related to input and output devices.
Storing data that will persist even after the computer is turned off.
Speeding up data access and manipulation by the CPU.
Communicating with input/output devices.
63 The primary use of Registers in a CPU Controlling the power supply to the CPU.
CPU registers are volatile and lose their data when the computer is
CPU registers are used for long-term storage of data.
A CPU typically has only one register.
64 Correct statements about CPU registers CPU registers are used primarily for storing program instructions.
Execution of arithmetic and logic operations.
Long-term storage of application data.
Facilitating communication with peripheral devices.
65 The role of registers in the context of a CPU Allocating memory for programs.
The speed and efficiency of program execution.
The size of the instruction set.
The amount of cache memory in the CPU.
66 Select the general-purpose registers that affect in a CPU The power consumption of the CPU.
A type of memory module
A technique to store data in cache
A way to specify the location of data in memory
67 an addressing mode in computer architecture A type of CPU instruction
Immediate addressing
Indirect addressing
Indexed addressing
68 The addressing mode that is commonly used to access data stored in an array Direct addressing
Keyboard
Mouse
Scanner
69 which of the following are input devices? All of these
Random Origin Money
Random Only Memory
Read Only Memory
70 RAM stands for Random Access Memory
4 bits
8 bits
12 bits
71 1 Byte = 16 bits
American Stable Code For International Interchange
American Standard Case For Institutional Interchange
American Standard Code For Interchange Information
72 ASCII stands for American Standard Code For Information Interchange
AND
OR
EXOR
73 Which gate gives the output as 1 only if all the inputs signals are 1. EXNOR
AND
OR
EXOR
74 Which gate gives the output as 0 only if all the inputs signals are 0. EXNOR
OR
AND
XOR
75 Which of the following is a universal logic gate? . NAND
7
8
6
76 how many binary digits are required to count decimal 100 5
 Bit
Byte
Nibble
77 Which of the following is typically the longest? Word
172
272
174
78 convert Binary number to Octal 010111100 274
1100 1011 1000
0011 0100 0111
0011 0100 0001
79 BCD number for decimal 347 1100 1011 0110
100010
100101
110101
80 Binary equivalent of Octal 45 100100
111011
1011001.011
1110.11
81 Convert 59.72 to BCD 1.011E+14
35647
11010
1.011E+15
82 convert 8B3F to Binary 1.0001E+15
8
10
2
83 The value of radix in binary number system is 4
624.12
145.12
154.12
84 Octal equivalent of 1100101.001010 145.21
1
2
If a 3-input AND gate has eight input possibilities, how many of those possibilities 4
85 will result in a high output? 8
A’+B’
A+A.B
A’B+AB’
86 Expression of an EXOR gate AB+A’B’
Main memory
Virtual memory
Associative memory
87 Content addressable memory is Auxiliary memory
paging
segmentation
fragmentation
88 Memory management technique where allocated size is fixed - indexing
Shared memory
Distributed memory
Both of these
89 Which of the following is/are type of multi processor on basis of memory? None of these
faster
same
slower
90 Associative memory is ……… than RAM. does not depend
paging
segmentation
fragmentation
91 Memory management technique where allocated size varies indexing
FIFO
LRU
Optimal
92 Which of the following is/are the algorithm for page replacement? All of these
Cache
Registers
RAM
93 Which of the following has the highest access time? Program Counter
Greater performance loss
Machine size is limited
Some functional unit is not fully pipelined
94 When Data hazards occurs Pipeline changes the order of read/write access to operands
k-n-1
k+n-1
Calculate the total number of clock cycles in pipelining (where n = number of k-n+1
95 instruction and k = number of stages) k+n+1
 sequential processing
pipelining
parallel processing
96 The overlapping concept of stages as a All of these
control hazard
data hazard
resource hazard
97 Structural hazard in pipelining as program hazard
To compress the binary representation of the operands
To encode the control signals for the ALU
To generate a partial product array
98 What is a Booth encoding used for in a Booth multiplier To perform modular arithmetic
It reduces the number of partial product bits.
It increases the number of adder stages.
It simplifies the multiplication process.
99 The advantage of using Booth encoding in multiplication It eliminates the need for carry propagation.
Subtract the multiplicand from the accumulator.
Add the multiplicand to the accumulator.
Shift the accumulator right by one position.
100 How do you handle a 0 1sequence in the multiplier during a Booth multiplier Shift the accumulator left by one position.
The same
Faster
The time complexity of a Booth multiplier compared to a simple ripple-carry Slower
101 multiplier for multiplying two n-bit numbers Depends on the specific operands
Multiply two numbers
Add two numbers
Write down the primary objective of both restoring and non-restoring division Divide one number by another
102 techniques Find the greatest common divisor of two numbers
Adding a constant to the quotient
Substituting the dividend with the divisor
Finding the remainder
103 Discuss about the term restoring in the context of division Rounding the quotient to the nearest integer
Simplicity of implementation
Faster convergence for all cases
What is an advantage of the restoring division algorithm over the non-restoring Reduced number of iterations
104 algorithm Lower hardware complexity
Add the divisor to the partial remainder
Subtract the divisor from the partial remainder
Shift the partial remainder right
105 What is done if the quotient bit is 0 in non-restoring division Shift the partial remainder left
Exact division
Approximate division
Integer division
106 Restoring division is Floating-point division
EEPROM
Flash memory
Which of the following is a volatile semiconductor memory technology used in SRAM
107 most computers for main memory (RAM)? ROM
L1 cache
L2 cache
Which level of memory is the fastest but also the smallest in capacity In a RAM
108 computer's memory hierarchy? Hard disk drive
To enhance CPU performance
To manage I/O devices
To execute user programs
109 Primary purpose of using interrupts in a computer system. To store temporary data
An interrupt is a program that runs concurrently with the main
An interrupt is an exception that transfers control to a specific routine
An interrupt is a type of instruction that improves CPU efficiency
110 Which of the following best describes the role of an interrupt in a CPU? An interrupt is a form of memory protection
To execute user programs
To provide additional CPU cores
Describe what is the primary purpose of using a DMA controller in the context of To manage interrupts
111 DMA (Direct Memory Access)? To transfer data between memory and I/O devices without CPU
When you need low latency and minimal CPU involvement
It requires the CPU to actively manage data transfer between I/O
It is less efficient for handling I/O devices.
112 Which of the following statements is true regarding interrupt-driven I/O? It is primarily used for program execution.
When you need low latency and minimal CPU involvement
When the CPU is not available for any other task
When would you typically choose DMA over interrupt-driven I/O for a data When you want to improve CPU clock speed
113 transfer operation? When you need to execute user programs simultaneously
They allow data to be entered into the computer.
They convert physical actions into digital data.
Examples include monitors and printers.
114 Which of the following is NOT a characteristic of input devices? They are essential for user interaction with the computer.
 They provide a way to display information on a screen.
They are used to temporarily store data in the computer's memory.
They are non-volatile and retain data even when the computer is
115 Which of the following is a characteristic of storage devices? They are not considered peripheral devices.
They are a type of CPU
They perform I/O operations without the involvement of the CPU
They are used to generate interrupts
116 Which of the following statements is true about DMA controllers? They improve CPU performance by reducing clock cycles.
To reduce the clock speed of the processor
To reduce the number of pipeline stages
To increase the throughput and performance of the processor
117 The primary goal of pipelining in computer architecture? To simplify the design of the processor
0
1
2
118 Estimate the ideal CPI (Cycles Per Instruction) for a pipelined processor? 5
An instruction that executes quickly
A delay in the pipeline to resolve a hazard
A type of branch instruction
119 What is a "stall" or "bubble" in a pipeline? A measure of the pipeline's capacity
The time it takes to complete a single task
The rate at which a system processes tasks or data
The number of CPU cores in a computer
120 What is throughput in the context of computer systems? The efficiency of a data storage system
Speedup = Execution Time of Sequential Program / Execution Time of
Speedup = Cache Size / Memory Size
Speedup = Number of Processors - Number of Tasks
121 Speedup in parallel computing is often calculated as: Speedup = Clock Frequency × Number of Cores
A dangerous situation in a computer system
An obstacle that prevents the smooth execution of instructions in a
A type of instruction used for debugging
122 What is a hazard in the context of pipeline processing in computer architecture? A type of microprocessor architecture
Structural hazard
Data hazard
Control hazard
123 Which of the following is NOT a common type of pipeline hazard? Caching hazard
A hazard related to the structure of the instruction set
A hazard caused by limited hardware resources in the pipeline
A hazard that occurs when instructions depend on a previous control
124 What is a structural hazard in pipeline processing? A hazard that involves the ordering of instructions
It occurs when two instructions write to the same register.
It occurs when an instruction reads data before a previous instruction
It occurs when an instruction reads data after a previous instruction
125 What is a "read-after-write" data hazard in pipelining? It is a structural hazard.
Forwarding (also known as data forwarding or data bypassing)
Clock gating
Register renaming
126 Which technique is commonly used to resolve data hazards in pipelining? Pipeline flushing
Indirect addressing
Register addressing
The addressing mode that the operand is explicitly specified in the instruction Indexed addressing
127 itself Immediate addressing
Register addressing
Direct addressing
The addressing mode that is used when an instruction specifies the address of Indirect addressing
128 the data, and the CPU fetches the data from that address? Indexed addressing
Register addressing
Direct addressing
Indirect addressing
129 The addressing mode that a register is used to store the address of the operand? Immediate addressing
Indexed addressing
Indirect addressing
The addressing mode that is typically used for jump instructions and subroutine Relative addressing
130 calls Register addressing
Indexed addressing
Indirect addressing
The addressing mode, that the operand is calculated by adding an offset to a Immediate addressing
131 base address Absolute addressing
Indirect addressing
Register addressing
The addressing mode that is most suitable for accessing local variables and Immediate addressing
132 parameters in a function Indexed addressing
Indirect addressing
Relative addressing
The addressing mode that is used when the operand is located at a fixed memory Direct addressing
133 location specified within the instruction ndexed addressing
 Direct addressing
Immediate addressing
The addressing mode that is often used for quick access to small, constant values Indirect addressing
134 like 0 or 1 Indexed addressing
A set of hardware components in a CPU
A set of high-level programming languages
A set of instructions that a CPU can execute
135 An instruction set in computer architecture is A set of memory addresses in a computer
Operation code (opcode)
Source and destination registers
Which is NOT a typical component of an instruction in a computer's instruction Memory address
136 set? High-level programming language
RISC (Reduced Instruction Set Computer)
CISC (Complex Instruction Set Computer)
An instruction set architectures that is commonly used in modern desktop and VLIW (Very Long Instruction Word)
137 server CPUs None of the above
Adds two numbers
Multiplies two numbers
Transfers data from memory to a register
138 The function of a load instruction Jumps to a different location in memory
CPU performance
Storage capacity
The number of bits in an instruction can affect ________ aspects of a computer Network speed
139 system. Printer quality
It always jumps to a specific location.
It jumps to a location based on a condition, such as a comparison
It performs mathematical operations.
140 What best describes about conditional branch instruction in an instruction set It moves data between registers.
It indicates the memory address to load data from.
It represents a constant value to be used in the operation.
It specifies the next instruction to execute.
141 What is the purpose of an immediate value in an instruction It denotes the source and destination registers.
Fixed-point uses a fixed number of bits for the integer and fractional
Fixed-point is more suitable for scientific computations, while floating-
What is the main difference between fixed-point and floating-point Fixed-point is only used in specialized hardware, while floating-point
142 representations There is no difference; the terms are interchangeable.
255
Discuss the maximum value that can be represented in a fixed-point 32767
representation, if you have 8 bits allocated for an integer part and 8 bits for a 65535
143 fractional part 65536
Greater precision
Wider range of representable numbers
Simpler hardware implementation
144 An advantage of fixed-point over floating-point representation Improved handling of very large numbers
16 bits for mantissa and 8 bits for exponent
The number of bits for the mantissa (significand) and exponent in a floating-point 23 bits for mantissa and 8 bits for exponent
representation for the standard IEEE 754 single-precision format that typically 32 bits for mantissa and 16 bits for exponent
145 allocates. 64 bits for mantissa and 32 bits for exponent
They can represent all real numbers exactly.
They are always stored with infinite precision.
They are subject to rounding errors due to finite precision.
146 Correct statement about floating-point numbers They have a fixed number of decimal places.
When you need a wide range of values with high precision.
When you have limited hardware resources and need simplicity.
When should you choose fixed-point over floating-point representation for a When you require exact representation of all real numbers.
147 given application When you want to handle very large or very small numbers.
Digital signal processing
Control systems for industrial machines
Fixed-rate financial calculations
148 Common application for floating-point representation Text processing and word processing
A type of coffee maker
An electronic circuit for adding binary numbers
A water purification system
149 Ripple carry adder A type of video game controller
It adds binary numbers using a parallel mechanism
It adds binary numbers using a serial mechanism
It adds binary numbers using optical signals
150 How does a ripple carry adder perform addition It adds decimal numbers, not binary numbers
It is very fast
It is highly energy-efficient
It has a slow propagation delay
151 Primary disadvantage of a ripple carry adder It can only add a limited number of bits efficiently
It is generated by a separate carry generator circuit
It travels through a parallel path
It travels through a series of logic gates from one bit to the next
152 How does the carry signal ripple in a ripple carry adder It is generated independently for each bit
 Constant time
Linear time
What is the time complexity of a ripple carry adder in terms of the number of bits Quadratic time
153 it can add? Exponential time
1
2
Discuss the number of full adders that are typically used in a 4-bit ripple carry 3
154 adder 4
It is discarded
It is used in the addition of the current bits and passed to the next
It is stored in memory
155 What happens when a carry bit is generated in a full adder during addition It is used to subtract the numbers
Increasing the number of full adders
Reducing the clock frequency
Using more power-hungry components
156 Which is the method to improve the speed of addition in a ripple carry adder Implementing parallel addition
Image processing
Digital signal processing
Arithmetic and data processing units in microprocessors
157 What is the most common application of ripple carry adders Cryptography
Low power consumption
Simplicity in design and implementation
Extremely fast addition speed
158 Primary advantage of ripple carry adders High resistance to noise
Faster propagation delay
Simplicity of design
Primary advantage of a carry-look-ahead adder (CLA) over a ripple-carry adder Lower power consumption
159 (RCA) Reduced gate count
4 G and 4 P signals
3 G and 3 P signals
How many G and P generate/propagate signals are needed in a 4-bit carry-look- 16 G and 16 P signals
160 ahead adder 7 G and 7 P signals
It generates the carry-out bit by ripples through all the adder stages.
It uses a fixed carry chain to calculate carries in parallel.
It is slower than the ripple-carry adder for all input combinations.
161 Correct statements about the carry-look-ahead adder It is only suitable for small addition operations.
The number of input bits
The number of XOR gates used
Critical path delay in a 4-bit carry-look-ahead adder that is primarily determined The carry-look-ahead logic
162 by The number of output bits
High gate count
Slower operation compared to RCA
Limited input width
163 The primary disadvantage of a carry-look-ahead adder (CLA) Reduced parallelism
Division of two numbers
Addition of two numbers
Multiplication of two numbers
164 The primary purpose of a Booth multiplier Subtraction of two numbers