Microprocessor Systems

Software Model

Dr. Taisir Eldos

 Introduction
q Machine language uses sequence of words of 0’a &1’s to specify the program
v Load Accumulator with $12 is 00111110, 00010010
q Hex language uses sequence of words of hexadecimal representation of them
v Load Accumulator with $12 is: 3E, 12
q Symbolic language uses mnemonics that represent them
v Load Accumulator with $12 is: LDA 12
q Assembly languages is a symbolic language with directives and labels
v Load Accumulator with $12 is:
v Count EQU $12
v Start LDA #Count
q Assemblers Translate Source Code into Object Code
v Use Macros to replace sets of instructions (sequences)
v Use Labels and Comments for Better Programming
v Use Directives for selectivity, easy allocation
v Enhance Modular Programming and Reusability
q Critical parts of some applications are written in Assembly for efficiency

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 Memory Organization and Indexing
q Memory may be organized as bytes, words, longwords, etc.
q Each location in memory has an index or address to refer to
q The index may refer to a byte, word, longword, or …
q The memory is then: byte indexed, word indexed, longword indexed, or …

000000 000000 000000

000001 000001 000001
000002 000002 000002
000003 000003 000003

Byte wide Word wide Longword wide

Byte indexed Word indexed Longword indexed

000000 000000 000000

000001 000002 000004
000002 000004 000008
000003 000006 00000C

Byte wide Word wide Longword wide

Byte indexed Byte indexed Byte indexed

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 Endian & Alignment
q If the memory organization and indexing are not the same, we have few issues
to consider; data mapping and alignment
q If the processor registers and memory have different size, we need a method
to map multi-byte or multi-word data between processor registers and
memory locations, there are to methods:
v Little Endian, which maps lower order data items to lower order address locations
v Big Endian, which maps lower order data items to higher order address locations
q The Endian term applies to file formats too, when an application stores a
multi-byte or multi-word data items
q Endianness is significant because data may be copied from memory to a file to
bee seen on another computer, and they have to agree on the ordering
q For example:
v DEC and IBM processors are Little
v Motorola and Sun processors are Big
v MIPS and PowerPC 601 are switchable; allow selecting either one at run time
q Alignment is about the data fragmentation when accessing memory; whether
the boundaries of data units must be aligned or not
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 Processor & Memory Data Mapping - Bytes
q Little Endian, Lower Order Data maps to Lower Order Addresses
q Big Endian, Lower Order Data maps to Higher Order Addresses
q Processors are either Little Endians or Big Endians
q Some processors are switchable; may default to one and switch to the other
000100 … B3 B2 B1 B0
000101 B3
000102 B2
000103 B1 Big Endean Processor:
Low Order Data « High Order Address
000104 B0
000105 …
000106 B0
Little Endean Processor:
000107 B1 Low Order Data « Low Order Address
000108 B2
000109 B3
00010A … B3 B2 B1 B0

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 Processor & Memory Data Mapping - Words
q If the processor and memory data buss are word sized, then word mapping is
straightforward
q However, multi-word data items map the way we discussed before

000100 … … W1 W0
000102
000104
000106 W1 Big Endean Processor:
Low Order Data « High Order Address
000108 W0
00010A … …
00010C W0
Little Endean Processor:
00010E W1 Low Order Data « Low Order Address
000110
000112
000114 … … W1 W0

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 Memory Alignment
q When writing data to memory, should we allow 001001 01 23 001000
fragmented access? 001003 00 45 001002
q Then we have to think of two distinct but related 001005 67 89 001004
issues: Alignment and Padding 001007 001006

q If it has to go to an even address, then we say the 001009 001008

00100B 00100A
processor is aligned, and some data like zeros go to
the skipped locations which is called padding
q Regarding spatial and temporal performance,
q Aligned processor show good for temporal but bad
for spatial performance, nonaligned is opposite 001001 01 23 001000
001003 89 45 001002
q Suppose the program wants to write $0123 word,
001005 67 001004
then $45 byte, then $6789 word (Little Endian)
001007 001006
q The upper one is aligned and it pads the next 001009 001008
available byte with 00 to keep data aligned 00100B 00100A
q The lower one is nonaligned, and it write to the
next available, no attention to boundaries, assumed
little endian processor here
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 Assembler Directives - EQU
EQU Equate ; Binds a name to a value

Salary EQU 1120

CMP.W #Salary, D0 ; compare D0 with 1120
MOVE.W #Salary, D2 ; load D2 with 1120

When a parameter is used quite often in the code, you better use this directive; if
it needs to be changed later, you change only one place

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 Assembler Directives - ORG
ORG Origin ; Location Counter 001000 12 3C 001001
001002 00 20 001003
ORG $001000 001004 08 14 001005
001006 00 05 001007
MOVE.B #$20, D1
001008 06 FA 001009
Loop BTST #5, (A4) 00100A 00100B
BNE Loop 00100C 00100D
00100E 00100F
001010 001011
ORG $001012
001012 10 20 001013
Count DC.W $1020 001014 001015

Why MOVE.B #$20, D1 is $123C0020? And BTST #5, (A4) is $08140005? See
the next slide

After fetching BNE, PC=00100A, if the condition of BNE is true, we add to it

the sign extended argument (FA) which is FFFFFA to get 001004 and loop

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 Assembler Directives - DC
DC Define Constant 001000 0A 42 001001
Load it in memory before running 001002 00 0A 001003
001004 00 42 001005
001006 41 70 001007
ORG $001000
001008 72 69 001009
Time DC.B 10, 66 00100A 6C 20 00100B
DC.W 10, 66 00100C 38 20 00100D

Date DC.B “April 8 1985” 00100E 31 39 00100F

001010 38 35 001011
DC.L 19, $32
001012 00 00 001013
001014 00 13 001015
Note: 10 and 66 saved as 0A and 42, since they have no 001016 00 00 001017
identifiers, default is decimal 001018 00 32 001019
00101A 00101B
19 is decimal, its Hex is 00 00 00 13 or 0000 0013
00101C 00101D

The MC68000 is Big Endian, the higher order byte has the
address of the word, and the lower is one count up, this
is why we swapped the addressing (left and right)
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 Assembler Directives - DS
DS Define Storage 001000 001001
Allocates only, written/read in run time 001002 001003
001004 001005
001006 001007
Base EQU 4
001008 001009
ORG $001000 00100A 00100B
Block1 DS.B 3*Base+2 00100C 00100D

Block2 DS.W Base 00100E 00100F

001010 001011
Space DS.B 3
001012 001013
Start MOVE.B #$75, D1 001014 001015
001016 001017

Block1 is 001000, light gray bytes reserved (no write) 001018 X 001019
00101A 12 3C 00101B
Block2 is 00100E, dark gray words reserved (no write) 00101C 00 75 00101D
Space is 001016
Start is 00101A not 001019 to keep instructions word
aligned with word boundaries (X means skipped)

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 Instruction Encoding & Decoding
q MOVE.B #$20, D1, encoded as $123C0020
q 00 01 001 000 111 100, 00000000010000
v 00, Opcode (Move instruction)
v 01, Size (01 for Byte, 10 for Word and 11 for Longword)
v 001, For register number 1
v 000, For destination addressing mode (Dn)
v 111, For source addressing mode (Immediate number, along with register value)
v 100, For destination register
v 0000000000100000, The immediate value of the source

q BTST #5, (A4) is encoded as $08140005

q 0000100000010100, 0000000000000101
v 0000100000, Opcode (Bit Test instruction, with immediate bit number)
v 010, For addressing mode of the test location, (An)
v 100, For the register to test (A4)
v 0000000000000101, The immediate value of the number of bit to test

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 Programming Model
q 8x32 Data Registers (D0 - D7) 31 16 15 8 7 0
D0
q 7x32 Address Registers (A0 - A6)
q 1x32 User Stack Pointers (USP=A7)
q 1x32 Supervisor Stack Pointer (SSP=A7’)
q 1x32 Program Counter (PC)
q 1x16 Status Register (SR) D7
v 5 Flags, System Byte (SB) A0
v 5 Flags, Condition Code Register (CCR)
q Data registers can be accessed as byte,
words and long words
q Address registers can be accessed as A6
words and long words only
A7
q There are 2 modes o operation; user and A7’
supervisor mode (or protected mode)
q System Byte (SB) can be accessed in the PC

T S I2 I1 I0 X N Z V C SB CCR SR

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 System Register Flags
Bit Name Meaning

0 C Carry Bit (multipurpose flag, affected by arithmetic and others)

1 V Overflow Bit (For signed numbers)
2 Z Zero Bit
3 N Negative Bit (Copy of the MSB of the result)
4 X Extend Bit (affected by arithmetic operations only, better use)

8 I0 Interrupt Mask Bit

9 I1 Interrupt Mask Bit
10 I2 Interrupt Mask Bit

13 S Status Bit (Supervisor/User Mode)

15 T Trace Bit (Trace/Normal Mode)

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 Microprocessor Systems
Addressing Modes

Dr. Taisir Eldos

 Addressing Modes - Symbols and Notation
q Register Transfer Language (RTL)

Instruction ADD <source>, <destination>

RTL equivalent [destination]ß [destination] + [source]

Instruction MOVE <source>, <destination>

RTL equivalent [destination]ß [source]

q Source & destination are effective addresses, addressing mode determines

q $ means Hexadecimal, % means Binary, no symbol means Decimal

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 Immediate or Literal
q In this mode, the actual operands follow the instruction
q Allows a constant to be setup when program is written
q The # is used to tell the Assembler “its immediate”
q Typical application to setup control loops and delay counters
q Example

MOVE.W #$8123, D3 // [D3(0:15)] ß $8123

MOVE.L #$8123, D3 // [D3(0:31)] ß $00008123

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 Absolute or Direct
q Instruction contains the operand’s address not its value
q Long, 32-bit address, accesses 16 Mbytes
q Short, 16-bit signed, to be extended
q Used when the address of the operand is known when the program is written,
like memory-mapped I/O instruction or non-relocatable code
q Avoid Position-Independent Code (Relocatable)
q Assembler decides on short or long, (evaluate labels)
q Examples

MOVE.L D3, $1234 // [M($1234)] ß [D3(16:31)]; [M($1236)] ß [D3(0:15)]

MOVE.W $1234, D3 // [D3(0:15)] ß [M($1234)]

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 Register Direct
q Does not involve memory address, hence so fast
q Effective address of operand is the register name
q Example

MOVE.L D0, D3 // [D3] ß [D0]

MOVE.W D0, D3 // [D3(0:15)] ß [D0(0:15)]

Destination can not be an Address Register, Need to use a special one

MOVEA.L D0, A3 // [A3] ß [D0]

Dr. Taisir Eldos

 Address Register Indirect
q Specified by enclosing the address register in 001000 001001
parentheses 001002 57 30 001003
q Fast, address is in the CPU and can be dynamically 001004 001005
changed (add x) 001006 001007

q Apps: Arrays, records and link lists 001008 31 29 001009

00100A 57 30 00100B
q Example
00100C 00100D
A5 = 00001002 00100E 00100F
A6 = 00001008 001010 001011
001012 001013
D4 = 31295730
001014 001015
001016 001017
MOVE.W D4, (A5) // [M([A5])] ß [D4(0:15)] 001018 001019
00101A 00101B
MOVE.L D4, (A6) // [M([A6])] ß [D4] 00101C 00101D

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 Address Register Indirect with Postincrement
q Postincrement provides faster access to consecutive data items like tables and
arrays
q Features less time and space
q Increment by 1 for .B, 2 for .W and 4 for .L instructions
q Exception is A7/A7’, where only 2 or 4 is valid, to preserve alignment (word
boundary)
q Applications: accessing data structures

MOVE.L (A0)+, D3 // [D3] ß [M([A0])]; [A0] ß [A0] + 4

MOVE.W (A7)+, D4 // [D4(0:15)] ß [M([A7])]; [A7] ß [A7] + 2

MOVE.B (A7)+, D4 // [D4(0:7)] ß [M([A7])]; [A7] ß [A7] + 2

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 Address Register Indirect with Postincrement
* Clear Array
* Clear an array of 16 longwords starting at address Buffer
*
MOVE.B #16, D0 // Setup a counter
MOVEA.L #Buffer, A0 // Point to the array
Loop CLR.L (A0)+ // Clear and move
SUBQ.B #1, D0 // Decrement counter
BNE Loop // Repeat until zero

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 Address Register Indirect with Postincrement
// Compare two arrays of 100 words at 2000 and 3000
Table1 EQU $002000 // Location of 1st table
Table2 EQU $003000 // Location of 2nd table
Many EQU 100 // A counter, 100 words
MOVEA.L #Table1, A0 // Load address
MOVEA.L #Table2, A1 // Same as above
MOVE.B #Many, D0 // Setup a counter
Loop CMPM.W (A0)+, (A1)+ // Compare and move up
BNE Fail
SUBQ.B #1, D0
BNE Loop // Repeat until done
Success .
.
Fail .
.

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 Address Register Indirect with Predecrement
q Predecrement provide faster access to consecutive data items like tables and
arrays
q Features less time and space
q Decrement by 1 for .B, 2 for .W and 4 for .L instructions
q Exception is A7/A7’, where only 2 or 4 is valid, to preserve alignment
q Applications include accessing data structures

MOVE.L -(A0), D3 // [A0] ß [A0] – 4; [D3] ß [M([A0])]

MOVE.W -(A7), D4 // [A7] ß [A7] – 2; [D4(0:15)] ß [M([A7])]

MOVE.B -(A7), D4 // [A7] ß [A7] – 2; [D4(0:7)] ß [M([A7])]

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 Register Indirect with Displacement
q Effective address computed by adding the content of address register to a
signed 16-bit word (part of the instruction, then sign extended)
q Effective Address ea is the sum of address register content plus displacement
q Applications include accessing data structures with records and fields

MOVE.L 12(A4), D3 // [D3] ß [M(12+[A4])]

MOVE. W-$4(A1), D0 // D0(0:15)] ß [M(-$4+[A1])]

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 Register Indirect with Index
q Effective address computed by adding the content of address register to a
signed 16-bit word (after sign extension) or 32-bit longword, and an 8-bit
signed offset
q Most complex addressing mode
q Apps: accessing 3D arrays

MOVE.L 9(A1,D0.W), D3 // [D3] ß [M(9+[A1]+[D0(0:15)])]

q Sign extend Xj if needed, then compute: ea = d8 + [Ai] + [Xj]

q Index register is Xi but only .L or .W allowed, and the offset is d8
q Get 7th item in 23rd record of 13th structure, Go

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 Program Counter Relative
q Special case of register indirect, the PC register is implied
q May or may not be indexed:
v Index: ea = [PC] + [Xn] + d8, and
v No index: ea = [PC] + d16
q Limiting the displacement to d8 when index is used is a tradeoff; to provide 5
bits in the instruction to encode Xi (D0, …, D7, A0, …, A6)

MOVE.B Table(PC), D2 // Load value1 in D2(0:7)

.
.
Table DC.B Value1
DC.B Value2

q The actual distance is computed and encoded within the instruction, to be

added to the PC upon running
q This addressing mode is quite useful in making Position Independent Code
(PIC), as it can reside anywhere in the memory

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