Department of Computer Science,

Mathematics & Physics

COMP2220 Computer Systems Architecture

Laboratory #4 –Digital Logic Circuits

INTRODUCTION

The focus of the laboratory session this week is on digital logic circuits. After several
weeks of preparation we are finally ready to get creative. This laboratory exercise will
provide you with the opportunity to put your previous experience to the test.

LAB OBJECTIVES:

By the end of this session students will be able to:

 Demonstrate the ability to design and implement combinational logic solutions
 Design the ability to design and implement synchronous counter circuits
 Prepare a MSWord document containing the designed solutions (All working must
be shown).

GETTING STARTED

Recall that there is no magic trick in designing digital logic solutions. The process covered in
laboratory #2 often involves:
i. Define the required circuit functionality using truth tables or otherwise (e.g. Boolean
functions). For synchronous counters, the present-state next-state table is employed.
ii. Use the Boolean Algebra or otherwise† to reduce the complexity of the final circuit (i.e.
reduce the number of required gates and the resulting power requirements).
iii. Implement the circuit. NB if NAND only or NOR only implementations are required
you may need to use DeMorgan’s Theorem to convert the simplified expression to is
corresponding form.

†
Karnaugh maps and Quine McClusky are alternative minimization techniques. Have a look at the
Karnaugh Map tool on the course Moodle site.

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Question 1‡

The rebel organisation in the Republic of Rif (North Africa) has requested your
expertise in redesigning a portion of their Ministry of Defence (MoD) reconciliation
circuit. The circuit is promoted as the device the will ensure lasting world peace. A
representative for the organisation has provided you with the original circuit design
(see Figure 1) and complains that it is too large to fit onto the control chip. Your role
is to determine the function that is to be implemented and to modify the original
design so as to minimise the space requirements. Unfortunately, the organisation only
has 2-Input and 3-Input NAND gates at its disposal. Be sure to show your new
design.

Republic Of Rif Official

Top Secret Document
Military Chinese Document

LED

Figure 1: MoD Circuit Diagram

‡
2010/2011 Semester II past paper

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Question 2§

A loading dock for large trucks is shaped as shown in Figure 1. Truck drivers have
been complaining to management about the severe difficulties they have been
encountering due to the blind corner at the entrance of the docking area. Management
has decided to offer an internship to a university Computer Science student to
develop a parking notification system to warn drivers when not to enter the docking
area. The proposed new system will employ four (4) proximity sensors. Each sensor
produces a high output signal when a truck is in one of the bays. A “no parking” light
at the entrance to the lot should become illuminated when the dock is full. The
constraints on the system are as follows:

i. Only three (3) trucks are allowed in the docking area at one time.
ii. If docking bays 1 and 2 are filled, no other trucks are allowed to enter.

As the lucky intern selected, your job is to design and implement the control circuit
for the proposed system. Moreover, you are limited to 2-Input NAND gates only.
Impress your employers, by ensuring that you use as few NAND gates as possible.

From Loading Dock

To Loading Dock

1 2

3 4

Figure 2 - Loading Dock Layout

Question 3**

Design a synchronous JK flip-flop counter which produces the following repeated

binary sequence: 1, 2, 4, 3, 7, 5, 6, 0.

**End of Laboratory Exercise**

§
2011/2012 Semester I past paper
**
2011/2012 Assignment Question

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