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Circuit R
Circuit R
Circuit R
STOP START
Local:2:I.Data[1].0 STOP Local:2:I.Data[1].1 MEMORY_1
0 / /
MEMORY_1
START
STOP
Local:2:I.Data[1].0 STOP MEMORY_1 CMP MEMORY_2
1 / / Compare
Expression COUNTER_1.ACC=0
MEMORY_2
MEMORY_2 TON
2 Timer On Delay EN
Timer TIMER_1
Preset 30000 DN
Accum 0
CONVEYOR 1
TIMER_1.TT Local:2:O.Data[0].0
3
CONVEYOR_1
TIMER_1.DN CTU
4 Count Up CU
Counter COUNTER_1
TIMER_2.DN Preset 3 DN
Accum 0
TIMER_3.DN
BOTTOM ARM
CMP Local:2:O.Data[0].1
5 Compare
Expression COUNTER_1.ACC=1
BOTTOM_ARM
BOTTOM ARM
Local:2:O.Data[0].1 TON
6 Timer On Delay EN
Timer TIMER_2
Preset 10000 DN
Accum 0
MIDDLE RM
CMP Local:2:O.Data[0].2
7 Compare
Expression COUNTER_1.ACC=2
MIDDLE_ARM
Logix Designer
MainRoutine - Ladder Diagram Page 2
CAPSTONE_LOGIC:MainTask:MainProgram 3/23/2024 9:51:37 PM
Total number of rungs in routine: 21 C:\Users\Rpatel77054\OneDrive - Conestoga College\rishi_capstone_logic_final.ACD
MIDDLE RM
Local:2:O.Data[0].2 TON
8 Timer On Delay EN
Timer TIMER_3
Preset 10000 DN
Accum 0
TOP ARM
CMP Local:2:O.Data[0].3
9 Compare
Expression COUNTER_1.ACC=3
TOP_ARM
TOP ARM
Local:2:O.Data[0].3 TON
10 Timer On Delay EN
Timer TIMER_4
Preset 10000 DN
Accum 0
TIMER_4.DN COUNTER_1
11 RES
STOP
Local:2:I.Data[1].0
STOP
MEMORY_5 MEMORY_5
CONVEYOR 2
Local:2:O.Data[0].4
CONVEYOR 2
Local:2:O.Data[0].4
CONVEYOR_2
PROXIMITY_SENSOR
MEMORY_3
Logix Designer
MainRoutine - Ladder Diagram Page 3
CAPSTONE_LOGIC:MainTask:MainProgram 3/23/2024 9:51:37 PM
Total number of rungs in routine: 21 C:\Users\Rpatel77054\OneDrive - Conestoga College\rishi_capstone_logic_final.ACD
CONVEYOR 2 PROBE A
TIMER_5.TT Local:2:O.Data[0].4 Local:2:O.Data[0].5
15 /
PROBE B
Local:2:O.Data[0].6
PROBE_A
PROBE_B
FEEDBACK_NOT_OK PROXIMITY_SENSOR
MEMORY_4
MEMORY_4 TON
17 Timer On Delay EN
Timer TIMER_6
Preset 10000 DN
Accum 0
BAD_PART_PUSH
FEEDBACK_OK
MEMORY_5
MEMORY_5 TON
20 Timer On Delay EN
Timer TIMER_7
Preset 10000 DN
Accum 0
(End)
Logix Designer