Unit2 - COD - Mano (Upto Computer Instructions)

Unit-02
2/13/2024 MANOJ YADAV 1

Computer Organization and Design
U-1: Overview of Digital Seq. Cir. and Implementation (4 Hrs.)
U-2: Introduction to Computer Organization (8 Hrs.)
U-3: Instruction Set Architecture and Assembly Language Prog. (8 Hrs.)
U-4: Basics of Memory Organization and Pipelining (6 Hrs.)
Dr. Manoj Yadav, Assistant Professor

Department of ICT, PDEU Gandhinagar
2/13/2024 Manoj Yadav 2

Bus-System
and
Register Transfer

Computer System Bus
o The computer system bus is the method by which data is communicated between all the
internal pieces of a computer.
o It connects the processor to the RAM, to the hard drive, to the video processor, to the I/O
drives, and to all the other components of the computer.
o Types of buses in any

processor (generally
three):
i. Control bus – is
used to control the
functional units.
ii. Address bus – is
used to transfer the
address of the data.
iii. Data bus – is used
to transfer data to
and from memory.

Computer System Bus – functions
o An address bus: this determines the location in memory that the processor will read data
from or write data to.
o A data bus: this contains the contents that have been read from the memory location or
are to be written into the memory location.
o A control bus: this manages the information flow between components indicating
whether the operation is a read or a write and ensuring that the operation happens at the
right time.

Register Transfer Language
o The operations executed on data stored in registers are called
microoperations.
o The result of the operation may replace the previous binary information
of a register or may be transferred to another register.
o Examples of microoperations are shift, count, clear, and load.
o Information transfer from one register to another is designated in

symbolic manner. (RTL)
o This can be in terms of transfer or replacement operator. For example:
o Above statement denotes a transfer of the content of register R1 into

register R2.

Representation of Registers
o A 16-bit register is partitioned into two parts in (d).
o Bits 0 through 7 are assigned the symbol L (for low byte) and bits 8
through 15 are assigned. The symbol H (for high byte). The name of the
16-bit register is PC (program counter).
o The symbol PC(0–7) or PC(L) refers to the low-order byte and PC(8–15)
or PC(H ) to the high-order byte.

Control Functions in Registers
o We want the transfer to occur only under a predetermined control
condition. This can be shown by means of an if-then statement.
o Where P is a control signal generated in the control section. A control

function is a Boolean variable that is equal to 1 or 0.
o The above statement can be rewritten as below:
o It symbolizes the requirement that the transfer operation be executed

by the hardware only if P = 1.

Hardware Schematic of Register Transfer
o Every statement written in a register
transfer notation implies a hardware
construction for implementing the
transfer.
o The block diagram that depicts the

transfer from R1 to R2. n-outputs of
register R1 are connected to the n-inputs
of register R2. Register R2 has a load
input that is activated by the control
variable P.
o In the timing diagram, P is activated in

the control section by the rising edge of a
clock pulse at time t.
o The next positive transition of the clock
at time t+1 finds the load input active and
the data inputs of R2 are then loaded
into the register in parallel.
Symbols of Register Transfer Notation
o Registers are denoted by capital letters, and numerals may follow the letters.
o Parentheses are used to denote a sub-part of a register by specifying the range

of bits or by giving a symbol name to a portion of a register.
o The arrow denotes a transfer of information and the direction of transfer.
o A comma is used to separate two or more operations that are executed at the
same time. The statement: denotes an operation that exchanges
the contents of two registers during one common clock pulse if T=1.

Problem – 01
o Registers Show the block diagram of the hardware that implements the
following register transfer statement:
y.T2: R2← R1, R1 ←R2

Problem – 01: Solution
o Control signal y.T2 can be implemented by AND gate and is common to both the
registers.
o As soon as load is activated, contents of R1 and R2 gets exchanged with each
other.

Bus and Memory Transfer
o A typical digital computer has many registers, and paths must be provided to
transfer information from one register to another.
o The number of wires will be excessive if separate lines are used between each
register and all other registers in the system. Therefore, a more efficient scheme
for transferring information between registers in a multiple-register configuration
is a common bus system.
o A bus structure consists of a set of common lines, one for each bit of a
register, through which binary information is transferred one at a time.
o One way of constructing a common bus system is with multiplexers. (we have
already studied it, lets revise it again)

Bus System for 4-Registers
o Depending on selection lines values chosen, data of a register is made available
to the 4-line common bus.

1- Line Bus System Using decoder
o As we have already studied, bus system can be built using decoders also. The
data transfer commands are equally true as in case of other bus as previous one.

Transfer Statements applied to Common Bus
o The symbolic statement for a bus transfer may mention the bus or its
presence may be implied in the statement. When the bus is included in
the statement, the register transfer is symbolized as follows:
o The content of register C is placed on the bus, and the content of the bus
is loaded into register R1 by activating its load control input.
o If the bus is known to exist in the system, it may be convenient just to

show the direct transfer.

Memory Transfer: Read Operation
o The transfer of information from a memory word to the outside
environment is called a read operation.
o The transfer of new information to be stored into the memory is called

a write operation.
o A memory word will be symbolized by the letter M. The particular

memory word among the many available is selected by the memory
address during the transfer.
o Consider a memory unit that receives the address from a register, called
the address register, symbolized by AR.
o The data are transferred to another register, called the data register,
symbolized by DR.
o Read operation statement can be given as below:

Microoperations

Microoperations
o A microoperation is an elementary operation performed with the data
stored in registers.
o The microoperations most often encountered in digital computers are

classified into four categories:
• Register transfer microoperations transfer binary information from
one register to another.
• Arithmetic microoperations perform arithmetic operation on
numeric data stored in registers.
• Logic microoperations perform bit manipulation operations on
nonnumeric data stored in registers.
• Shift microoperations perform shift operations on data stored in
registers.

Arithmetic Microoperations: Add Micro-op
o The basic arithmetic microoperations are addition, subtraction,
increment, decrement, and shift.
o The arithmetic microoperation defined by the statement specifies an

add microoperation:
o Above states that the contents of register R1 are added to the contents
of register R2 and the sum transferred to register R3.
o For hardware implementation: To implement this statement with

hardware we need three registers and the digital component (adder)
that performs the addition operation.

Arithmetic Microoperations: Subtraction
o Subtraction is most often implemented through complementation and
addition.
o Instead of using the minus operator, we can specify the subtraction by
the following statement: subtraction microoperation:
o 𝑅2 is the symbol for the 1’s complement of R2.

o Adding 1 to the 1’s complement produces the 2’s complement.
o Adding the contents of R1 to the 2’s complement of R2 is equivalent
to R1 - R2.

Arithmetic Microoperations: Others
o The increment and decrement microoperations are symbolized by plus-
one and minus-one operations, respectively.
o These microoperations are implemented with a combinational circuit

or with a binary up-down counter.
o In most computers, the multiplication operation is implemented with

a sequence of add and shift microoperations. Division is implemented
with a sequence of subtract and shift microoperations.

Hardware Implementation of Add Micro-op.
o To implement the add microoperation with hardware, we need the
registers that hold the data and full-adders. An n-bit binary adder
requires n full-adders.
o Let’s understand by example of 4-bit adder circuit operation as given
below:
o Firstly, at stage-0 (from left-side): LSB bits A0 and B0 are added with
carry C0. Resulting sum is S0 and C1 is the carry generated and is input to
stage-1.
o The similar operation (as in stage-0 case) is repeated at all the stages viz.
stage – 1, 2 or 3.

Hardware Implementation of Add Micro-op.
o The n data bits for the A inputs come from one register (such as R1),
and the n data bits for the B inputs come from another register (such
as R2). The sum can be transferred to a third register, R3 or to one of
the source registers (R1 or R2), replacing its previous content.

Hardware Implementation of Add-Subtract
o The addition and subtraction operations can be combined into one
common circuit by including an exclusive-OR gate with each full-
adder.
o The mode input M controls the operation. When M=0 the circuit is an
adder and when M=1 the circuit becomes a subtractor.

Hardware Implementation of Subtraction
o The subtraction of binary numbers can be done the most conveniently

by means of complements as discussed in previous slides.
o Remember that the subtraction A-B can be done by taking the 2’s
complement of B and adding it to A.
o The 2’s complement = 1’s complement + 1 (to LSB pair).
o When M=1, we have B⊕1=B’ and C0=1. The B inputs are all
complemented and a 1 is added through the input carry. Therefore, now
the circuit performs the operation: A + 2’s complement of B.

Hardware Implementation of Increment
o The increment microoperation adds one to a number in a register.

Hardware Implementation of Increment
o One of the inputs to the least significant half-adder (HA) is
connected to logic-1 and the other input is connected to the LSB of the
number to be incremented.
o The output carry from one half-adder is connected to one of the

inputs of the next-higher-order half-adder.
o The circuit receives the four bits from A0 through A3, adds 1 to it,
and generates the incremented output in S0 through S3.
o The output carry C4 will be 1 only after incrementing binary 1111. This
also causes outputs S0 through S3 to go to 0.
o This circuit can be extended to an n-bit binary incrementor by

extending the diagram to include n half-adders.
H/W Implementation of Arithmetic Ckt (All)
Fig. a

H/W Implementation of Arithmetic Ckt (All)
o Table showing the multi-functional arithmetic circuit which can
implement so many arithmetic microoperations all together.
o For example: When S1S0 = 00, the value of B is applied to the Y inputs
of the adder. And, if Cin=0, the output D=A+B.
o If Cin=1, output D=A+B+1. Both cases perform the add
microoperation with or without adding the input carry.

Logic Microoperations
o Logic microoperations specify binary operations for strings of bits
stored in registers. These operations consider each bit of the register
separately and treat them as binary variables.
o For example: the exclusive-OR microoperation with the contents of

two registers R1 and R2 is symbolized by the statement:
o It specifies a logic microoperation to be executed on the individual

bits of the registers only if control variable P=1.

Logic Microoperations
o For example: Let the content of R1 be 1010 and the content of R2 be

1100.
o The exclusive-OR microoperation stated in previous slide symbolizes

the following logic computation:
o Bit-wise exclusive-OR microoperation is performed.

Logic Microoperations:
o Several logic operations with their symbols listed below in the table:

Hardware for Logic Microoperations: Example
o The following show how the bits of one register (designated by A) are
manipulated by logic microoperations as a function of the bits of
another register (designated by B).
Fig. b

o In a typical application, register A is a processor register and the bits of
register B constitute a logic operand extracted from memory and stored
in register B.
o The selective-set operation sets to 1 the bits in register A where there are
corresponding 1’s in register B. It does not affect bit positions that have 0’s
in B. For example: following numerical can clarify this operation:
o From the truth table, we note that the bits of A after the operation are
obtained by the logic-OR operation of bits in B and previous values of A
(and when S1S0=01). Therefore, the OR microoperation can be used to
selectively set the bits of a register.
o Therefore, many other logic manipulation can be done on processor register
A.
o In a typical application, register A is a processor register and the bits
of register B constitute a logic operand extracted from memory and
stored in register B.
o The selective-set operation sets to 1 the bits in register A where there

are corresponding 1’s in register B. It does not affect bit positions that
have 0’s in B.
o For example: following numerical can clarify this operation:
o From the truth table we note that the bits of A after the operation are
obtained from the logic-OR operation of bits in B and previous values of
A. Therefore, the OR microoperation can be used to selectively set bits
of2/13/2024
a register. Manoj Yadav 36
Shift Microoperations
o A logical shift is one that transfers 0 through the serial input. The
symbols shl and shr for logical shift-left and shift-right microoperations.
For example:
o The bit transferred to the end position through the serial input is
assumed to be 0 during a logical shift.

Hardware Implementation: Shifter Circuit
o When the selection input S=0, the input data are shifted right (down in
the diagram). When S=1, the input data are shifted left (up in the
diagram).

Arithmetic Logic Shift Unit: ALU Design
o To perform microoperation, the
contents of specified registers
are placed in the inputs of the
common ALU. The ALU
performs an operation, and the
result of the operation is then
transferred to a destination Fig. a
register.
o The ALU is a combinational

circuit so that the entire register
Fig. b
transfer operation from the
source registers through the
ALU and into the destination o The arithmetic, logic, and shift circuits introduced in
previous sections can be combined into one ALU with
register can be performed during common selection variables.
one clock pulse period.
o Table below lists the 14 operations of the ALU.

o In above table, 14 operations of the ALU can be performed.
o Among them, the first eight are arithmetic operations (see Table) and
are selected with S3S2 = 00.
o The next four are logic operations (see Fig. b) and are selected with
S3S2 = 01.
o The input carry has no effect during the logic operations and is
marked with don’t-care (×) conditions.
o The last two operations are shift operations and are selected with S3S2 =
10 and 11.
o The other three selection inputs have no effect on the shift.

Problems based on
above lectures of U-2

Problem – 02

Problem – 02 : Solution

Problem – 03

o You already have studied about ‘register transfer statement’
o So, the solution would be represented like following:
P: R1 R2
P’.Q: R1 R3

Problem – 04
o Draw a diagram of a bus system similar to the 4-bit bus line using
MUX, but use three-state buffers and a decoder instead of the
multiplexers.


Problem – 05
o A digital computer has a common bus system for 16 registers of 32

bits each. The bus is constructed with multiplexers.
i. How many selection inputs are there in each multiplexer?
ii. What size of multiplexers are needed?
iii. How many multiplexers are there in the bus?

o A digital computer has a common bus system for 16 registers of 32

bits each. The bus is constructed with multiplexers.
i. How many selection inputs are there in each multiplexer?
Ans: 4 selection lines to select one of 16 registers.
ii. What size of multiplexers are needed?
Ans: 16 × 1 multiplexers.
iii. How many multiplexers are there in the bus?
Ans: 32 multiplexers, one for each bit of the registers.

Problem – 06


Instruction Codes

Instruction Set Architecture: Introduction
o The organization of the computer is defined by its internal registers,

the riming and control structure, and the set of instructions that it uses.
o The internal organization of a digital system is defined by the sequence

of microoperations it performs on data stored in its registers.
o The user of a computer can control the process by means of a program.

A program is a set of instructions that specify the operations,
operands, and the sequence by which processing has to occur.
o A computer instruction is a binary code that specifies a sequence of

microoperations for the computer.

Instruction Set Architecture: Introduction
o A computer instruction is a binary code that specifies a sequence of
microoperations for the computer. Instruction codes together with data
are stored in memory.
o The computer reads each instruction from memory and places it in a

control register.
o The control then interprets the binary code of the instruction and
proceeds to execute it by issuing a sequence of microoperations.
o Therefore, an instruction code is a group of bits that instruct the

computer to perform a specific operation.
o It is usually divided into parts, each having its own specific

interpretation. The most basic part of an instruction code is its
operation part.
Instruction Code: Stored Program Organization
o Operation code of an instruction is a group of bits that define such operations as add,
subtract, multiply, shift, and complement.
o The operation code must consist of at least n-bits for a given 2n (or less) distinct
operations.
o The operation must be performed on some data stored in processor registers or in

memory.
o An instruction code must therefore specify not only the operation but also the registers or
the memory words where the operands are to be found, as well as the register or memory
word where the result is to be stored. Memory words can be specified in instruction
codes by their address.
o Processor registers can be specified by assigning to the instruction another binary code of
k bits that specifies one of 2k registers.

o The simplest way to organize a
computer is to have one
processor register and an
instruction code format with
two parts.
o The first part specifies the

1) operation to be performed
and second specifies an
2) address.
o Memory address tells the

control where to find an
operand in memory.
o This operand is read from

memory and used as the data to
be operated on together with
the data stored in the
processor register.
o (See Fig. in previous slide), Instructions are stored in one section of
memory and data in another.
o For a memory unit with 4096 words we need 12 bits to specify an
address since 212 = 4096.
o If we store each instruction code in one 16-bit memory word, we have
available four bits for the operation code (abbreviated opcode) to
specify one out of 16 possible operations, and 12 bits to specify the
address of an operand.
o The control reads a 16-bit instruction from the program portion of
memory. It uses the 12-bit address part of the instruction to read a 16-
bit operand from the data portion of memory. It then executes the
operation specified by the operation code.
o The operation is performed with the memory operand and the content of
Accumulator (AC), the processor register.

Concept of Instruction Cycle
o The above graphic animation illustrates typical operation of an instruction by

the processor.
o It places the contents of the instruction pointer onto the address bus and
fetches the instruction.
o Once decoded, the instruction is executed, and the instruction pointer altered to
point to the next instruction.
Modified Instruction Format
o When the second part specifies the address
of an operand, the instruction is said to have
a direct address.
o In Fig., it consists of a 3-bit operation code, a
12-bit address, and an indirect address
mode bit designated by I. The mode bit is 0
for a direct address and 1 for an indirect
address.
o When mode bit I=1, it is recognized as an
indirect address instruction. The address
part is the binary equivalent of 300. The
control goes to address 300 to find the
address of the operand. The address of the
operand in this case is 1350. The operand
found in address 1350 is then added to the
content of AC.
Computer Registers

Computer Registers
o Computer instructions are normally stored in consecutive memory
locations and are executed sequentially one at a time.
o The control reads an instruction from a specific address in memory and
executes it. It then continues by reading the next instruction in sequence
and executes it, and so on.
o This type of instruction sequencing needs a counter to calculate the
address of the next instruction. Program counter holds address of next
instruction.
o It is also necessary to provide a register in the control unit for storing the
instruction code after it is read from memory. The instruction read from
memory is placed in the instruction register (IR).
o The data register (DR) holds the operand read from memory.
o The accumulator (AC) register is a general-purpose processing register.
o Temporary register (TR) is used for holding temporary data during the
processing.
Computer Registers
o The memory address register (AR) has 12 bits since this is the width of
a memory address.
o The program counter (PC) also has 12 bits, and it holds the address of
the next instruction to be read from memory after the current
instruction is executed.
o The PC goes through a counting sequence and causes the computer to read
sequential instructions previously stored in memory.

Sizes of different Registers
o Basic computer registers and memory.

Bus Design using Different Registers and Memory
o The basic computer has eight
registers, a memory unit, and a
control unit (to be discussed
later).
o Paths must be provided to
transfer information from one
register to another and between
memory and registers.
o The connection of the registers
and memory of the basic
computer to a common bus
system is shown in Fig. (on right)
o Selection variables S2, S1, and S0
decides that which output to be
available on the bus-line.
Bus Design using Different Registers and Memory
o For example, the number along the output of DR is 3. The 16-bit outputs
of DR are placed on the bus lines when S2S1S0 = 011.
o The lines from the common bus are connected to the inputs of each register
and the data inputs of the memory.
o Now, if LD (load) input of a particular register is enabled, it receives the
data from the bus during the next clock pulse transition. Also, memory
receives the contents of the bus when its write input is activated. The
memory places its 16-bit output onto the bus when the read input is
activated and S2S1S0 = 111.
o Two registers, AR and PC, have 12 bits each since they hold a memory
address. When the contents of AR or PC are applied to the 16-bit common
bus, the four most significant bits are set to 0’s. When AR or PC receive
information from the bus, only the 12 least significant bits are
transferred into the register.
o INPR receives a character from an input device which is then transferred to
AC.
Computer Instructions

Basic Computer Instruction Formats
o The basic computer has three instruction code formats, as shown in Fig.
below. Each format has 16 bits.
o A memory-reference instruction uses 12 bits to specify an address and
one bit to specify the addressing mode I. The register reference
instructions are recognized by the operation code 111 with a 0 in the
leftmost bit (bit 15) of the instruction. A register-reference instruction
specifies an operation on the AC register.

o Similarly, an input–output instruction does not need a reference to
memory and is recognized by the operation code 111 with a 1 in the
leftmost bit of the instruction.
o The remaining 12 bits are used to specify the type of input–output
operation or test performed.
o In summary, the type of instruction is recognized by the computer

control from the four bits in positions 12 through 15 of the instruction.
o Control first verifies three bits from 12th to 14th , if it is not 111;
instruction type is memory-reference instruction.
o If 12th to 14th , if it is111 then control checks for I value. If I = 0, it is
register – reference instruction. And, If I = 1, it is Input – output
instruction. (see Fig. on previous slide)
o Note: symbol I is not used as a mode bit when operation code is 111.
o In previous discussion, only three bits of the instruction are used for the
operation code.
o Therefore, it may seem that the computer is restricted to a maximum of

eight distinct operations.
o However, since register-reference and input–output instructions use the

remaining 12 bits as part of the operation code, the total number of
instructions can exceed eight.
o The total number of instructions chosen for the basic computer is equal
to 25.

Instruction Set Completeness
o The instructions for the computer are listed in Table on previous slide.
o The symbol designation is a three-letter word and represents an
abbreviation intended for programmers and users.
o The hexadecimal code is equal to the equivalent hexadecimal number of
the binary code used for the instruction.

Memory reference instructions
o Total 16-bits instruction including I-bit, opcode and address.

Register reference Instruction
o Total 16-bits instruction including I=0, opcode = 111 and other bits for
address.

I/O operations
o Total 16-bits instruction including I=1, opcode = 111 and other bits for
address.

Problem – 07

o References to solve problem:

o References to solve problem:

Control Unit
of
Basic Computer

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Unit-02

2/13/2024 MANOJ YADAV 1

Dr. Manoj Yadav, Assistant Professor

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o Types of buses in any

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o Examples of microoperations are shift, count, clear, and load.

o Information transfer from one register to another is designated in

o Above statement denotes a transfer of the content of register R1 into

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o Where P is a control signal generated in the control section. A control

o The above statement can be rewritten as below:

o It symbolizes the requirement that the transfer operation be executed

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o The block diagram that depicts the

o In the timing diagram, P is activated in

o Parentheses are used to denote a sub-part of a register by specifying the range

o The arrow denotes a transfer of information and the direction of transfer.

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y.T2: R2← R1, R1 ←R2

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o If the bus is known to exist in the system, it may be convenient just to

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o The transfer of new information to be stored into the memory is called

o A memory word will be symbolized by the letter M. The particular

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o The microoperations most often encountered in digital computers are

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o The arithmetic microoperation defined by the statement specifies an

o For hardware implementation: To implement this statement with

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o 𝑅2 is the symbol for the 1’s complement of R2.

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o These microoperations are implemented with a combinational circuit

o In most computers, the multiplication operation is implemented with

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o The subtraction of binary numbers can be done the most conveniently

o The 2’s complement = 1’s complement + 1 (to LSB pair).

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o The output carry from one half-adder is connected to one of the

o This circuit can be extended to an n-bit binary incrementor by

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o For example: the exclusive-OR microoperation with the contents of

o It specifies a logic microoperation to be executed on the individual

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