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18-Memory Design-07-02-2023
18-Memory Design-07-02-2023
RAM CHIPS
• Features:
• RAM Chips is suited for the communication with
the CPU if it has one or more control inputs that
select the chip only when needed
• Bidirectional Databus – that allows the data either
from CPU to memory or memory to CPU
• Bidirectional Data Bus can be constructed with
three state Buffers
» Logic 0
» Logic 1
» High Impedence state
Memory Block Diagram
• A basic memory n Data Input Lines
system is shown here: n
Decoder
• RAM and ROM
3 2 1 0 chips are
CS1
CS2
connected to a
Data
RD 128 x 8
RAM 1
CPU through the
WR
AD7
data and address
buses
CS1
CS2 • The low-order
Data
RD 128 x 8
RAM 2
lines in the
WR
AD7
address bus
select the byte
CS1 within the chips
CS2
Data
RD 128 x 8 and other lines in
RAM 3
WR the address bus
AD7
select a particular
CS1 chip through its
CS2
RD 128 x 8 Data chip select inputs
RAM 4
WR
AD7
CS1
CS2
Data
1- 7 512 x 8
8
9 } AD9 ROM
Memory Design
How many 1024x 8 RAM chips are needed to provide a memory capacity of 2048 x 8?
Case 1:
If NI > N & WI = W
NI
Increase number of words by the factor of p =
N
How many 1024x 4 RAM chips are needed to provide a memory capacity of 1024 x 8?
Case 2:
If NI = N & WI > W
I
Increase the word size of a Memory by a factor of q = W
W
How many 1024x 4 RAM chips are needed to provide a memory capacity of 2048 x 8?
Case 3:
If NI > N & WI > W
Increase number of words by the factor of p &
Increase the word size of a Memory by a factor of q
Memory design – Increasing the word size
• Problem - 1
• Design 128 × 16 - bit RAM using 128 × 4 - bit RAM
• Solution: p = 128 / 128 = 1; q = 16 / 4 = 4
• Therefore, p × q = 1 × 4 = 4 memory chips of size 128 × 4 are
required to construct 128 × 16 bit RAM
From To 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data Bus
16
4 4 4 4
Data (0-3) Data (0-3) Data (0-3) Data (0-3)
Read/write Control
Memory Design
Data r/w
6-0
16
7
4 4 4 4
1
Memory Design – Increasing the number of
words
• Problem - 2
• Design 1024 × 8 - bit RAM using 256 × 8 - bit RAM
• Solution: p = 1024 / 256 = 4; q = 8 / 8 = 1
• Therefore, p × q = 4 × 1 = 4 memory chips of size 256 × 8 are required
to construct 1024 × 8 bit RAM
1024
1 RAM 256 × 8 4 1 4 8 2 0 10
×8
2
3
4
Memory Address Map
Component Hexadecimal address Address Bus
From To 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data
Address Bus 256 × 8 Bus
0 8 RAM 8
1
A8 CS R/W
2×4 2
A9 decoder
Data
3 Address Bus 256 × 8 Bus
8 RAM 8
CS R/W
Data
Address Bus 256 × 8 Bus
8 RAM 8
CS R/W
8 R/W
Data
Bus
Design with gates
Data
8 Address Bus 256 × 8 Bus
Address Bus 8 RAM 8
A9 A8 A0 – A7 R/W
CS
Data
Address Bus 256 × 8 Bus
8 RAM 8
CS R/W
Data
Address Bus 256 × 8 Bus
8 RAM 8
CS R/W
Data
Address Bus 256 × 8 Bus
8 RAM 8
CS R/W
8 R/W
Data
Bus
256 × 8
Data
987-0 RAM 1 r/w
8
8
256 × 8
RAM 2
8
2×4
Decoder
256 × 8
3 2 1 0 RAM 3
256 × 8
RAM 4
8
Memory Design
• Problem - 3
• Design 256 × 16 – bit RAM using 128 × 8 – bit RAM
chips
S.NO Memory NxW N 1 x W1 P q p*q x y z Total
4
Memory Address Map
Component Hexadecimal address Address Bus
From To 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address Bus
128 × 8 128 × 8
RAM 1.1 RAM 1.2
1×2
Decoder
1 0
16
8
8
128 × 8 128 × 8
RAM 2.1 RAM 2.2
16
8
8
Memory Design
• Problem - 4
• Design 256 × 16 – bit RAM using 256 × 8 – bit RAM chips
and 256 × 8 – bit ROM using 128 × 8 – bit ROM chips.
S.NO Memory NxW N1 x W1 P q p*q x y z Total
256 × 256 ×
1 RAM 1 2 2 8 0 1 9
8 16
128 ×
2 Rom 256 × 8 2 1 2 7 1 1 9
8
3
4
Memory Address Map
Component Hexadecimal address Address Bus
From To 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1×2 1×2 8
Decoder Decoder
1 0 1 0
128 × 8
ROM 2
●
256 × 8 256 × 8
RAM 1.1 RAM 1.2
16
8
8
Example 1
A computer employs RAM chips of 1024 x 8 and ROM chips of
2048 x 4. The computer system needs 2K x 16 of RAM, and 2K x 16
ROM and an interface unit with 256 registers each. A memory-
mapped I/O configuration is used. The two higher -order bits of the
address bus are assigned 00 for RAM, 01 for ROM, and 10 for
interface..
a). How many RAM and ROM chips are needed?
b). Draw a memory-address map for the system and Give the address range in
hexadecimal for RAM, ROM