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74ACT373
74ACT373
January 2008
74AC373, 74ACT373
Octal Transparent Latch with 3-STATE Outputs
Features General Description
■ ICC and IOZ reduced by 50% The AC/ACT373 consists of eight latches with 3-STATE
■ Eight latches in a single package outputs for bus organized system applications. The flip-
■ 3-STATE outputs for bus interfacing
flops appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is LOW, the data that meets the
■ Outputs source/sink 24mA
setup time is latched. Data appears on the bus when the
■ ACT373 has TTL-compatible inputs Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Ordering Information
Package
Order Number Number Package Description
74AC373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT373MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74ACT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
IEEE/IEC
Pin Description
Pin Names Description
D0–D7 Data Inputs
LE Latch Enable Input
OE Output Enable Input
O0–O7 3-STATE Latch Outputs
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Capacitance
Symbol Parameter Conditions Typ. Units
CIN Input Capacitance VCC = OPEN 4.5 pF
CPD Power Dissipation Capacitance VCC = 5.0V 40.0 pF
13.00
12.60 A
11.43
20 11
B
9.50
10.65 7.60
10.00 7.40
2.25
1 10 0.65
PIN ONE 0.51 1.27 1.27
INDICATOR 0.35
0.25 M C B A
LAND PATTERN RECOMMENDATION
0.33
C 0.20
0.10 C
0.30
0.75 0.10 SEATING PLANE
X 45°
0.25
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
GAGE PLANE
(R0.10) MS-013, VARIATION AC, ISSUE E
0.25 B) ALL DIMENSIONS ARE IN MILLIMETERS.
8°
0° C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
1.27 D) CONFORMS TO ASME Y14.5M-1994
0.40 SEATING PLANE E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
(1.40) DETAIL A F) DRAWING FILENAME: MKT-M20BREV3
SCALE: 2:1
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
26.92
24.89
PIN #1 7.11
6.09
3.43
(0.97) 1.78 3.17 7.87
7° TYP
5.33 MAX
1.14
7° TYP
2.54 3.55
0.36 3.17 7.62
0.56 0.38 MIN 10.92 MAX
0.20
0.35
.001[.025] C
NOTES:
Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
Figure 5. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
Authorized Distributor
Fairchild Semiconductor:
74ACT373MSA_Q 74ACT373SC_Q 74AC373MTC_Q 74ACT373PC_Q 74AC373SCX 74AC373SJX 74AC373SJ
74AC373PC 74AC373SC 74AC373MTC 74AC373MTCX 74ACT373MTC_Q 74AC373PC_Q 74AC373SJ_Q
74AC373SC_Q