Q 1.

a List the types of Verilog modeling. Write a short note on each model
b Write the Verilog code for full subtractor using gate-level modeling, simulate, and download to the FPGA kit

c Implement D and T Flip flops using JK flip flops in digital trainer kit
d Write the brief classification of A/D and D/A converters. And also write a brief classification of memories

Q 2.

a List the types of Verilog modeling. Write a short note on each model
b Write the Verilog code for 1:4 Demux using data flow modeling, simulate, and download to the FPGA kit
c Construct and verify the working of the 4-bit SISO shift register using a suitable IC in a digital trainer kit
d Write the brief classification of A/D and D/A converters. And also write a brief classification of memories

Q 3.

a List the types of Verilog modeling. Write a short note on each model
b Write the Verilog code, simulate, and download to FPGA kit for a 4-bit ALU with any 2 arithmetic and logical
operations
c Construct and verify the working of the Johnson counter using suitable IC in the digital trainer kit
d Write the brief classification of A/D and D/A converters. And also write a brief classification of memories

Q 4.

a List the types of Verilog modeling. Write a short note on each model
b Write the Verilog code, simulate, and download to FPGA kit for T flip flop
c Construct and verify the working of the 3-bit ripple counter using IC 7476
d Write the brief classification of A/D and D/A converters. And also write a brief classification of memories

Q 5.

a List the types of Verilog modeling. Write a short note on each model
b Write the Verilog code, simulate, and download to FPGA/CPLD kit for an up/down counter using behavioral
modelling
c Construct and verify the working of the 4-bit SIPO shift register using suitable IC in the digital trainer kit
d Write the brief classification of A/D and D/A converters. And also write a brief classification of memories

Q 6.

a List the types of Verilog modeling. Write a short note on each model
b Write the Verilog code for 4:1 MUX using data flow modelling, simulate, and download to FPGA kit
c Construct and test clocked SR Flip flop using NAND gates in a digital trainer kit.
d Write the brief classification of A/D and D/A converters. And also write a brief classification of memories