A Survey on System-on-a-Chip Design Using
Chisel HW Construction Language
IECON 2021 - 47th Annual Conference of the IEEE Industrial Electronics Society | 978-1-6654-3554-3/21/$31.00 ©2021 IEEE | DOI: 10.1109/IECON48115.2021.9589614
Matti Käyrä, Timo D. Hämäläinen
Computing Sciences, Tampere University, Finland
matti.kayra@tuni.fi, timo.hamalainen@tuni.fi
Abstract—This paper presents a survey of functional pro-
gramming languages in System-on-a-Chip (SoC) design. The
motivation is improving the design productivity by better source
code expressiveness, increased abstraction level in design entry,
or improved automation. The survey focuses on Chisel that is one
of the most potential High Level Language (HLL) based design
frameworks. We include 26 papers that report implementations
ranging from IP blocks to complete chips. The result is that
functional programming languages are viable for SoC design
and can also be deployed in production use. However, Chisel
does not increase the abstraction level in a similar way as High
Level Synthesis (HLS), since it is used to create circuit generators
instead of direct descriptions. Additional benefit is that Chisel
offloads user effort from control and connectivity structures, and
makes reusability and configurability improved over traditional
Hardware Description Language (HDL) designs.
Index Terms—Survey, RTL Design, HDL, Chisel, FPGA, ASIC
I. I NTRODUCTION
System-on-Chips (SoC) include large number of Intellectual
Property (IP) Blocks that are often organised as subsystems
by function, speed or connectivity. Despite the growing com-
plexity, majority of the design work has still been done using
HW Description Languages (HDL) at Register Transfer Level
(RTL) abstraction. The reason is that the tools from RTL
description to netlist synthesis and ASIC backend tasks are
well established and not reasonable for a normal user to
change.
VHDL and Verilog HDLs were originally used for much
smaller ASIC designs and IPs, but large SoCs require much
more configurability and capability to manage masses of sig-
nals, IP blocks and special blocks like on-chip memories and
mixed-signal off-chip interfaces. In addition, the SoC design
must have different views: modular and hierarchical for human
designer comprehension, divisible to parts for verification like
emulation on several FPGA boards, and finally flattened to
physical placement and routing in silicon. As a result, the
total HDL lines of code and number of files in projects have
exploded and became difficult to change and maintain.
The solution has been heavy use of scripts in addition
to HDL itself to automate especially design configurations,
finally leading to HDL code generation. Therefore, several
proposals have been made to increase the design abstraction
above RTL even though all of them generate RTL HDL code
at the end. The proposals can be categorized as follows:
• Improve code expressiveness. Less lines of code (LoC)
but the abstraction might still be similar to RTL. Useful
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also in writing HDL code generators. In the worst case
HDL constructs are described as such just using other
language
• Increase abstraction level. Description omits low-level
constructs like clock cycle. This requires pre-made li-
braries or code templates that implement low-level con-
structs
• Visualize the design entry. Model Driven Development
(MDD) based methods like UML diagrams are used
to express the design intent. These have been studied
extensively but not gained popularity because graphical
models are difficult to maintain.
Other aspect is to orthogonalize structure, functionality and
configuration management that might be mixed in plain HDL
project files.
Well known High-Level Languages (HLL) are often pre-
ferred because they have matured development tools. However,
they are often extended to support some of the HW design
requirements, which may break the benefit of standard tools.
Out of them C++ based High-Level Synthesis (HLS) has been
mostly studied and also deployed in production use. Lahti
et. al [1] found HLS to offer higher productivity with equal
performance and area results.
In this paper, we attempt to discover another direction from
HLS: how well functional programming languages can be used
in SoC design. The research questions are
• What functional languages are proposed for SoC design
• What design aspects they address
• How easy they are to adopt (tool maturity, usability)
• How complex SoC designs have been designed using
them
We are not aware of many surveys on the research questions.
One paper was published in 2012 for functional HW language
history [2]. Therefore, this paper provides a current update
on the questions that have great interest in SoC industry.
Our interest is through SoC-HUB project [3] that attempts
improving the SoC design productivity with real prototype
chips.
This paper is structured as following: First, Section II gives
an overview of the HLL solutions above HDL, and motivates
our selection of Chisel as the target for the survey. Section
III gives the evaluation criteria for the publications in survey,
and summarizes the findings. Lastly, Section IV concludes the
 TABLE I
S UMMARY OF FEATURES IN HLL AND SIMILAR DEVELOPMENT FRAMEWORKS .

HLL or Support
Base Initial Paradigm Test
development design Output Tools
language publication support Framework
framework orthogonalization
Architecture
Genesis2 [4] SystemVerilog 2012 configuration OOP HDL No Open source
functionality
Architecture
MyHDL [5] Python 2003 configuration FP, OOP HDL functional Open source
functionality
Architecture
Clash [6] Haskell 2009 configuration FP HDL functional Open source
functionality
HardCaml [7] OCaml 2014 - other HDL functional Open source
Architecture HDL Base
Veriscala [8] Scala 2019 configuration FP ,OOP +driver functional language
functionality (FPGA) tools
C/++, HDL
emulation
SDAccel [9] openCL, 2014 Architecture FP, OOP + driver Commercial
and FPGA
RTL (FPGA)
To be open
Kamel [10] IP-XACT 2020 Architecture other HDL No
source
Most Architecture
Generally
HLS [1], [11] prominently 1970s configuration FP, OOP HDL functional
commercial
C-based functionality
Architecture
HDL,
Chisel [12] Scala 2012 configuration FP, OOP functional Open source
FIRRTL
functionality

findings and discusses use of functional languages in real SoC
designs.
II. HLL P ROPOSALS
Table I presents potential HLL frameworks for SoC design
in order to narrow the search space and select the most po-
tential one for this survey. We consider the following criteria:
• Orthogonalization of design aspects, enabling division
between functionality, architecture and product configu-
rations
• Programming paradigm, e.g. object-oriented program-
ming (OOP), functional programming (FP) or specific
Model of Computation (MoC) if any
• Output readiness for implementation, e.g. RTL code,
driver SW, or intermediate representation
• Abstraction level of the tests and tool support
We are especially interested in availability of the tools
and prefer open source proposals. In addition, the output
should be usable for ASIC and FPGA synthesis without further
code transforms. We also consider the level of automation by
assessing how control structures are generated from higher
abstraction descriptions or if they are expressed easier in HLL
than HDL.
A. Summary of HLL proposals
Genesis2 [4] is a SystemVerilog extension that allows
creation of parameter based circuit generators. The generators
can create complex construction sequences that are expanded
with Genesis2 compiler, which makes the HDL source code
more compact. This is not actual HLL, but a good example of
extending HDL.
MyHDL [5] is Python based HW design language. It
offers higher-level programming language that is possible to
simulate the circuit functionality without transformation to
HDL. Development and user group of the language seem to
be relatively small, but decently active. General platform for
implementing designs seem to be simulation and FPGAs but
few ASICs have been also created [13]. Additional research
has been made to extend the capabilities of myHDL platform
[14].
Clash is a HW design extension to the Haskell language.
Clash relies on an existing Haskell compiler and extends it
to allow it to perform as a HW compiler. Conceptually Clash
seem to be promising, but it is not adopted to a great extent
outside the university it was created in. [6]
Hardcaml [7] is an OCaml language based HW development
language. It offers a circuit design platform and offers a
simulation suite to test the functional design. In addition to
producing HDL code, there is a capability to output the design
in C [15]. Main implementation platform of the language
is FPGA boards. Hardcaml development is active, but there
seems to be little published outside of the developers.
SDAccel is an FPGA acceleration framework by Xilinx

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targeting their own FPGA development boards. The suite
offers automatic HW generation and architectural exploration
from the application code. The resulting system will have both
software and HW parts as well as interfacing between them.
[9]
Veriscala is a co-development framework intended to im-
plement whole integrated accelerated systems including the
application, the driver framework and the HW module. As
name suggest, it is based on Scala. Veriscala introduces a new
HW construction language, scalaHDL. This approach differs
from the many of the other platforms with inclusion of the
software directly to the development framework. Veriscala
targets FPGAs. [8]
Kamel is meta-modeling framework that extends IP-XACT
model to enable more automated IP development. Aim of
Kamel is to generate as much of the IP as possible and
reuse interfaces, to reduce amount of coding and to increase
development productivity. [10]
High-level synthesis (HLS) is a general technique that aims
to transform high-level programming code to HW. General
approach of HLS techniques have been on behavioral model-
ing with C-language which is augmented with vendor specific
libraries that can apply platform specific optimizations to the
synthesis process. [1], [11]
Chisel [12] is based on Scala as an embedded domain
specific language (DSL). It uses extensions to generate circuits
from Scala programs build with Scala compiler. Chisel has
FIRRTL internal model, which allow optimization and trans-
formations to be done to designs [16].
All of the above have potential to increase design pro-
ductivity. According to our criteria, we find three proposals
that offer most advantages: MyHDL, Clash and Chisel. All
of them offer functional paradigm support and increase circuit
design abstraction level. They also provide methods for design
orthogonalization as well as including test frameworks for
functional testing. Some prefer specific implementation type
but can freely used for ASIC and FPGA. Additionally, all
are open source and under active development [17]–[19].
However, initial exploration to publications reveal that Chisel
is by wide margin the most reported in scientific publications.
Based on these facts, Chisel is chosen as the target of the
survey.
B. Chisel Features
The following summarizes how Chisel address the aspects
of the SoC design process.
• Expressiveness: Being higher multiparadigm program-
ming language, many complex structures can be ex-
pressed in concise form.
• Abstraction: For most circuits, designer can omit clock
and reset controls. This reduces LoC and increases pos-
sibilities for reuse.
• Orthogonalization: Parameterization and separation of
design aspects help address design process.
• Visualization: Chisel language features additional tool to
express the circuit schematic in visual form. [20]
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• Test framework: Chisel has functionality testing frame-
work for rapid testing. [21]
Chisel is based on the idea of generating circuit models
rather than creating HDL-like descriptional code. This allows
Chisel designs to benefit from increased parameterization and
combined higher level programming language features, which
leads the generators to be highly reusable.
Chisel features inspectable internal model, FIRRTL. It
is intermediary representation of the HW design. FIRRTL
enables transformations and optimizations to be run more
easily on the Chisel code which results in more simplified
and optimized generated HDL. FIRRTL can be simulated to
improve verification coverage. This allows original remain
verbose so it can be more easily reused by designers. [16]
Chisel supports reusing existing HDL modules as black
boxes. This means Chisel front-end verification is not usable
on them, but through configurations allows the generated HDL
target different platforms. On top of being open source itself,
Chisel community has published lot of designs. One of the
most notable is the Rocket Chip generator [22] that creates
custom RISC-V based SoCs.
III. C HISEL S URVEY
A. Methodology
Our survey involved exploring scientific databases with
the keyword ’Chisel’. IEEE explore database gained approx-
imately 150 results. Approximately 40 papers were found to
be relevant. The survey was performed in spring 2021.
The publications were selected to include a cross section
of what type of designs are generally produced: Simple
components, more complex IP blocks, interconnects, processor
cores and full SoCs.
The publications are analyzed in detail based on reported
design experiences, details of physical chip implementation
and reports about comparison to reference designs. Additional
focus is given to Chisel highlighted use of reusable generators
and impact on designer productivity.
B. Survey results
While this analysis only targets on the publications with
actual circuit designs, there exists research on design augmen-
tation, improving verification flow, comparative studies and
even conversion from HDL to Chisel. The latter is motivated
by improving reusability for old designs.
26 publications were selected in the analysis in further de-
tail. Designs types were chosen to fill the expected component
types. Details about the surveyed designs are elaborated in
Table II.
All of the publications are recent, oldest being 6 years old.
There are 6 publications that are less than 2 years old. Hence,
it is possible to conclude that there is currently large amount
of interest in Chisel language.
The Chisel language was developed in University of Califor-
nia, Berkeley. 11 of the publications in this analysis originate
from there. This includes 6 of the 7 papers detailing full
SoC implementation. All of these detail using the Rocket
 TABLE II
S URVEYED C HISEL DESIGN DETAILS . O NLY MOST COMPLEX TARGET REPORTED IS LISTED .
Comparison Impact of Use of Other
Year of Design Target Target Challenges
Design Power to reference Chisel on parameterized benefits
Publication Type technology Frequency with Chisel
implementation productivity generators from Chisel
Version api changes,
Roughly
[23] 2018 FIFO/Arbiter FPGA 250/500 MHz - Positive Yes Verification lack of HDL feature
equal
(implemented 2019)
Better
[24] 2020 LPDC Decoder ASIC: 55nm 290 MHz - performance Positive - - -
Better area
Reusable
[25] 2019 FFT Engine FPGA 100 MHz - Equal Positive - generic -
implementation
Estimated
[26] 2015 OFDM synchronizer Sim - - - Positive - - not industry
viable
[27] 2018 Spectrometer ASIC: 28nm 530 MHz 1W - Positive Yes Verification -
FPGA: SW:
[28] 2018 Sequence aligner 130-180 MHz 3,6-30 W - - - -
Chisel+ SDAccel Better power
[29] 2018 AES Accelerator Sim - - - Positive Yes less LoC -
Bad
Mean-shift
[30] 2017 FPGA - - Worse area Positive Yes - optimization
Accelerator
results
Increased
[31] 2018 DSP Library FPGA 100 MHz - Better area - Yes -
Abstraction
Accelerator Generates to Chisel
[32] 2018 FPGA 300 MHz - - - - -
Generator Increased optimization
Generates to Chisel
[33] 2020 CNN Accelerator FPGA 30 MHz 1.5 W - - - Performance validation -
Increased optimization
Verification
[34] 2016 FFT Engine ASIC:28nm 256 MHz - Equal - Yes -
Validation
Serialization
[35] 2020 ASIC: 40nm - 1.23 W - - - - -
Accelerator
[36] 2020 Accelerator Array FPGA 322.5 MHz - - - Yes Increased optimization -
Network
[37] 2021 Processing FPGA 200 MHz - Equal Positive Yes - -
accelerator
Interconnect
[38] 2016 Embedded to [22] - - - Positive Yes - -
Generator
Bluespec:
Interconnect 50mW
[39] 2017 ASIC: 15nm 2-2.9 GHz Worse area - Yes - -
Generator @1 GHz
Worse power
Interconnect
[40] 2020 Sim - - - Positive Yes less LoC -
Generator
Interconnect
[41] 2016 FPGA 125 MHz - - Positive Yes - -
Generator
11 ASICs
Rocket SoC 25-100MHz
[22] 2016 by 2016 - - Positive Yes - -
Generator on FPGA
45nm and 28nm
[42] 2019 SoC ASIC: 16nm 400 MHz 133.5 mW - - Yes Verification -
[43] 2017 SoC ASIC: 16nm 940 MHz 22.6 mW - - Yes Verification -
90- 24-
[44] 2019 SoC ASIC: 65nm - Positive - - -
510 MHz 355 mW
[45] 2017 SoC ASIC: 45nm 900 MHz - - - Yes - -
[46] 2019 SoC ASIC: 28nm 1 GHz - - Positive Yes - -
[47] 2016 SoC ASIC: 28nm 961 MHz 173 mW - Positive Yes - -

chip generator. While this skews the result out of being truly
objective towards the language in most complex use case, it
showcases a result how reusable the generator based structure
can be.
Rocket chip uses RISC-V architecture and allows either in-
order or out-of-order versions. The last SoC paper featured
configurable RISC-V core of their own design. We can con-
clude that in the survey results are 3 configurable variations
of RISC-V cores. As this core type is the most prominent
open source core architecture, lack of core variations is not
considered a flaw in survey results.
Of detailed 26 design papers, 12 reported ASIC and 10
FPGA as their primary target. On top of this, Rocket Chip gen-
erator technical report details that another 11 ASICs included
core generated with it by its release [22]. Though, one of the
analyzed publications [47] present one of those in more detail.
Not counting the additional chips in the technical report, 7 of
the 11 ASIC implementations were created in Berkeley. ASIC
implementations were featured accelerators, interconnects and
SoCs for both Chisel creators and external users. This gives
confidence in Chisel ASIC implementation as it is not only
the developers who report of having such target.
Implemented frequency of both FPGA and ASIC designs
varied greatly, latter being up to nearly 3 GHz. This confirms
that Chisel code can be used to create high speed SoCs. Many
things contribute to frequency, but it seems that Chisel is in
this domain just as capable as HDLs.
Power used by chips varied to a large extend depending on
their application and target technology. Few papers denoted
their design being of low-power or energy efficient solution.
There is not enough data to draw definitive conclusions, but
it would seem like on this domain Chisel code can be just as
efficient as RTL.
Some of the papers listed details about comparison to

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 TABLE III used as part of existing design flows. This can be further
S UMMARY OF SURVEY DETAILS . confirmed by inspecting system level descriptions. There is
Feature appears in % fully Chisel based designs and mixed language integration
Increased productivity 15 58% of Chisel modules. One publication analyzed integration of
Use of parameterized generators 18 69% Chisel based accelerator to SDAccel acceleration framework.
Worse results in comparison 2 8% Table III lists the reported features as a summary. Based on
Better results in comparison 3 12% analysis on publications we confirm Chisel is viable for HW
Equal results in comparison 4 15% design independent of target technology. Designer can expect
ASIC results 12 46% functionality to be correct and QoR being on near equal level
ASIC frequency 11 38% than with RTL design while gaining increased productivity
ASIC power 6 23% and reusability. According to surveyed papers Chisel is found
FPGA results 10 42% suitable to even most complex designs such as configurable
FPGA Frequency 9 35% cores and interconnects.
FPGA Power 2 8%
IV. C ONCLUSIONS
Simulation results 3 12%
Difficulties in adoption 0 0% Functional languages allow SoC design to be more expres-
Challenges with Chisel language 1 4% sive through features such as higher level functions. Greater
Challenges with Chisel results 1 4% expressiveness increases productivity, reusability and main-
Issues with integrating Chisel module 0 0% tainability of the code base. We explored available HLLs to
find Chisel being the most interesting choice for us currently.
Advantages featured by Chisel is being higher level language
reference implementation. Comparison was mainly done to and featuring tools to support design process. Chisel is sug-
RTL code. In one case, power comparison was done to server gested to be used with parameterization and using designs as
[28]. In this case, the comparison result details advantages of a generators to increase productivity and reuse.
specialized HW rather than of Chisel. One comparison was Survey to publications using Chisel details that most promi-
done with Bluespec SystemVerilog. This reported in greater nent user of it are still the creators. However, designs are
detail in how a structure being optimized differently leads to being created with it by other users, too. Survey confirms
worse results [39]. In one other case Chisel generated code that language is expressive and can be used to create very
performed worse than comparison target. In all other reported complex designs all the way to ASICs. Analysis revealed that
cases results were either better or equal. In general cases there is no reported cases about issues regarding the adoption
designer should be able to expect code that has high quality or usability of the Chisel.
of results (QoR). Survey also confirms that the language increases designer
Main advantage of the higher level languages in comparison productivity and design reuse without negative impact on
to HDL should be increased productivity. Approximately half physical design results. Even single components can benefit
of the analyzed publications confirm this being the case with from using Chisel, as the end result integrates to existing tools
Chisel. Additionally, one of the key ideas presented by Chisel just like component from RTL designer.
developers, parameterized generators to allow wide reuse, is
reported to be in use in 70% of the surveyed publications. V. F UTURE WORK
This confirms that Chisel designers gain more out of the spent Based on this survey results there is plan to include Chisel
design effort. to SoC-HUB chip design flow. This will enable trialing with
Additionally, few papers generated code to Chisel and the language and higher level features it provides with design
noted advantages in increased optimization by this approach. flow all the way to ASIC.
Other listed benefits were added verification, added validation,
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