1. If Simulation gets hung or running forever, how will you debug it.

Ans: Check your testcase , check sim commands uvm_timeout value

2. What if I have 200 txns in my verification environment and some of them are failing.
How will you debug
Using uvm log/ Transcript we can check the status of the reporting
statements(uvm_info, $display) for each txns.
We will trace each txn and check whether its been driven and whether being received
In scoreboard we will again use reporting statements in check phase to check whether
the expected and actual txn is matching

3. What if I have 100 testcases and 10 are failing due to simulation fatal error issues.
How to debug?
Develop a regression suite for all the test cases and run the same.( regression suit:
system asset that contains a set of related Regression Tests that, together, ensure that the
feature is properly working within a given aspect of a system)
All passing/failing testcases can be determined form the same along with the type of
severity.

4. If there are 100 testcases how to run them?

you need to write some (tcl) script to run the multiple test cases in regression. UVM
will generate the coverage report per test case and at the end of all test cases, total
coverage report needs to be generated based on the individual test coverage reports.

5. If you want your parent constraint to be worked rather than child constraint what you
are going to do?
Ans: We can disable the child constraint using the
object.constraint.constraint_mode(0);Object.constraint_mode(0);
Class base;
Rand bit [31:0] addr;
Constraint c_addr_default {addr==32’h0;}
Endclass

Class child extends base;

Constraint c_addr_default {addr == 32’h0000_000F;}
Endclass

Module test;
Child c;
Initial begin
C =new;
c.c_addr_default.constraint_mode(0);
b=c; //Handle assignment
 if (b.c_addr_default.constraint_mode())
$display(“Base constraint is on”);
$display (“c.addr is %0h”,c.addr);
End
Endmodule

6. What will be output for the below code?

class packet;
rand bit [7:0] id;
constraint c_id { id > 50; }
endclass

module tb;
initial begin
Item itm = new ();
itm.randomize() with { id == 20; };
$display ("Item Id = %0d", itm.id);
end
endmodule

A)It will result in an error because the inline constraint which is defined is not in sync
with the hard constraint defined, to avoid that we can use soft constraint or the inline
value range must in the range with hard constraint defined.

7. .Write an assertion to make sure data rate is within the limit?

$rose(o_tx_ready) -> datarate within 10G

8. You have transmitted FFFF but received EEEE what is your debug approach?
First I have to check the log file after that I have to check the scoreboard and from
scoreboard I have to check inside the monitor and so on.

9. You are given a memory we are writing to a memory address say its 10th location but
whenever writing to the location the data is writing to the 11th location and also while
reading data is retrieving from 11 th location. How we can identify this error.
We can develop a test which does frontdoor write and backdoor reads and vice
versa. If 10 th location write happened to a wrong location, we can catch that issue
from the backdoor reads. Backdoor read will give me data present in 10th location,
which wont match with the data we wrote .We will write a new data to 10th location.
Using backdoor read we can get the current data on 10th location.
10. A fifo given writing and reading at different speeds how we can avoid the
overflow/underflow cases?
 Hint: say abt wr_ptr and rd_ptr (the eqtn for underflow and overflow)
Make the speed rate of both processors same.
Make the depth of fifo infinite(so that we can write and read infinitely only
theoretically possible )

11. If u are going to send two monitors data one monitor data reaches slow and other
monitor fast what u will do?
Ans: As far as synchronization is concerned we need to trigger both the monitors
with same clocking block so that the data is synchronized.
@vif.cb_mon1
@vif.cb_mon2

12. If my code coverage is 100% and functional coverage is 80% . How to improve
functional coverage?

Ans: you don't have test cases which are covering the functional scenarios which are
coded in functional coverage. so you need to create the test cases which can exercise
those functional scenarios.

13. If my functional coverage is 100% and code coverage is 80%. How to improve code
coverage?
Ans: There is hole in your functional coverage. you don't have test cases which
exercise those code. So write the test cases which exercise those code and modify the
functional coverage code to add those missing functional scenarios.
-> There is also chance that design having the dead code.
14. If both code coverage and functional coverage is 100% . Is my verification is
successfully completed?
Ans: No!!!! Do multiple reviews of the test cases and functional coverage.
-> Do review the waveform of few test cases to check test is doing as expected.
-> Do read the specification multiple time and check that there is functional coverage
for each functional scenario.
15. Explain the ways you used for debugging.
o done using log files/transcript display monitor statements .
o done by tracking wave form schematic or data path: add signal to wave and then
add to data flow and it will generate a complete module or block with which that
signal is connected and we have to track the signal upto the last and then check that
path in Verilog/design rtl
o we can also use breakpoints by using $stop

16. If simulation gets hung or running forever. How you debugged it.
o as the person, who implemented testcase, we know how much it is supposed to run
for.
o run the testcase with that much timeout
 UVM_TIMEOUT=value
SV:
fork
begin
#time_delay;
end
begin
$finish;
end
join_any
o when we know that, it is timing out
o what is causing test to hang
o put display messages (UVM: we know from objections)
o from messages, we know, what is causing it to hang.

17. While sending the 1000 pkts, some pkts are missing how can you debug
Ans: we can check log file or transcript file for each transaction by using reporting
mechanism or $display statements and then checking or tracing for all packets whether its
been driven properly and received or not by writing reporting statement in scoreboard
then we can go on checking with monitor and so on.

18. How will you debug when dut is dropping pkts

Ans: Debugging can be in two ways, either it is verification (testbench) or RTL
debugging.
Will check as follows
1. There may be some communication is missing
Here we go for testbench or testcase debugging, in that we can check for
mailboxes(for proper configuration).
Again we check for one pass log file with another log file and check the conditions of
packet drop. It can be timing mismatch also.
2. Check maybe our DUT integrated with the environment In this we check for driver
component as it is sending transaction to dut through interface.

19. When can you say that our verification is 100%.

When have completely satisfied the testplan
All test cases as per the testplan are passing.
Functional coverage is 100%.
Assertion is 100%.
20. In your environment, if you get any error,how will you debug it?
You have an error :
Wdata mismatch with rdata(address missmatch)

Debugging:
1. Check for the testcases inside the generator/sequence
2. You have degugged that it is a address mismatch
3. Check for wr_seq and rd_seq.
4. And also how many mismatches happen.
5. Check for the address loctions, various signals and data, that you are passing.

Frontdoor and backdoor concepts are used for debugging register mismatches.

21. How to inject errors in components?

Call backs : UVM callback
Class callback extends from UVM_calback;
Pre_drive()=new();

Inside driver:
Pre_drive();
inject_errors;
Drive();
Post_drive();
inject_errors;

22. Ways to debug uvm code.

1. For pass and fail check for the test file.
2. Configuration (component check)
+UVm_CONFIG_DB_TRACE
3. Raise and drop objections: in test file we can apply and check raise and drop
objections.

23. If there are 500 input signals. How you will know that all the inputs signals are
toggling?
 Toggle coverage makes assures that how many time reg, net and bus toggled?
Toggle coverage could be as simple as the ratio of nodes toggled to the total
number of nodes.
 Toggle coverage will show which signal did not change the state. Toggle
coverage will not consider zero-delay glitches. Only 1->0 and 0->1 are much
important. This is very useful in gate level simulation.
 After the one step of toggle coverage variable coverage comes. Both the coverage
looks same but there is a minor different between them is toggle coverage works
on gate level but it fail on large quantity. For entity like bus we use variable
coverage.
 24. You have 16bit of data stored. How can you change only lower 8bits

class abc;

randc bit [15:0] a;

constraint data_range{a[7:0]==a;}

endclass

25. If there are 1000 assertions and 10 are failing, then how you debug it?
A. Ways of debugging :-
• TCL (Transcript or Log)
• Waveforms
• RTL files
• Coverage Report – Which assertion is failing and which is passing.