NAME:

ROLL NO:
BRANCH:

EXPERIMENT: 7
AIM: Implement 4bit up-down counter using any
modelling
 4 bit up-down counter using Behavioural modelling
Code:
`timescale 1ns / 1ps

module four_bit_up_down(input clk,input isUp,input reset,output reg [3:0]Q);

always @(posedge clk)

begin

if (reset == 1'b1)

begin

Q = 4'b0000;

end

else

begin

if (isUp == 1'b1)

begin

Q = Q + 4'b0001;

end

else

begin

Q = Q - 4'b0001;

end

end

end
endmodule

RTL:

SIMULATION:
`timescale 1ns / 1ps

module ttl_up_down();

reg reset; reg clk;

reg isUp;

wire [3:0] Q;

four_bit_up_down uut(.clk(clk),.isUp(isUp),.reset(reset),.Q(Q));

initial begin

forever #10 clk = ~clk;

end

initial begin

clk=1'b1;

reset=1'b1;

isUp=1'b1;

#20 reset=1'b0;

forever #300 isUp=~isUp;

end
endmodule

Waveform: