Reg No:

QUESTION PAPER CODE: JP733

B.E / B. Tech. DEGREE EXAMINATIONS, APRIL 2024
Sixth Semester
ELECTRONICS AND COMMUNICATION ENGINEERING
CEC337-DSP ARCHITECTURE AND PROGRAMMING
Internal Assessment Test – II
(Regulation 2021)
Time: 90 Minutes Maximum: 50 Marks
Answer ALL questions
PART A – (5 X 02 =10 Marks)

1. Compare linear and circular addressing modes of TMS320C6x. CO3 [K1]

2. List some of the interrupt control registers. CO3 [K1]
3. What are the commonly used directives of branch and move instruction? CO3 [K2]
4. Write down the list of CCS supporting tools. CO4 [K1]
5. What are the steps to be followed to install CCS? CO4 [K1]
PART B – (02 X 13 = 26 Marks)
6 (a) Briefly explain the major Commercial TI DSP processor. CO3 [K2] (13
(OR)
(b) With a neat block diagram explain the types of instruction in Assembly CO3 [K3] (13
Language.
7 (a) Describe the architecture of TMS320C6X DSP starter kit. CO3 [K2] (13
(OR)
(b) i) Write short note on interrupts of TMS320C6X processors CO3 [K1] (07

ii) Explain short note on Multichannel buffered serial ports. CO3 [K2] (06
PART C – (1 X 14 = 14 Marks)
8 (a) Explain the Digital Signal Processing development systems. CO4 [K3] (14
(OR)
(b) Outline the C54xx and C67xx on chip and on board DSP peripherals CO4 [K2] (14
development boards .

Knowledge Level:
[K1] - Remember, [K2] - Understand, [K3] – Apply, [K4] – Analyze, [K5] – Evaluate & [K6] - Create

CO Course Outcome Level

CO1 : Understand the architectural features of DSP Processors. K2
CO2 : Comprehend the organization of TMS320C54xx DSP processors K2
CO3 : Build solutions using TMS320C6x DSP Processor K2
CO4 : Implement DSP Algorithms K2
CO5 : Study the applications of DSP Processors. K2