Logic Families

Introduction
• Digital integrated circuits are produced using several different circuit
configurations and production technologies.
• Each such approach is called a specific logic family.
• Logic families represent kind of digital circuit/methodologies for logic
expression.
• These families vary by speed, power consumption, cost, voltage & current
levels
 Significance
• Different logic functions, when fabricated in the form of an IC belonging to
the same logic family, will have identical electrical characteristics.
• Different logic family may differ in various characteristics like supply
voltage range, speed of response, power dissipation, input and output
logic levels, current sourcing and sinking capability, fan-out, noise margin,
etc.
• the set of digital ICs belonging to the same logic family are electrically
compatible with each other.
• We need to include the interface techniques when two IC’s of different
logic family are used to make them compatible.
 Types of Logic Families
• RTL
• DTL
• TTL
• ECL
• I2L
• NMOS
• PMOS
• CMOS
• Etc.
Classification
 Characteristics
• Voltage and current parameters
• Fan-in
• Fan-out
• Power Dissipation
• Propagation Delay
• Noise Margin
• Figure of Merit
 Voltage Parameters:
• VIH(min): high-level input voltage, the
minimum voltage level required for a
logic 1 at an input
• Voltage levels associated with logic High
• VIL(max): low-level input voltage
and logic Low levels are not single
• VOH(min): high-level output voltage values but a band of values.
• VOL(max): low-level output voltage
• For proper operation the input voltage
levels to a logic must be kept outside
the indeterminate range. i.e. lower than
VIL(max) and higher than VIH(min).
Current Parameters:
 Noise Margin
• This is a quantitative measure of noise
immunity offered by the logic family.
• Maximum noise voltage added to an
input signal of digital circuit that doesn’t
cause undesirable changes in circuit
output(worst case)
• Maximum noise that can be tolerated by
a gate
• Measured in Volts
• VNH the HIGH level noise margin
• VNL the LOW-level noise margin
Determine the HIGH-level and LOW-level noise margins for CMOS and for TTL by
using the information
 Power Dissipation
• Amount of power delivered to gate from power supply not from another
gate
• product of supply voltage VCC and supply current ICC
• Current drawn from power supply depends on logic state of gate
• Measured in milliWatts

• Low power dissipation is desired in large systems as it leads to

• Lower cooling costs
• Lower power supply and distribution costs,
• Reduction in mechanical design problems
• Decrease in power dissipation on a per-gate basis with
higher integration level
 Steady state dissipation
• DC supply voltage VCC x Average supply current ICC
– Value of ICC for a Low gate output is higher than for a High output
– Manufacturer's data sheet usually specifies both these values as ICCL
and ICCH .
– The average ICC is then determined based on a 50% duty cycle
operation of the gate

ICCH : When the gate is in the

HIGH output state, an
amount of current is drawn;

ICCL : In the LOW output state,

a different amount of current
is drawn
 Dissipation during transitions
• The supply current drawn is generally very different during the transition
times
• More number of active devices come into operation, and parasitic
capacitors will have to be charged and discharged.
• Power dissipation increases linearly as a function of the frequency of
switching.
 Propagation Delay
• Time interval between the application of an input pulse and the
occurrence of the resulting output pulse.
• tPHL: Signal delay time between input and output when output changes
from high to low level
• tPLH: Signal delay time between input and output when output changes
from low to high level
• Measured in nanoseconds
• Smaller is the delay, faster is the gate

the 50% points on the

pulse edges used as
references.
 Speed-Power Product/Figure of Merit
• Desirable properties:
– Short propagation delays (high speed)
– Low power dissipation
• Speed-power product measures the combined effect
• Product of propagation delay and power dissipation
• The unit of speed-power product is the picojoule (pJ).
• Low value is desirable
• For example, HCMOS has a speed-power product of 1.2 pJ at
100 kHz while LS TTL has a value of 22 pJ.
 Fan In
• Fan in or gate is the number of inputs that can
practically be supported without degrading
practically input voltage level.
 Fan Out
• Maximum number of loads that can be
connected to an output of gate without
degrading the normal operation
• Also known as loading
• Calculated from amount of current available
in gate output and amount of current
needed in each input of gate
 Input and output structures
• Effective interfacing both at the input and output are
needed
• Interfacing at the input requires facility
– To accept different voltage levels for the two logic states
– To accept signals with rise and fall times very different
from those of the signals associated with that logic family
• At the output we require
– Larger current driving capability
– Facility to increase the voltages associated with the two
logic levels
– Ability to tie the outputs of gates to have wired logic
operations
 Interfacing at the inputs and outputs
• Interfacing the slow varying signals is achieved
through Schmitt triggers
• Voltage levels of the output signals can be
increased by providing open-collector
configurations. Open-collector configurations also
permit us to achieve wired-logic
operations
• The outputs of gates can be tied together by
having tristate outputs.
•
 Schmitt Trigger Inputs
• When a slow changing signal superposed with
noise is applied to gate
Current-Sourcing and Current-Sinking
action
• Logic families can be described according to how current flows between
the output of one logic circuit and the input of another.
 Voltage-Related Interfacing Problems
• In some interfacing situations, a HIGH output pin may produce a voltage
that is too low to be recognized as a HIGH by the input pin it’s connected
to.
• The solution in such cases is to use a pull-up resistor
• Example: TTL to CMOS
 A TTL HIGH output may be as low as 2.4 V.
 But a CMOS input expects HIGHs to be at least 3.33 V
 Current-Related Interfacing Problems
• In some interfacing situations, either a HIGH output pin may not source
enough current to drive the input pin it’s connected to, or a LOW output
pin may not sink enough current to drive the input pin it’s connected to.
• The solution in such cases is to use a buffer.
• Example: CMOS to TTL
 A CMOS LOW output can only sink 0.51 mA.
 But as much as 1.6 mA may flow out of a TTL LOW input.
 It can also be used for increasing the fanout
 Three-State Outputs
• Logic outputs have two normal states; Low and High

• It is desirable to have another electrical state in which the output of the circuit offers very high
impedance, high impedance, Hi-z or floating state

• In the high-Z state, the output is disconnected from the external circuit. In this state, the circuit is
effectively disconnected at its output, except for a small leakage current.

• Three states: logic 0, logic 1, and Hi-z.

• An output with three possible states is called tri-state output

• Devices with three state outputs, should have an extra input, called as output enable (OE) for
placing a device in low-impedance or high-impedance state

• Useful when the outputs of many chips are tied to the same bus: at any time, only one of them
should be connected to the bus. The outputs of devices which can have three states can be tied
together, to create a three-state bus.
 Diode Logic (DL)
• simplest; does not scale
• NOT logic not possible (need an active
element)
Bipolar Junction Transistor as a Switch
 Transistor as a Switch
• When the input of a saturated transistor is
changed
– Output does not change immediately
– It takes extra time, called storage time, to come out of
saturation
• Storage time accounts for a significant portion of
the propagation delay in the earlier TTL families.
• This storage time is reduced by placing a Schottky
diode between the base and collector of each
transistor that might saturate.
 Transistor Transistor Logic (TTL)
• TTL family is a modification to the DTL. It has come to existence so as to
overcome the speed limitations of DTL family. The basic gate of this family
is TTL NAND gate.

• Its versatility lead to several subfamilies:

– Low Power TTL
– High Frequency TTL
– Schottky TTL
• Several sub-families have evolved in the Schottky TTL family
– Low-power Schottky TTL (LSTTL)
– Fairchild Advanced Schottky TTL (FAST)
– Advanced Low Power Schottky TTL (ALSTTL)
– Advanced Schottky TTL (ASTTL)
Output Configuration of TTL Series
• Open Collector Output
• Totem Pole Output
• 3-State (Tristate) Output
The combination of Q3 and Q4
is called TOTEM POLE
arrangement.

Q1 is called input transistor, which

is multi emitter transistor, that
drive transistor Q2 which is used
to control Q3 and Q4.

diode D1 ensures when Q4 is ON, Q3 is OFF.

Q3 is cutoff when output transistor Q4 is saturated and

Q3 is saturated when output transistor Q4 is cutoff .
Thus one transistor is ON at one time.
 Operation
• When any of the input is low, the
emitter junction of Q1 is forward
biased and hence Q1 is ON and
Current flow from Vcc to the input
through resistance R1. The voltage
available at the base of Q2 is not
sufficient and hence Q2 is off.

• With Q2 off, there is no base

current for Q4, and it turns off.
Because there is no Q2 collector
current, the voltage at Q3’s base
will be large enough to forward-
bias Q3 and D1, so that Q3 will
conduct.
 Operation
• When all the inputs are high, then Q1
will be off and no current flow from the
input to the Q1.
• The current will flow from VCC to Base of
Q2 through resistance R1 making Q2 ON.
• Current from Q2’s emitter will flow into
the base of Q4 and turn Q4 on. At the
same time, the flow of Q2 collector
current produces a voltage drop across
R2 that reduces Q2’s collector
voltage(voltage at base of Q3) to a low
value that is insufficient to turn Q3 on.

• To prevent Q4 to go into saturation, D1 is

used and hence Q4 is OFF and O/P is low
 Advantage of Totem-pole
• Transistors Q3 and Q4 constitute what is known as a totem-pole output
arrangement. In such an arrangement, either Q3 or Q4 conducts at a time
depending upon the logic status of the inputs.
• The major advantage of using a totem-pole connection is that it offers
low-output impedance in both the HIGH and LOW output states.
• In the HIGH state, Q3 acts as an emitter follower and has an output
impedance of about 70  .
• In the LOW state, Q4 is saturated and the output impedance is
approximately 10 .
• Because of the low output impedance, any stray capacitance at the output
can be charged or discharged very rapidly through this low impedance,
thus allowing quick transitions at the output from one state to the other.
• Another advantage is that, when the output is in the logic LOW state,
transistor Q4 would need to conduct a fairly large current if its collector
were tied to VCC through R3 only. A non-conducting Q3 overcomes this
problem.
 Disadvantage of Totem Pole
• In the totem-pole output configuration, the switch-off action
of Q4 is slower than the switch-on action of Q3.
• On account of this, there will be a small fraction of time, of
the order of a few nanoseconds, when both the transistors
are conducting, thus drawing heavy current from the supply.
• Wired logic not possible
 Open Collector Output
the output is the collector of transistor
Q3 with nothing connected to it,
hence the name open collector.

In order to get the proper HIGH and

LOW logic levels out of the circuit, an
external pull-up resistor must be
connected to VCC from the collector of
Q3,

When Q3 is off, the output is pulled up to VCC through the external

resistor.
When Q3 is on, the output is connected to near-ground through the
saturated transistor.

Open Collector symbol for the inverter
When Q3 is off, the output is pulled up to VCC
through the external resistor. When Q3 is on,
the output is connected to near-ground
through the saturated transistor.
The main advantage of open collector is that
the outputs of different gates can be wired
together, resulting in ANDing of their outputs.
The big disadvantage of open-collector gates is
their slow switching speed.
Why is it slow?
Because the pull-up resistance is a few
kilohms, which results in a relatively long time
constant when it is multiplied by the stray
output capacitance.
 Wired operation with Totem-Pole
• Not feasible

Let us assume that the output of one of the

gates, say gate-1, is High, and the output of the
other is LOW.

The result is that a relatively heavier current

flows through Q31 and Q42.

This current, which is of the order of 50–60

mA, exceeds the IOL(max.) rating of Q42.

This may eventually lead to both transistors

getting damaged.
 Applications
• To drive a lamp or relay
• Perform wired logic (not possible with totem
pole)
• Construction of common bus system
 Floating and Unused Inputs
in TTL
• The floating input of TTL family devices behaves as if logic HIGH has been
applied to the input.
• it is strongly recommended that the unused inputs of TTL gates be
connected to a logic HIGH input instead of floating or unconnected
because floating input behaves as an antenna and may pick up stray noise
and interference signals, thus causing the gate to function improperly.
 ECL (Emitter Coupled Logic)
• Emitter coupled logic (ECL) is fastest logic family.
• It is a nonsaturating logic family. The transistors of an emitter coupled
logic are operated in cut-off or active region, it never goes in saturation
and therefore the storage time is reduced.
• The circuit consists of difference amplifiers and emitter followers. Emitter
terminals of the two transistors are connected together and hence it is
called as emitter coupled logic.
• The circuit has two outputs which are complementary. These outputs
corresponds to OR and NOR Logic.
• The emitter followers are used at the output of difference amplifier to
shift the DC level.
• Because of the low output impedance of the emitter-follower and the high
input impedance of the differential amplifier input, as a result, the
transistors change states quickly, gate delays are low, and the fan out
capability is high.
• The lack of saturation results in higher power consumption and limited
voltage swing (less than 1 V), but it permits high-frequency switching.
Basic ECL Current Switch
The VCC pin is normally
connected to ground, and the
VEE pin is connected to -5.2 V
from the power supply for
best operation.

logic LOW = logic ‘0’ = -1.75 V

logic HIGH = logic ‘1’ = −0.9 V

logic LOW = logic ‘0’ = -1.75 V

logic HIGH = logic ‘1’ = −0.9 V

The bias network configured around transistor Q6 produces a voltage of typically

−1.29V at its emitter terminal.
This leads to a voltage of −2.09V at the junction of all emitter terminals of various
transistors in the differential amplifier, assuming 0.8V to be the required forward-
biased P–N junction voltage.
When all i/p are low

 Now, let us assume that all inputs are in a logic ‘0’ state, that is, the voltage at the
base terminals of various input transistors is −1.75 V.
 This means that the transistors Q1, Q2, Q3 and Q4 will remain in cut-off as their
base-emitter junctions are not forward biased{(-1.75-(2.09))=0.34V }by the required
voltage(0.8V).

 This leads us to say that

transistor Q7 is conducting,
producing a logic ‘0’ output, and
transistor Q8 is in cut-off,
producing a logic ‘1’ output.
When any or all i/p are high

 If any one or all of the inputs are driven to logic ‘1’ status, that is, a nominal voltage
of −0.9V is applied to the inputs.
 The base-emitter voltage differential of transistors Q1–Q4 exceeds the required
forward-biasing threshold, with the result that these transistors start conducting.
 This leads to a rise in voltage at the common-emitter terminal, which now becomes
approximately −1.7V as the common-emitter terminal is now 0.8V more negative
than the base terminal voltage.

 With rise in the common-

emitter terminal voltage, the
base-emitter differential voltage
of Q5 becomes 0.31 V, driving
Q5 to cut-off.
 The Q7 and Q8 emitter
terminals respectively go to
logic ‘1’ and logic ‘0’.
 Wired ECL

External Wired operation of two NOR output produces wired OR function

 ECL Characteristics
• Produces True and Complimented output simultaneously
without use of inverter
• High i/p impedance and low o/p impedance
• Large fanout ( approx. 25) and drive capability
• Less propagation delay time (td = 1ns).
• 0 –1.7 V and 1–0.8V (Such strange logic levels require
extra effort when interfacing to TTL/CMOS logic families.)
• Poor noise margin (0.2-0.25 V )
• Large Power dissipation within the range of 40–55 mW.
• Wired OR Logic is supported
 Unconnected Input of ECL
• If any one of the inputs of the ECL gate is
open, then the corresponding transistor
operates in cut-off and there is no current
flow through the transistor. The same
condition occurs when the input is in logic 0
level and hence the unconnected input of ECL
is treated as logic 0.
 NMOS
• NMOS family uses only n-
channel enhancement MOSFET
• VGS in NMOS device is normally
zero or positive. If VGS = 0 then
the resistance from drain to
source (RDS ) is very high, of the
order of mega ohm or more.
• When VGS is made positive RDS
can decrease to a very low
value, of the order of 10 ohms.
 NMOS Inverter

• MOSFET Q1 acts as a load resistor and MOSFET Q2 acts as a switching element.

• Q1 is always ON; the load resistance is equal to RON of the n-channel MOSFET.

• Instead of load resistance, Q1 is used, which reduces the size of the chip.
• Q1 may be of depletion type or enhancement type. But Q2 is always of
enhancement type
 Operation of NMOS as Inverter
• When the input signal is high
(positive voltage), Q2 is ON,
the current flows through the
drain terminal and the output
is low.

• When the input signal is low (0

V or negative voltage), Q2 is
OFF, there is no current flow
through the circuit and the
output is high (VDD).
NMOS as NAND Gate
NMOS NOR Gate
Characteristics of NMOS
 PMOS
• VGS is normally zero
or negative. If VGS is
zero, then the
resistance from
source to drain (RDS )
is very large

• When VGS is negative

RDS can decrease to a
very low value.
 Complimentary MOS (CMOS)
• Considerably lower energy consumption than TTL and ECL, which has
made portable electronics possible.

• Most widely used family for large-scale devices.

• Combines high speed with low power consumption.

• Usually operates from a single supply of 5 – 15 V

• Excellent noise immunity of about 30% of supply voltage

• Can be connected to a large number of gates (about 50) .

• don’t leave inputs floating (in TTL these will float to HI, in CMOS you get
undefined behaviour)
 CMOS/TTL power requirements
• TTL power essentially constant (no frequency
dependence)

• At high frequencies (>> MHz) CMOS dissipates more

power than TTL
• Overall advantage is still for CMOS even for very fast
chips – only a relatively small portion of complicated
circuitry operates at highest frequencies
CMOS Inverter
CMOS NAND gate
CMOS NOR gate
CMOS tri-state buffer
 CMOS Characteristics

Operation Speed

Noise Margin
Fan Out: MOS devices have a very high input impedance; therefore, the fan-
out is large.

Fan-out of a CMOS is 50 for low frequency and less than 50 for high
frequency in

Unused Input : CMOS inputs have to be connected with a fixed voltage level or to
another input.

If inputs of unused CMOS gates are open, they are susceptible to

noise and static charge that could bias both p and n-channel
MOSFETs in the conductive state and results in increased power
dissipation and overheating
 Integrated Injection Logic (I2L)
• The integrated injection logic uses only
transistors for the construction of a gate and
hence it becomes possible to integrate a large
number of gates in a single package.
• This IC is easier and cheaper to fabricate. The
figure of merit of I2L circuits is quite small (4
PJ)
 I2L Inverter
• If the input V1 is at low logic level, transistor T1 is off and IB1 = 0.
• The input source acts as a sink for the current supplied by the current
source I1 and the output is at high logic level.
• If the input is high, the base current IB1 = IS + I1 and T1 operates in
saturation. The output is at low logic level
• 2nd shows a simple inverter circuit with transistor T2 as the constant
current source, hence T2 is in series as a constant current source
When the input is low, the source sinks the
current and T1 is off and the output is high.

When the input is high, the base current of T1

is the sum of currents I1 and the current
supplied by the source, T1 is ON and the
output is low.
 I2L NAND Gate
• When inputs A and B are low
or any one of the inputs is
low, the current provided by
T2 is sinked by the source,
T1 is OFF, and the output is
high.

• When both the inputs are

high, the base current of T1
is the sum of currents
provided by the source and
T2, transistor T1 is ON and
the output is low
 I2L NOR Gate
• The circuit has two
inverters with their outputs
connected together. When
both or any one of the
inputs is high, the output of
the corresponding inverter
is low and the resulting
output is low.

• When both inputs are low,

the output of both the
inverters is high and the
result is also high