IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO.
3, MARCH 2009
Adaptive-Bandwidth Phase-Locked Loop With
Continuous Background Frequency Calibration
Jaeha Kim, Member, IEEE
Abstract—This brief presents an adaptive-bandwidth (BW)
phase-locked loop (PLL) that retains the optimal jitter perfor-
mance over a wide frequency range via continuous background
frequency calibration. The effective center frequency of the
voltage-controlled oscillator (VCO) is calibrated by adjusting the
feedforward division factor while a dual-PLL architecture hides
the switching transients. As a result, the core ring oscillator only
needs to operate over a narrow frequency range of 2 : 1 that is opti-
mal for the jitter, supply sensitivity, and charge pump current mis-
match over process, voltage, and temperature (PVT) conditions.
The prototype PLL was fabricated in a 0.13-μm CMOS process,
consumed 36 mW of power, and occupied 1.1 × 0.46 mm2 of
area. The measured root-mean-square (RMS) tracking jitter was
less than 0.2% of the reference clock period for the wide range
of output frequency (2 MHz–1 GHz) and multiplication factor
(20−9 ), which supports that the PLL BW scales adaptively with
the reference frequency. Compared to a PLL without frequency
calibration, the proposed PLL demonstrated the jitter reduction
up to 80%.
Index Terms—Adaptive bandwidth (BW), automatic frequency
calibration (AFC), CMOS, phase-locked loop (PLL).
I. I NTRODUCTION
A S CMOS technology scales, it becomes more challenging
to design circuits that meet the specifications under all
process, voltage, and temperature (PVT) conditions. In phase-
locked loop (PLL) designs, one of the challenges is ensuring
that the frequency range of the voltage-controlled oscillator
(VCO) is wide enough to cover the desired frequency points
under all conditions. The widening gap in VCO frequencies
between the slowest and fastest conditions demands a wide
VCO tuning range, even when the PLL needs to operate only
at a single frequency. While many circuit techniques have been
reported to extend the tuning range, a common problem is the
degradation in jitter performance. This brief presents a PLL that
maintains the optimal jitter and bandwidth (BW) characteristics
over a wide range of frequency and PVT conditions.
One of the techniques used in recently reported PLLs is au-
tomatic frequency calibration (AFC). In the LC PLLs described
in [1] and [2], one of the many fine-tuning subranges of the LC
VCO is selected during the start-up, which includes the desired
frequency point. As each subrange does not need to cover the
Manuscript received August 30, 2008; revised November 6, 2008. First
published February 24, 2009; current version published March 20, 2009. This
work was recommended by Associate Editor J. Buckwalker.
The author is with Stanford University, Stanford, CA 94305 USA (e-mail:
jaeha@ieee.org).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2008.2011601
1549-7747/$25.00 © 2009 IEEE
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205
entire range, it helps reduce the VCO gain and the jitter due to
the noise on the control input.
However, most of the frequency calibration schemes in the
literature are in the foreground and cannot perform the cali-
bration without interrupting the normal operation. Therefore,
when the environment condition significantly drifts from the
initially calibrated condition, the PLL may lose lock and remain
unlocked until the VCO is recalibrated. To prevent such disrup-
tion, each fine-tuning range of the VCO must be wide enough
to accommodate any possible drifts under PVT conditions
after the calibration. Unless the expected drift range is known
and narrow, a wide fine-tuning range is still required, and the
original challenge is not alleviated.
This brief presents an adaptive-BW PLL that achieves a wide
frequency range and optimal jitter performance via continuous
background frequency calibration. The PLL calibrates the ef-
fective center frequency of the VCO by adjusting the division
factor of a feedforward divider following the VCO. The division
factor can be varied during the normal operation by having two
sub-PLLs since one can hide the disruption in the other during
the calibration. The main benefit of this architecture is that the
core VCO needs to operate only over a narrow frequency range
of 2 : 1 that has the lowest jitter and supply sensitivity for any
given PVT condition. In addition, the PLL BW is more explic-
itly controlled by the division factor than the self-biased charge
pump alone, resulting in more accurate adaptive-BW dynam-
ics (i.e., the constant BW-to-frequency and constant damping
ratios) in deep-submicron CMOS processes [4], [5], [8].
This brief is organized as follows: First, the architecture of
the PLL, including the operating principle of the continuous
background frequency calibration, is described. Second, the
circuit implementation of each key component in the PLL
is presented. Then, the measurement results from a test chip
fabricated in a 0.13-μm CMOS are discussed.
II. PLL A RCHITECTURE
The overall architecture of the proposed PLL is shown in
Fig. 1. As mentioned earlier, it consists of two sub-PLLs
with programmable feedforward and feedback dividers. The
feedforward divider is used to control VCO frequency fVCOi ,
independent of the actual output clock frequency fOUTi , where
i is the index for each sub-PLL (1 or 2). In other words, fVCOi
can become any multiple of fOUTi by varying feedforward
division factor Ni . The feedback divider is used to multiply the
input clock frequency by its division ratio M , as in conven-
tional PLLs.
Feedforward division factor Ni is controlled, so that VCO
frequency fVCOi is confined within a narrow range. For ex-
ample, if Ni takes an integer power of 2, the VCO needs to
 206 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 3, MARCH 2009
Fig. 1. Dual-PLL architecture for continuous background frequency
calibration.
Fig. 2. (a) VCO frequency calibration via the feedforward division factor.
(b) Algorithms for sub-PLL selection and division factor calibration.
operate only over a narrow range of 2 : 1, as shown in Fig. 2(a).
The operating range of the PLL is primarily determined by the
programming range of the feedforward divider, as long as the
VCO has a range of 2 : 1. As a result, we can greatly relax
the design constraints on the VCO. One can further reduce the
required range of the√VCO by varying Ni as an integer power
of less than 2, e.g., 2 ∼ = 7/5. In this case, one would need a
fractional divider, such as that described in [3].
A glitch-free continuous background calibration of feedfor-
ward division factor Ni is enabled by the sub-PLL selection
algorithm that hides the switching transient from the output
clock CKOUT . As shown in Fig. 1, a finite-state machine (FSM)
determines which sub-PLL drives the output clock and adjusts
the feedforward division factor of the unselected sub-PLL. Any
glitches due to change in the feedforward division factor are
avoided by changing it only when the sub-PLL is not currently
driving the output clock. In addition, any glitches due to change
in the selection of the sub-PLL are minimized by switching the
selection only when both the sub-PLLs are locked and equally
optimal to drive the output clock.
Fig. 2(b) shows the algorithm that governs the sub-PLL
selection and the division factor calibration. The gray lines plot
the control voltage VCTRL versus the output clock frequency
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Fig. 3. Replica-compensated supply-regulated VCO.
fOUT characteristics for various feedforward division factors,
and the black lines highlight the regions where the correspond-
ing sub-PLL is selected to drive output clock CKOUT in Fig. 1.
The feedforward division factors of the two sub-PLLs, i.e., N1
and N2 , are always different by a factor of 2.
The optimality of each sub-PLL driving the output clock is
determined by the distance of its control voltage VCTRLi to
optimal voltage VOPT , i.e., the sub-PLL with the settled VCTRL
closer to VOPT drives the output clock. Therefore, the switch
in the sub-PLL selection occurs when the two VCTRL ’s have
equal distances to VOPT or, equivalently, when the average
of the two VCTRL ’s is equal to VOPT , as shown in Fig. 2(b).
The change in the feedforward division factor occurs when the
corresponding sub-PLL’s VCTRL becomes too far from VOPT
or when the other sub-PLL’s VCTRL crosses VOPT . Voltage
VOPT can be made to track the PVT condition, so that the
continuous background frequency calibration keeps the VCO
in its optimal jitter condition at all times. The next section
describes the circuit implementation of each component in the
PLL, including the FSM and the circuit that generates VOPT .
III. C IRCUIT I MPLEMENTATION
A. Replica-Compensated Supply-Regulated VCO
Fig. 3 shows the circuit schematics of the replica-
compensated supply-regulated VCO [6]. The frequency of the
CMOS inverter-based five-stage ring oscillator is controlled by
regulating its supply voltage VREG . The regulator is basically
a two-stage amplifier in a unity-gain feedback configuration,
tracking input voltage VFF . The secondary feedback consisting
of a replica load helps extend the regulator BW and improve
the supply noise rejection. The replica load has similar I–V
characteristics as the ring oscillator but has quicker response
to the supply noise. As a result, the regulator can react to the
noise sooner. We used the static load structure shown in Fig. 3
as the replica for the minimum loading on VRPL . Fig. 4 shows
the simulated ratio between the I–V characteristics of the VCO
and the replica load. Over the voltage range 0.5–1 V and under
various PVT conditions, the ratio is kept fairly constant between
2.6 and 3.1, demonstrating the suitability of the chosen static
load as the replica.
B. Charge Pump With Adaptive-BW Control
In this brief, we aim to control the PLL BW to be a fixed
portion of the reference frequency, e.g., 1/100, independent of
the PVT condition. Such adaptive control of BW helps achieve
the best jitter performance over a wide frequency range. In the
fixed-BW PLLs, the choice of BW is typically limited by the
worst-case condition, such as the lowest reference frequency,
and the PLL is often forced to give up the performance
KIM: ADAPTIVE-BANDWIDTH PHASE-LOCKED LOOP WITH CONTINUOUS BACKGROUND FREQUENCY CALIBRATION
Fig. 4. Simulated ratio between oscillator load current IVCO and replica load
current IRPL under various PVT conditions.
Fig. 5. Push–pull charge pump with replica biasing for adaptive BW.
achievable under other conditions. According to [8], for a
charge-pump PLL to have an adaptive BW, it must satisfy
ICP ∝ − ∂TREF /∂VCTRL (1)
R ∝ TREF (2)
where ICP is the charge-pump current, R is the loop filter
resistance, TREF is the reference clock period, and VCTRL is the
control voltage. For the regulated-supply PLLs, the first scaling
requirement translates to
ICP ∝ IVCO /(Ni · M ) (3)
where IVCO is the current consumed by the ring oscillator when
its supply VREG is regulated to VCTRL . The product of Ni and
M is the total division factor of the PLL.
Fig. 5 shows the circuit schematic of the charge pump. A
replica-feedback biasing loop generates two bias voltages VBP
and VBN that determine the up and down currents of the charge
pump, respectively. The replica circuit closely tracks the I–V
characteristic of the ring oscillator across PVT, so that the down
current proportionally scales with oscillator current IOSC when
VBN is equal to VCTRL . The biasing loop also controls VBP ,
so that the up and down currents are the same (= ICP ). As a
result, both the up and down currents scale with IVCO .
The push–pull charge pump in Fig. 5 is divided into four
equally sized segments to scale the currents by ×1, ×1/2, and
×1/4 for the total division factor Ni M of 1, 2, and 4, respec-
tively. For Ni M greater than 4, the current scaling is effectively
done by the charge redistribution network, as described in the
next section.
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207
Fig. 6. Simulated mismatch between the up/down currents of the
charge pump.
Fig. 7. Half-duty sampled feedforward loop filter and charge redistribution
network.
Fig. 6 shows the simulated mismatch between the up and
down currents of the charge pump. The replica-feedback bias-
ing loop maintains a close match within ±1% for VCTRL be-
tween 0.5 and 1 V and various PVT conditions. For the reduced
VCTRL range due to the continuous frequency calibration, the
mismatch is less than ±0.2%. Good matching between the up
and down currents is desirable for minimizing the static phase
offset and the reference spur of the PLL.
C. Half-Duty Sampled Feedforward Loop Filter and Charge
Redistribution Network
Fig. 7 shows the half-duty sampled feedforward loop filter
[7] with the charge redistribution network. The charge redistri-
bution network scales down the charge transferred by the charge
pump to meet the first scaling requirement (3) for N · M greater
than 4. Every time signal S1 toggles up and down, the error
charge stored in the VCP node is halved via charge sharing.
Signal S1 is generated by the programmable divider and toggles
log2 (Ni M/4) times within a reference period. Redistributing
charge saves the loop capacitor area by reducing the effective
ICP and mitigates the area penalty of using two sub-PLLs.
Once the charge is scaled, it is transferred to the half-duty
sampled feedforward loop filter. Its operation is explained in
[7]. Voltage VFF is equivalent to the voltage across the conven-
tional series-RC filter and is provided to the VCO. However,
unlike that in the series-RC filter case, its proportional control
 208 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 3, MARCH 2009
Fig. 8. Programmable divider.
TABLE I
TRUTH TABLE FOR SUB-PLL SELECTION AND FREQUENCY CALIBRATION
pulse lasts for a half reference period (TREF /2), with the
amplitude proportional to the transferred charge. As a result, the
effective loop filter resistance can be found to be proportional to
TREF , realizing the second scaling requirement (2) for adaptive
BW. In addition, the fixed-duration proportional control pulse
helps reduce the reference spur [5].
D. Programmable Divider
Fig. 8 shows the programmable divider. It implements both
the feedforward (÷Ni ) and feedback (÷M ) dividers in Fig. 1.
The divider is composed of 24 synchronous divide-by-2 cells in
series, each of which is enabled or disabled by the thermometer-
coded log2 (Ni M ), i.e., sel_NM[23:0]. Feedback clock CKFBi
is generated at the end of this chain, and the output clock is
tapped from one of the intermediate cell outputs based on the
value of M . The additional logic included in each divider cell
generates signal S1 for the charge redistribution network.
E. FSM for Continuous Background Frequency Calibration
Table I lists the truth table for the FSM that controls the sub-
PLL selection and the VCO frequency calibration. Fig. 9 shows
the supporting circuits that generate the necessary signals for
the FSM to make the decisions. Those signals include the
outputs of the frequency detectors comparing the frequencies
of the feedback clocks (CKFB1,2 ) to the reference (ST_FAST1,
2 and ST_SLOW1, 2) and the output of the comparators
comparing VOPT with VCTRL1 , VCTRL2 , and (VCTRL1 +
VCTRL2 )/2 (ST_VCTRL1, 2 and ST_VCM). The circuit gen-
erating VOPT that tracks the VCO condition across PVT is also
shown in Fig. 9.
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Fig. 9. Supporting circuits that generate the necessary signals for the FSM.
Fig. 10. Die of the prototype PLL.
TABLE II
CHIP CHARACTERISTICS SUMMARY
Frequency detection is necessary to ensure that VOPT is
compared against the settled VCTRL and not to that still in
transient. It also ensures that only the sub-PLL in the locked
state drives the output clock.
When the FSM switches the sub-PLL selection, the output
clock may experience a phase shift due to the difference in
the static phase offsets between the two sub-PLLs. To prevent
such phase shifts from turning into high-frequency jitter via
frequent switching of the sub-PLL selection, the FSM makes
the switch only after two consecutive identical decisions are
made. Nonetheless, it is desirable to minimize the difference in
the static phase offsets, e.g., with careful layout matching or an
auxiliary offset calibration (which is not implemented in this
brief).
IV. M EASUREMENT R ESULT
The described adaptive-BW PLL was implemented in a
0.13-μm CMOS process. The die is shown in Fig. 10, and the
characteristics are summarized in Table II. The PLL occupies
1.2 × 0.46 mm2 of the area and dissipates 36 mW from a
1.2-V supply. The PLL had a wide division factor (Ni M ) range
KIM: ADAPTIVE-BANDWIDTH PHASE-LOCKED LOOP WITH CONTINUOUS BACKGROUND FREQUENCY CALIBRATION
Fig. 11. Measured jitter versus output frequency fOUT (M = 1).
Fig. 12. Measured RMS jitter versus output frequency fOUT and M .
of 21−24 , but the PLL only locked to reference frequency fREF
ranging from 2 MHz to 1 GHz. For the reference frequencies
below 2 MHz and the total division factors beyond 210 , the sub-
threshold leakage and charge injection in the charge pump and
the loop filter network were significantly affecting the charge
that controls the loop. The continuous background calibration
of feedforward division factor Ni successfully operated, and the
VCO oscillation frequency was confined to a narrow range of
1–2 GHz over the entire range of fOUT . The PLL can multiply
the reference frequency by any factor M = 20−9 as long as
M fREF does not exceed 1 GHz.
The measured peak-to-peak and root-mean-square (RMS)
jitters of the PLL output clock versus output clock frequency
fOUT and versus multiplication factor M are plotted in Figs. 11
and 12, respectively. In the measurement setup, a low-noise
clock from an Agilent 81134A pulse generator was used as
the reference source; thus, the PLL clock jitter was largely
contributed by the VCO phase noise. Under such conditions,
it has been analyzed in [10] that the jitter of a second-order
PLL inversely proportionally scales to the square root of the
PLL BW if the PLL filters all but the high-frequency portion of
white thermal noise (e.g., when the BW is high). On the other
hand, the jitter scales as 1/BW if significant 1/f flicker noise
remains unfiltered and dominant (e.g., when the BW is low).
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209
Figs. 11 and 12 confirm that the BW of the proposed PLL
adaptively scales with fOUT and 1/M , respectively. For low-
fREF points in the figures where the BWs are low and the flicker
noise contributions remain dominant, the RMS jitter linearly
scales with 1/fOUT and M , respectively. On the other hand,
for the high-fREF points, the jitter is inversely proportional to
the square root of fOUT /M . Both cases support the scaling
of PLL BW with fOUT /M (= fREF ). The discontinuities in
the jitter trends correspond to the points where feedforward
division factor N changes.
When the PLL operated with a fixed N , the jitter more
rapidly increased as the frequency decreased. The phase noise
of the inverter-based ring oscillator worsened as its voltage
swing was reduced and the devices generated more noise [9].
By calibrating N , jitter reduction of as much as 80% was
achieved.
The measured worst-case difference between the static phase
offsets at the sub-PLL selection boundaries was 3.6% of the
reference period. Since the two sub-PLLs had identical layouts,
the differences were mainly due to random mismatches. How-
ever, any increase in the measured jitter due to frequent sub-
PLL switching was not observed during the measurements.
V. C ONCLUSION
The adaptive-BW PLL with continuous background fre-
quency calibration has been presented. The digital controller
that performs the frequency calibration complements various
imperfections in the analog components of the PLL and helps
realize a low-jitter PLL that operates over a wide frequency
range in deep-submicrometer CMOS technology.
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