Fundamental Concepts

Dr. Sunita Rawat

 Processor •Fastest access is to the data held in
processor registers. Registers are at
Registers the top of the memory hierarchy.
Increasing Increasing Increasing •Relatively small amount of memory that
size speed cost per bit can be implemented on the processor
Primary L1 chip.This is processor cache.
cache
•Two levels of cache. Level 1 (L1) cache
is on the processor chip. Level 2 (L2)
cache is in between main memory and
SecondaryL2 processor.
cache
•Next level is main memory, implemented
as SIMMs. Much larger, but much slower
than cache memory.
Main •Next level is magnetic disks. Huge amount
memory of inexepensive storage.
•Speed of memory access is critical, the
idea is to bring instructions and data
Magnetic disk
that will be used in the near future as
secondary close to the processor as possible.
memory
◾ Maximum size of the Main Memory is determined by the
addressing scheme.
For example, a computer that generates 16-bit addresses is capable of
addressing up to 2^16 = 64K (kilo) memory locations.
◾ byte-addressable
◾ CPU-Main MemoryConnection

Processor Memory
k-bit
address bus
MAR
n-bit
data bus
MDR Up to 2k addressable
locations

Word length = n bits

Control lines
( R / W , MFC, etc.)
A useful measure of the speed of memory units is the time that elapses between the
initiation of an operation to transfer a word of data and the completion of that
operation. This is referred to as the memory access time.

Another important measure is the memory cycle time, which is the minimum time
delay required between the initiation of two successive memory operations,
Memory cycle time = access time plus transient time (any additional time required
before a second access can commence)
for example, the time between two successive Read operations.

The cycle time is usually slightly longer than the access time, depending on the
implementation details of the memory unit.
A memory unit is called a random-access memory (RAM) if the access time to any
location is the same, independent of the location’s address.
One way to reduce the memory access time is to use a cache memory.
This is a small, fast memory inserted between the larger, slower main
memory and the processor.
It holds the currently active portions of a program and their data.

Virtual memory is another important concept related to memory organization.

With this technique, only the active portions of a program are stored in the main
memory, and the remainder is stored on the much larger secondary storage
device.
◾ Measures for the speed of a memory:
▪ memory access time.
▪ memory cycle time.

◾ An important design issue is to provide a

computer system with as large and fast a
memory as possible, within a given cost
target.
◾ Several techniques to increase the effective
size and speed of the memory:
▪ Cache memory (to increase the effective speed).
▪ Virtual memory (to increase the effective size).
Semiconductor RAM memories
◾ Each memory cell can hold one bit of information.
◾ Memory cells are organized in the form of an array.
◾ One row is one memory word.
◾ All cells of a row are connected to a common line, known as the
“word line”.
◾ Word line is connected to the address decoder.
◾ Sense/write circuits are connected to the data input/output lines
of the memory chip.
 7 7 1 1 0 0
W0

•
•
•
FF FF
A0
W1

•
•
•
A1
Address • • • • • • Memory
decoder • • • • • • cells
A2
• • • • • •
A3

W15
•
•
•

Sense / Write Sense / Write Sense / Write R/W

circuit circuit circuit
CS

Data input /output lines: b7 b1 b0

16 X 8 organization
 ◾ Memories that consist of circuits capable of retaining their state as long as power is applied
are known as static memories.
◾ Two transistor inverters are cross connected to implement a basic flip-flop.
◾ The cell is connected to one word line and two bits lines by transistorsT1 andT2
◾ When word line is at ground level, the transistors are turned off and the latch retains its state
◾ Read operation: In order to read state of SRAM cell, the word line is activated to close switchesT1 and
T2. Sense/Write circuits at the bottom monitor the state of b and b’

b b Transistors controls the access to cell

If want to write, activate
word line, pass info to bit
lines, as word line is
active, transistor will be
in closed state, so
whatever information, it
will get store into
cell/flipflop
Transistors are control by word line, if
word line is enable transistors will be in
T1 T2 closed state
X Y
Bit lines are connected to the sense/write
ckt, so whatever information read by it
from cell/flipflop will be available

Word line
Bit lines
Example of a CMOS Memory Cell
◾ Static RAMs (SRAMs):
▪ Consist of circuits that are capable of retaining their state as long as the power
is applied.
▪ Volatile memories, because their contents are lost when power is interrupted.
▪ Access times of static RAMs are in the range of few nanoseconds.
▪ However, the cost is usually high.

◾ Dynamic RAMs (DRAMs):

▪ Do not retain their state indefinitely.
▪ Contents must be periodically refreshed.
▪ Contents may be refreshed while accessing them for reading.
◾ In order to store information in the cell, the transistor T is turned “on‟ & the
appropriate voltage is applied to the bit line, which charges the capacitor.
◾ After the transistor is turned off, the capacitor begins to discharge which is
caused by the capacitor’s own leakage resistance.
◾ Hence the information stored in the cell can be retrieved correctly before the
threshold value of the capacitor drops down.
◾ During a read operation, the transistor is turned “on”& a sense amplifier
connected to the bit line detects whether the charge on the capacitor is above
the threshold value.
◾ If charge on capacitor > threshold value -> Bit line will have logic value “1‟.
◾ If charge on capacitor < threshold value -> Bit line will set to logic value “0‟.

Used for large memory requirements

 21-bit
addresses 19-bit internal chip address Implement a memory unit of 2M
A0
A1 words of 32 bits each.
Use 512kx8 static memory chips.
A19 Each column consists of 4 chips.
A20
Each chip implements one byte
position.
A chip is selected by setting its
chip select control line to 1.
Selected chip places its data on the
2-bit
decoder data output line, outputs of other
chips are in high impedance state.
21 bits to address a 32-bit word.
High order 2 bits are needed to
512K  8
memory chip select the row, by activating the
D31-24 D23-16 D 15-8 D7-0
four Chip Select signals.
512K  8 memory chip
19 bits are used to access specific
byte locations inside the selected
19-bit 8-bit data
address input/output chip.

Chip select
That means we will have total
2^19 locations and after selecting
a particular word we will get 8 bit
of data
 How many chips of size 512K X 8 will be
required to make 2M X 32 ?? Here, each chip will give me 8
bits of data but my
requirement is 32 bit so, I need
= to arrange it 4 in a row
(parallelly)to get 32 bit output

= 2^4
So, total 16 chips will be required = 16

4 I have arranged in a row and total

chips are 16 so no. of rows will be 4
◾ How many 128x8 RAM chips are needed to provide a memory capacity of 2048
bytes.
◾ How many lines of address bus must be used to access 2048 bytes of memory.
◾ How many of these lines will be common to all chips.
◾ How many lines must be decoded for the chip select ? specify the size of the
decoder.

◾ 2048/128 =16 chips.

◾ 2048 = (2 power 11) = 11 address lines are needed to address 2048 bytes.
◾ 128 = (2 power 7) = 7 lines to address the chip.
4 lines to decoders for selecting the16 chips.
◾ 4x16 decoder.
If you won’t read question properly answer will be like this….
◾ Design 64K X 8 memory using 16K X 1 static
memory chip.
 Row address strobe ◾ Each row can store 512 bytes.
RAS 12 bits to select a row, and 9
bits to select a group in a row.
Row Total of 21 bits.
address Row 4096 (512 8)
decoder cell array • First apply the row address,
latch
RAS signal latches the row
address.Then apply the
column address,CAS signal
A20- 9  A8- 0 Sense / Write CS latches the address.
circuits R•/ W Timing of the memory unit is
controlled by a specialized
unit which generates RAS and
Column
Column CAS.
address decoder
latch • This is asynchronous DRAM

CAS D7 D0
Column address strobe
◾ Suppose if we want to access the consecutive bytes in
the selected row.
◾ This can be done without having to reselect the row.
▪ Add a latch at the output of the sense circuits in each row.
▪ All the latches are loaded when the row is selected.
▪ Different column addresses can be applied to select and place different bytes on
the data lines.
◾ Consecutive sequence of column addresses can be
applied under the control signal CAS, without
reselecting the row.
▪ Allows a block of data to be transferred at a much faster rate than random
accesses.
▪ A small collection/group of bytes is usually referred to as a block.
◾ This transfer capability is referred to as the
fast page mode feature.
 • Operation is directly synchronized
Refresh
counter with processor clock signal.
•The outputs of the sense circuits are
connected to a latch.
Row
•During a Read operation, the
Row
address
decoder Cell array contents of the cells in a row are
latch
Row/Column loaded onto the latches.
address •During a refresh operation, the
Column Column Read/Write
contents of the cells are refreshed
address
counter
decoder circuits & latches without changing the contents of
the latches.
•Data held in the latches correspond
Clock to the selected columns are transferred
RA S to the output.
Mode register
CA S and Data input Data output •For a burst mode of operation,
register register
R/ W timing control successive columns are selected using
CS column address counter and clock.
CAS signal need not be generated
externally. A new data is placed during
Data
raising edge of the clock
• First ,the row address is latched under control of RAS signal.
• The memory typically takes 2 or 3 clock cycles to activate the selected row.
• Then the column address is latched under the control of CAS signal.
• After a delay of one clock cycle,the first set of data bits is placed on the data lines.
• The SDRAM automatically increments the column address to access the next 3
sets of bits in the selected row, which are placed on the data lines in the next 3
clock cycles.
◾ Large dynamic memory systems can be implemented
using DRAM chips in a similar way to static memory
systems.
◾ Placing large memory systems directly on the
motherboard will occupy a large amount of space.
▪ Also, this arrangement is inflexible since the memory system cannot be expanded easily.
◾ Packaging considerations have led to the
development of larger memory units known as SIMMs
(Single In-line Memory Modules) and DIMMs (Dual In-
line Memory Modules).
◾ Memory modules are an assembly of memory chips
on a small board that plugs vertically onto a single
socket on the motherboard.
▪ Occupy less space on the motherboard.
▪ Allows for easy expansion by replacement .
◾ Recall that in a dynamic memory chip, to reduce the
number of pins, multiplexed addresses are used.
◾ Address is divided into two parts:
▪ High-order address bits select a row in the array.
▪ They are provided first, and latched using RAS signal.
▪ Low-order address bits select a column in the row.
▪ They are provided later, and latched using CAS signal.
◾ However, a processor issues all address bits at the same
time.
◾ In order to achieve the multiplexing, memory
controller circuit is inserted between the processor
and memory.
 Row/Column
Address address

RAS
R/ W
CAS
Memory
Request controller R/ W
Processor Memory
CS
Clock
Clock

Data

22
Read-Only Memories (ROMs)
◾ SRAM and SDRAM chips are volatile:
▪ Lose the contents when the power is turned off.
◾ Many applications need memory devices to retain contents after
the power is turned off.
▪ For example, computer is turned on, the operating system must be
loaded from the disk into the memory.
▪ Store instructions which would load the OS from the disk.
▪ Need to store these instructions so that they will not be lost after the
power is turned off.
▪ We need to store the instructions into a non-volatile memory.
◾ Non-volatile memory is read in the same manner as volatile
memory.
▪ Separate writing process is needed to place information in this
memory.
▪ Normal operation involves only reading of data, this
type of memory is called Read-Only memory (ROM).
Not only in computer but in various electronic devices we use it like washing
machine, microwave…
◾ Read-Only Memory:
▪ Data are written into a ROM when it is manufactured.

◾ Programmable Read-Only Memory (PROM):

▪ Allow the data to be loaded by a user (once).
▪ Process of inserting the data is irreversible.
▪ Storing information specific to a user in a ROM is expensive.

▪ Providing programming capability to a user may be better.

▪ Eg: cell phones, video game consoles, medical devices….

◾ Erasable Programmable Read-Only Memory (EPROM):

▪ Stored data to be erased and new data to be loaded.
▪ Flexibility, useful during the development phase of digital systems.
▪ Erasable, reprogrammable ROM.
▪ Erasure requires exposing the ROM to UV light.
▪ Eg: some micro controllers use it to store program
◾ Electrically Erasable Programmable Read-Only Memory
(EEPROM):
▪ To erase the contents of EPROMs, they have to be exposed to ultraviolet light.
▪ Physically removed from the circuit.
▪ EEPROMs the contents can be stored and erased electrically.
◾ Flash memory:
▪ Has similar approach to EEPROM.
▪ Read the contents of a single cell, but write the contents of an
entire block of cells.
▪ Flash devices have greater density.
▪ Higher capacity and low storage cost per bit.
▪ Power consumption of flash memory is very low, making it
attractive for use in equipment that is battery-driven.
▪ Single flash chips are not sufficiently large, so
larger memory modules are implemented using
flash cards and flash drives.
Flash memory contd……
◾ A big challenge in the design of a computer system
is to provide a sufficiently large memory, with a
reasonable speed at an affordable cost.
◾ Static RAM:
▪ Very fast, but expensive, because a basic SRAM cell has a complex circuit making it
impossible to pack a large number of cells onto a single chip.
◾ Dynamic RAM:
▪ Simpler basic cell circuit, hence are much less expensive, but significantly slower than
SRAMs.
◾ Magnetic disks:
▪ Storage provided by DRAMs is higher than SRAMs, but is still less than what is
necessary.
▪ Secondary storage such as magnetic disks provide a large amount
of storage, but is much slower than DRAMs.
Disk

Disk drive

Disk controller
 Sector 0, track 1
Sector 3, trackn
Sector 0, track 0

Figure Organization of one surface of a disk.

◾ A disk system has 10 recording surfaces with 2048 track per
surface,64 sector per track and 512 bytes of data per sector.
The inner and outer diameter of the cylinder 5 and 9 inch.
a. What is track density?
b. What is total capacity of disk?
c.What is data transfer rate, if rotational speed is 2600
rpm?
d. What is maximum bit density?
surface=10
track/surface=2048
sector/track=64
bytes/sector=512
diameter=5 inch inner
diameter=9 inch outer

a)Track density=(Tracks/Surface)/((Radius of outer

cylinder- Radius of inner cylinder))
=2048/((4.5-2.5))
=1024 tracks/inch
b)Total capacity of disk
=bytes/sector*sector/track*track/surface*number of surface
=512*64*2048*10
=671088640 bytes
=67.10 *10^7 bytes

c)Data transfer rate=(sector/track*byte/sector*

rotational speed)/60
=(64*512*2600)/60
=14.14 * 10^4 bytes/s
◾ d) Bit Density = Bit capacity of all tracks is same but
maximum bit density will occur along the inner track.
Max bit density=(sector/track *
bit/sector)/(circumference of inner track)
=(64*512*8)/(Pi*5)
=16697.07 bit/inch
~~16698 bits/inch
◾A disk system has 18 data recording with
1024 tracks/surface. There are 16
sector/track, each sector containing 1024
bytes. The inner and outer diameter of disk is
5 and 9 inch respectively.
1) What is total disk capacity?
2) What is track density?
3) What is maximum bit density?
◾ What is the average access time for transferring
512 bytes of data with the following specifications-
◾ Average seek time = 5 msec
◾ Disk rotation = 6000 RPM
◾ Data rate = 40 KB/sec
◾ Controller overhead = 0.1 msec
TIMETAKEN FOR ONE FULL AVERAGE ROTATIONAL
ROTATION- DELAY-

Time taken for one full Average rotational delay

rotation = 1/2 xTime taken for one full
= (60 / 6000) sec rotation
= (1 / 100) sec = 1/2 x 10 msec
= 0.01 sec = 5 msec
= 10 msec
TRANSFERTIME- AVERAGE ACCESSTIME-

Transfer time
= (512 bytes / 40 KB) sec Average access time
= 0.0125 sec = Average seek time +
= 12.5 msec Average rotational delay +
Transfer time + Controller
overhead + Queuing delay
= 5 msec + 5 msec + 12.5 msec
+ 0.1 msec + 0
= 22.6 msec
◾ Storage devices can also be implemented using optical
means. The familiar compact disk(CD), used in audio
systems, was the first practical application of this
technology.

◾ Soon after, the optical technology was adapted to the

computer environment to provide a high capacity read-only
storage medium known as a CD- ROM.
◾ The first generation of CDs was developed in the mid-1980s
by the Sony and Philips companies. The technology
exploited the possibility of using a.
◾ digital representation for analog sound
signals. To provide high-quality sound
recording and reproduction, 16-bit samples of
the analog signal are taken at a rate of 44,100
samples per second.
◾ Initially, CDs were designed to hold up to 75
minutes, requiring a total of about 3 × 10bits
(3 gigabits)of storage. Since then, higher-
capacity devices have been developed
◾ The optical technology that is used for CD
systems makes use of the fact that laser light
can be focused on a very small spot.
◾ A laser beam is directed onto a spinning disk,
with tiny indentations arranged to form a
long spiral track on its surface.
◾ The indentations reflect the focused beam
toward a photo detector, which detects the
stored binary patterns.
◾ The laser emits a coherent light beam that is
sharply focused on the surface of the disk.
Coherent light consists of synchronized
waves that have the same wavelength.
◾ If a coherent light beam is combined with
another beam of the same kind, and the two
beamsare in phase, the result is a brighter
beam.
◾ But, if the waves of the two beams are 180
degrees out of phase, they cancel each other.
◾ Thus, a photo detector can be used to detect
the beams. It will see a bright spot in the first
case and a dark spot in the second case.