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A novel design technique to speed-up the charge pump and improve the
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 International Review on Computers and Software (I.RE.CO.S.), Vol. 5, n.6

A Novel Design Technique to Speed-up the Charge Pump

and improve the Stability of PLLs

Gh. R. Karimi1, R. E. Atani2, A. Taleb Baygi1

Abstract – In this paper, a novel technique for increasing the stability of integer-N CMOS
Phase Locked Loops (PLLs) is presented. The method is based on the change of load capacitance
which improves the stability of the second order PLL. Indeed, when PLL is in transient state and
system is locked to proposed output frequency, there is a stable position in PLL that helps to
decrease spurious frequency wave to affect on the jitter of the system. Consequently, we have an
automatic switch that recognizes the transient state from steady state, which is based on phase
difference and it does not need to know the transient time. This method uses excess output to
cancel the accumulated phase error. The paper also presents a design method to speed-up the
frequency step response of the system by alteration bandwidth in transient state. The key
parameter considered in this technique is the loop filter resistance which improves raise time
responding to step response in PLL. The simulation results show that the proposed PLL achieves
the setting time of 130 ns with phase margin of 78 ° for output frequency of 2 GHz when N = 4.
Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved.

Keywords: Integer-N, Charge pump phase locked loops, Stability, automatic switch.

bandwidth for the optimum spectrum is often found to be

I. Introduction
While operating high-frequency and high performance
electronic systems, the problems which in the
distribution of clock signal throughout entire system are
encountered. An external clock cannot be used, thus
creating the need for an on-chip clock multiplier for
high speed products, Phase-Locked Loops (PLLs) have
been employed. PLLs have been played an important
role in communication systems, such as for bit timing
estimation, demodulation, and frequency synthesis.
Typical applications of the PLL can be found in analog
modulators and demodulators.
Robustness is an essential property for a control system
design. To observe plant disturbances or model
uncertainties, frequency response analysis and stability
margins have been used to measure a system's
performance. The stability of the PLLs is a crucial issue
in the design to guarantee the PLL system, show the
correct results. Settling time is another important
characteristic of the PLL frequency synthesizers. It is
affected by bandwidths critically, that includes lock time
and output spectrum. A wider loop bandwidth directly
translates to a faster locking. So, the bandwidth must be
maximized to minimize locking time. On the other
hand, a very wide bandwidth brings more spurs and
component noise (except VCO noise) into the PLL’s
output spectrum. But a very narrow bandwidth brings
more VCO phase noise into the spectrum. Hence, this
smaller than 0.1 reference frequency [3,], [1], [11], [12].
There are different strategies in the design of PLLs. The
most applied ones are based on first order PLL and
second order PLLs. First order PLL is more stable than
second order design but, the second order PLL is used to
cancel the problem of overshoot and jumps in transient
time. The second order PLL uses a load capacitance in
loop filter to decrease these jumps. The equation (1)
shows the suggested values for this capacitance to
achieve a stable position: [2]
Cp Cp
< Cl < (1)
10 5
The choice of Cl in equation (1) is important. This
limitation is created by some facts that low value of this
capacitance helps to stabilize the system by increasing
the phase-margin but, the main problem for ignoring the
jumps, is not solved and on the other hand, high value of
Cl is not good for the stability of PLL and achieving a
fast response from system. The behavioral impacts of the
choice of Cl in PLL stability and speed of its response
will be studied in section II. The working status of PLLs
can be classified into two modes. The transient mode
and the steady time that PLL is locked in proposed
point. Settling time is the amount of time spent during
transient state and bandwidth can impress this time. The
main goal is to find the most suitable Cl until there is no
overshoots in transient state and at the same time

Manuscript received September 2010, revised November 2010 Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved
 GH. R. Karimi, R. E. Atani, A. T. Baygi
increasing the stability similar to first order PLL in
steady state and having a decreasing transient time
without any effects on the stability.
Observations show that the best way for omitting
influence of each kind of change on other parameters to
decrease settling time or improve stability, is the
separation of transient state from steady state in the PLL
[1], [4]. Regarding this idea, we need a switchable
circuit. In some papers, a lock timer circuit is used
which is responsible to choose transient time boundaries
[1]. The lock timer can be realized in a variety of ways
[15]-[17]. But this method is so complicated and it needs
to have knowledge about the changing time of the states
of PLL. For example if PLL is used in RF receiver,
designer should know when the reference pulses would
change. The main goal of this paper is to present a
method so the PLL can recognize transient time from
stable time. We describe the basic ideas and also the
details of this method in Section III.
Finally, for establishment of a fast PLL, it is
necessary to maximize the bandwidth which is against
the conditions of smaller bandwidth to optimize the
spectrum. To find the best tradeoff, a variable-bandwidth
scheme is employed in PLL frequency synthesizers [5].
In this approach, a wider bandwidth is used during
transient to accelerate phase locking, but once a PLL
enters a phase-locked steady state, the bandwidth is
shifted to a smaller value to attain optimum spectrum.
This scheme exploits the fact that lock time matters only
in transient state while spectrum matters only in steady
state. The main idea of the reported work here is based
on controlling the resistor and load capacitance of the
loop filter to speed-up the charge pump and improve the
stability of the PLL automatically.
The rest of the paper is organized as follows: Section
II describes the stability of different load capacitors.
Then the phase margin, locking time and the effect of
the resister on settling time is evaluated. Section III
presents the switchable circuit and its operation. The
simulations results of the CMOS circuit of proposed
approach is found in Section IV. In section V, an
optimal observation in PLL design is presented. Section
VI calculates the jitter from spectral output in the PLL
and finally paper concludes in Section VII.
II. Operating Principles and Architecture
II.1. Load capacitance architect
PLL is composed of Phase Frequency Detection
(PFD), charge pump; low pass filter, VCO and feedback
divider which each of them has special functionality. In
Manuscript received September 2010, revised November 2010
this work, the used PFD, operates at 1.5 GHz [6], which
is faster than PFD designs of [13], [14]. The VCO
generates frequency of 2 GHz with gain of 2.5 GHz/V,
[7], and then divider N=4, formed by two D Flip-flops
[8].
This section intends to design the loop filter. During
the design the method of choosing the optimum load
capacitance is presented. We show how this important
parameter in closed loop PLL is effective on PLL system
stability. The stability of the closed loop system in this
case depends on the order of the low pass filter. If the
low pass filter is of the first order, then the system is
always stable irrespective of the parameters such as
VCO gain, phase detector gain, low pass filter gain and
divider ratio. If the low pass filter is of higher order i.e.,
second, third or fourth then the stability should be
checked for each system individually [8]. In first order
PLL and open loop PLL, there is one serried resistance
with one capacitance that produce one zero in
w z = 1 R p C p and one pole in the origin. In the second
order filters, it is composed of one serried resistance
with one capacitance which have another load
capacitance in parallel in loop filter which adds one pole
1
in w p = in open loop filter. Using one of
R p (C L || C P )
the known techniques such as Routh's criterion, Nyquist
theorem, Root Locus, Bode plot, etc. the stability of the
system can be checked. Using MATLAB we solved the
mathematical model of the proposed system in frequency
domain. Now, we study the behavior of PLL stability
when the value of C L changes and we use the Bode Plot
and Root Locus to prove the stability of the overall
system by checking the stability of the low pass filter.
Figure 1 shows the circuit of passive loop filter.
Fig. 1. The figure of low pass filter in second order PLL.
The Bode Plot and Root Locus of the transfer function
of the open loop system in condition
of R p = 5kW , Cp = 1nF , CL = 0.1nF is shown in Fig. 2.
The results show the system is unstable because phase
margin is low and it is 1.2 ° at 9.57e+07 rad/s. Now, we
change the value of C L to 0.1 PF. Figure 3 shows the
Bode Plot and Root Locus of the first open loop system.
The gain and phase margin are calculated from the Fig.
3 and the results show this system is stable with phase
margin of 36.4° at 2.71e+09 rad/sec.
According to the results, it is clear that C L should
become less to increase the phase margin and stability,
Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved
 GH. R. Karimi, R. E. Atani, A. T. Baygi

but the order of system changes to first order. This kind
of PLL has the disadvantage of jumps on the control
voltage of VCO, which does not allow it to be locked in
proposed voltage in PLL system when current of charge
pump is flowing in loop filter.
state because the frequency of jumps has been increased.
The quantities chosen in the loop filter is given as the
following: R p = 5kW , C p = 1nF , CL = 0.1 pF ; For
N = 4 the bandwidth of PLL is 70 MHz; so, the rate
B × WPLL 1
of = . But, this value is not good for the
f ref 7.14
design of PLLs and must be changed for optimum
system which is fully described in section V.

Fig. 2. (a) Root Locus (b). Bode Plot of the open loop filter
for C L = 100 pF .

Fig.4 (a) Bode plots of the magnitude and phase of the open loop transfer
Fig. 3. (a). Root Locus (b). Bode Plot of the open loop filter
function. (b) Second-order loop filter with a switch.
for C L = 0.1 pF .
When the value of C L is relatively large, the lock time
is long and in steady state, PLL gets an unstable state II.2. Achieving of a good bandwidth Switching
hence there are unwanted waves that influence on jitter parameter
at output in steady state. In our method, first, in filter Consider a general charge-pump PLL frequency
design, in order to achieve the optimal bandwidth (based synthesizer with a second-order loop filter [see Fig. 5a].
on the value of gain in PLL), the values of R p , Cp are The frequency division ratio N d can be an integer or a
accounted and then we try to find the load capacitance fractional number. The open-loop transfer function of
( CL ) by solving the problem of waves in locked state this synthesizer is according to (2).
with switch-able Circuit. In fact, with choice of one q ( s) KVCO I 0 F ( s)
A W ( s) = div = × × (2)
capacitance with big value in transient time, the impact q REF (s ) 2p N d s
of jumps and overshoot is decreased in this time and also Where KVCO is the VCO gain, I 0 is the charge-
with choice of a small capacitance in steady state, we
pump current, and F (s ) is the input impedance of the
increase the phase margin that can help the stability in
stable state. According to fig.4a for this capacitance loop filter given by (3).
( C L ) the phase margin is small and when PLL stands in 1 1 + SRC2
F (s ) = × (3)
locking position, switch S1 becomes open-circuit as s(C1 + C2 ) 1 + SRC||

shown in fig.4b and low value capacitance ( C'L ) is put C1 × C 2

Where C|| = . The magnitude and phase of
in loop filter in steady state. In this condition, phase (C1 + C 2 )
margin is more than previous state and it helps the A 0 (s ) are then given by equation (4) and (5) [1].
stability. Small capacitance removes low jumps in stable

Manuscript received September 2010, revised November 2010 Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved
 GH. R. Karimi, R. E. Atani, A. T. Baygi

According to Fig. 6 the structure of the circuit is one

KVCO I 1 + ( SRC2 ) 2 1
A 0 ( s) = × 0 × × (4) XOR gate, in which calculates ΔΦ in inputs and also
2p (C1 + C 2) N d 1 + ( SRC|| ) 2 s 2 consists of a kind of buffer which is composed of two
F (s ) » tan -1( sRC2 ) - tan -1 (sRC|| ) - 180 (5) inverters for producing desired boundary. Switch can be
designed for different phase boundary and certain
The Bode plots of them are shown with solid lines in
reference frequency limitation by changing architect of
Fig. 5b, where the unity gain frequency is denoted by
its buffer. Anyway, we can change this Φo = 18° to up or
wc = w and the phase margin at wc is signified by F M down range with choosing (W/L) ratio of each inverter.
, that wc is given by equation (6) [2].
IpK0
wC = ×R (6)
2p 1 + N
Now according to equation (6), we need to increase
the bandwidth by a factor of α at the onset of a transient
state while keeping the switch S2 as an open-circuit as
shown in Fig. 5c and loop filter resistance is αR (α>1).
This can be done by simultaneously reducing loop
parameter, R (loop filter resistance) by a factor of a in
steady state.
This adjustment replaces ω in (4) and (5) with w / a .
This rescaling of ω corresponds to parallel translation of
the pole and zero by log a along the ω axis in the log
scale, resulting in the dashed lines in Fig. 5b. These
parallel translations produce the desired results: 1) the
change of the unity gain frequency from wc to
aw c corresponds to the proportional bandwidth
enhancement; 2) The phase margin at the new unity
gain frequency is smaller than the old unity gain
frequency just in transient state. So, wider bandwidth
and decreasing the raising time helps to decline settling
time in transient state and it is exchanged to optimal
frequency bandwidth and phase margin by S2 switch
when the PLL locks. [See Fig. 5c]
The operation of this switch is effective in fast
variable-bandwidth PLL to support system in different
position. It works in opposite performance of Sl switch
to do its duty, correctly. Eventually, it seems phase
margin in transient time is unusually different and also
it is not influenced on action of system, but this factor is
sensitive in steady state.

III. XOR-KEY design Fig. 5. (a) General charge-pump PLL model with a second order loop
filter. (b) Bode plots of the magnitude of the open loop transfer function.
Figure 6 shows the diagram of designed circuit which The solid and dashed lines correspond to the smaller and larger bandwidth
works as a switch. This switch is automatic and cases, respectively. (c) Second-order loop filter with a switch.
recognizes transient state from steady state and it is
based on phase difference (ΔΦ) of input clock pulse.
Actually, the designed circuit is sensitive to one angle as
a boundary in Φo = 18° for comparison of phase
difference in certain reference frequency limitation. In
this kind of switch when ΔΦ < 18° or ΔΦ = 18° the
output work as an open-circuit, as shown in Fig. 7 and
when ΔΦ > 18°, the output of circuit works as a close-
circuit, as shown in Fig. 8 (phase difference 18° in Fig 6 . XOR-KEY switch circuit.
reference frequency 500 MHz equals to the time
In fact, while this switch is placed in PLL, maybe that
difference 100 PS in time domain).
switch works in opposing application. Thus, with placing
Manuscript received September 2010, revised November 2010 Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved
 GH. R. Karimi, R. E. Atani, A. T. Baygi

a PMOS MOSFET instead of NMOS MOSFET in
output, the switch works as open-circuit in transient state
and for steady state, switch output acts as short
connected. The inputs of switch are connected to outputs
of PFD (UP, DOWN).
It can be said that switch output is similar as 10KΩ
resistance, in open-circuit condition and a100Ω
resistance, in close-circuit condition.
changing the load capacitance (CL) to small compensated
capacitance (Co) and increasing the phase margin.
The problem of this circuit is low level jumps in steady
state. One method for solving this problem is decreasing
the charge pump current (Ip ) and loop filter resistance
(Rp) that expound in section 5. The other method is by
the use of the dummy switches that used in this design in
order to reduce the charge injection as shown in the
following Fig. 13, [9].

(a)

(a)

(b)

(c)
Fig. 7. a) Operation of outputs of switch in lock state for Δt = 100 PS. b) (b)
output voltage and c) the current of the switch (peak to peak of current Fig. 8. a) Operation of outputs of switch in lock state for Δt = 400 PS. b)
signal is ±100μA). output voltage and current switch (peak to peak of current signal is
±500μA).

IV. Simulation Results

The software used in this section is ADS and the
measurement results on silicon using a 2.5 V TSMC
0.13 mm CMOS process. The used schematic of PLL is
shown in Fig. 9 and Fig. 10. The general PLL output
without the use of switch circuit is shown in Fig.11 and it
can be seen that there is an unstable state for this PLL
when it is entered in lock state. The component values of
the implemented loop filter of Fig. 10 are CL = 10 pF, Cp
= 1 nF, Rp = 5 kΩ and Ip = 2.3 mA. The low phase margin
for the PLL causes the sinusoidal output in steady state as
shown in Fig. 11. Figure 12 shows the measured response
of the PLL using the XOR-KEY switch (adaptive switch)
which produces a stable state and it takes place with Fig. 9. Charge-pump PLL architecture with dual switch. b) Optimum
PLL schematic structure

Manuscript received September 2010, revised November 2010 Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved
 GH. R. Karimi, R. E. Atani, A. T. Baygi

According to the results it can be seen that phase error is

reducing to zero and the resulted settling time is near to
40 ns for N= 4 and CKref = 500 MHz. Also PLL is locked
in Vcontrol = 1.31 V and fout = 2 GHz.
According to section II, it is shown to bring an enduring
condition of an unstable PLL and it is possible to select
parameter easily and there is no worry for stability.
Additionally, improvement in stability is earned by
correct operation of mentioned switch and it guarantees
the stable state.

Fig. 13. Dummy switch circuit.

Fig. 10. Optimum PLL schematic structure
V. Final optimization
In this part, we try to achieve the best position in circuit
for bandwidth, loop gain, settling time, jumping range
in lock state, and minimization in phase difference.
The Bode Plot and Root Locus of the transfer function of
the open loop system in condition of Rp = 1 kΩ, Cp =
46.6 pF, CL = 3 pF is shown in Fig. 14a. The results
show that the system is stable and phase margin is 58.1°
at 1. 58e+08 rad/s.
Fig. 14b shows the Bode Plot and Root Locus of the
open loop system while the value of CL has been
changed to 0.5 PF. The gain and phase margins are
calculated from the graphs and the results show that the
system is stable with phase margin 78° at 1.82e+08
rad/sec and system becomes more stable. Thus, in this
step of design, system is stable, generally but, it has been
helped to raise phase margin and stability without
impact on overshoot in transient state

Fig. 11. Output voltage control oscillator in PLL for CL = 10 PF without

switch circuit.

(a)

Fig. 12. Output voltage control oscillator in PLL for Cl = 10 PF with

switch circuit and compensated capacitance (Co=1 PF)

Manuscript received September 2010, revised November 2010 Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved
 GH. R. Karimi, R. E. Atani, A. T. Baygi

(c)

(b)
Fig 14 . Root Locus and Bode Plot of the open loop filter for (a) CL = 3
PF (b) CL = 500 FF.

For this case, results are indicated in Hspice model by

ADS software in two parts, with compensated
capacitance (Co=500fF) and without it; According to
Fig. 15a when PLL changes to first order, the system
has jumps in steady state. As, it has been seen from Fig.
(d)
15.b, this problem is canceled by the use of Fig. 15. Output voltage control oscillator in PLL for CL = 3 PF with
compensating capacitance. switch circuit and (a) without compensated capacitance (b) with
The option of XOR-KEY switch inside of PLL shows compensated capacitance (Co=0.5 PF). The simulation waveforms when
the PLL is locked for (c) up and down (d) Inputs (i1, i2)
that PLL in lock state has minimum difference phase
almost near to zero observed in Fig. 15c and 15d. Of
course if there is no compensated capacitance as shown
Fig. 15a, system works as a first order system and
stability is better. But, compensated capacitance
(Co=500fF) is used for losing these jumps in lock state.

Fig. 16. The simulation jumps on filter output when the PLL is locked

The target frequency synthesis plan for the PLL with the
following parameter is summarized as: Cp = 46.6 PF, Rp
= 1 KΩ, CL = 3 PF, Co = 500 fF and Ip = 0.5 mA.
(a)
TABLE I
SHOWS THE PARAMETERS OF THE DESIGNED PLL
Parameter Value
Loop bandwidth 10.6 MHZ
Settling-time 200 NS
Phase error <0.1 NS
Cycle Jitter 3.37 PS
Reference frequency 500 MHZ
Output frequency 2 GHZ

Figure 16 shows the variation of VCTRL when the

optimum PLL is locked, where VCTRL is the output
(b)
signal of the charge pump. The maximum variation in
Fig. 16 is less than 50mV at all PVT (process, supply
voltage, temperature) corners. Fig. 17 shows a feature of
XOR-KEY output voltage and current. It can be seen

Manuscript received September 2010, revised November 2010 Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved
 GH. R. Karimi, R. E. Atani, A. T. Baygi

that the structure of the PLL is changed in 270 ns time Fig. 18 . Optimal output voltage control oscillator in PLL
and difference phase is zero nearly. This is because of
the effect of the switch circuit. Although, the switch
At the end, to have a better inside, the output spectrum
operates at 270 ns and current becomes zero, the switch
frequency of VCO, in circuit level simulation, is shown
output works as an open circuit after this time.
in Fig. 19. As it can be seen there is a good achievement
Consequently, by adding the other switch to exchange
goal such as bandwidth in the design.
the loop filter resistance from 15 KΩ in transient state to
0.94KΩ in lock state, the bandwidth of system is
changing from 63.66 MHz to 10.73 MHz, respectively.
VI. Output Jitter
Figure 18 shows the result of this work that it is
deducted the settling time from 200 NS to 130 NS.
Corresponding to Fig. 18, raise time is decreased by The PLL output jitter was measured with the transmitter
changing the loop filter resistance in transient time that it launching a NRZ sequence of alternating ones and zeros.
can be done by using an additional switch to exchange
the loop filter resistance. When PLL enters to locked
state, the desired switch would act, gradually and it puts
load resistor (Rp') out in system. The key parameter in
this step is: Cp = 46.6 PF, Rp = 0.9 KΩ, Rp‫=׳‬15 KΩ, C L
= 3 PF, Co = 710 fF and Ip = 0.5 mA.

Fig. 19. VCO output spectrum.

(a)

Fig. 20. Measured closed-loop transmitter output spectrum at frequency of

2 GHz (2.5 V, N = 4). Spectrum illustrates Nyquist carrier at 2 GHz with
reference spurs at Δ f = 500 MHz

(b)
Jitter was extracted from the frequency spectrum as
Fig. 17. XOR-KEY output a. current and b. voltage available time-domain instruments could not achieve sub
pico-second accuracy. To extract jitter, we relate the
power of some frequency spur, in dBc at an offset Df from
the carrier frequency fc to the corresponding RMS jitter.
From analysis of single-tone frequency modulation with
small modulation index, it can be shown that [10]:

[ dBc ( Df )]
10 10
2
I rms (Df ) = (7)
2p 2 f c 2

We extract the total RMS jitter by integrating (7) across

Df of 1 kHz to 100 MHz beyond which the spectrum

Manuscript received September 2010, revised November 2010 Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved
 GH. R. Karimi, R. E. Atani, A. T. Baygi

analyzer noise floor is dominant. As an example, the [6] M. Mansuri, D. Liu and C. K. Yang, “Fast Freq Uency Acquisition
Phase-Frequency Detectors for GSamples/s Phase-Locked Loops”,
transmitter output demonstrates 3.37 ps RMS jitter at 2
IEEE J. solid-state Circuits, VOL. 37, NO. 10, OCTOBER 2002.
GHz with reference spurs at 30.45 dBc (Fig. 20). Most [7] C. Wang, G. Sung, J. Huang and L. Lin, “An 80MHz PLL with
of this random jitter falls within the loop bandwidth of a 72.7ps peak-to-peak jitter”, Microelectronics Journal, Vol. 38, pp.
716-721, April 2007.
reasonable receiver PLL. In Fig. 15, jitter from the
[8] A.A. Telba, S.M. Qasim, J.M. Noras and B. Almashary and M.A. El
reference spurs falls outside the bandwidth of jitter Ela, “Behavioral Modeling and Simulation of Dual Cascaded PLL
integration and is excluded from the computed jitter as it Based Frequency Synthesizer”, MIXDES '07, pp. 407-411, June
contributes negligible error. As the results of this work, 2007.
[9] Ge Fuding, PFD-CP Phase Locked Loop Design, 2001.
the measured optimum PLL performance and comparison [10] A.L.S. Loke, R.K. Barnes, T.T. Wee, M.M. Oshima, C.E.
are summarized in Table II. Moore, R.R. Kennedy and M.J. Gilsdorf, “A Versatile 90-nm
CMOS Charge-Pump PLL for SerDes Transmitter Clocking”, IEEE
J. Solid-State Circuits, Vol. 41, No. 8, August 2006.
[11] F. M. Gardner, “Charge-pump phase-lock loops,” IEEE Trans.
Com., Vol. COM-28, No. 11, pp. 1849–1858, Nov. 1980.
[12] B. Razavi, RF Microelectronics. Upper Saddle River, NJ: Prentice-
TABLE II
Hall, 1998.
OPTIMUM PLL PERFORMANCE AND COMPARISON
[13] H. Partovi et al., “Flow-through latch and edge-triggered flip-flop
Parameters w. switches w.o. switch hybrid elements”, IEEE Int. Solid-State Circuits Conf. Dig. Tech.
Settling time 130 NS 200 NS Papers, San Francisco, CA, pp. 138–139, Feb. 1996.
Run time 1518 S 917 S [14] H. Ebenhoech, “Make IC digital frequency comparators”, Electron.
B.W. in steady state 10.73 MHz 10.6 MHz Design, Vol. 15, No. 14, pp. 62–64, July 1967.
P.M. in steady state 78º 58.1° [15] M. Keaveney, P. Walsh, M. Tuthill, C. Lyden and B. Hunt, “A
Settling time 130 NS 200 NS 10 ms fast switching PLL synthesizer for a GSM/EDGE base-
Run time 1518 S 917 S station”, IEEE ISSCC Dig. Tech. Papers, 2004, p.p. 192–193.
[16] B. Memmler, E. Gotz and G. Schonleber, “New fast-lock PLL for
mobile GSM GPRS applications”, Proc. 26th ESSCIRC, Sep. 2000,
As it can be seen from these results, the proposed pp.468–471.
method seems to have good and optimal parameters in [17] D. Banerjee, PLL Performance, Simulation, and Design, 4th ed.
Santa Clara, CA: National Semiconductor, 2005.
PLL design.

VII. Conclusion Authors’ information

In this research, a novel technique to improve the Gholam Reza Karimi,
1
application of PLLs is introduced. This method is Department of Electrical Engineering
Razi University
composed of two efficient techniques: One is the use of
Kermanshah, Iran
the notion of variable-bandwidth PLL and variable- ghkarimi@razi.ac.ir
phase margin for optimization in settling time and
stability and the other one is designing an automatic Reza Ebrahimi Atani (Corresponding author)
2
Department of Computer Engineering
switch that can recognize different states (transient and
The University of Guilan
steady states) to support variable-condition for PLL and P.O. Box 3756
it can be designed for different noisy environment by Rasht, Iran
changing the optional boundary (Φ0 = 18º). This design rebrahimi@guilan.ac.ir
helps to expel the trace of noise in PLLs. Finally the
Abolfazl Taleb Baygi
simulation results confirmed the design goals and PLL 1
Department of Electrical Engineering
characteristics in stability and settling time improved Razi University
alot. Kermanshah, Iran
talebbegi_elec@yahoo.com

References
[1] K. Woo, Y. L. E. Nam and D. Ham, “Fast-Lock Hybrid PLL
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[2] B. Razavi, Design of Analog CMOS Integrated Circuits,
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Manuscript received September 2010, revised November 2010 Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved

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