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Circuit Design For That PCB
Circuit Design For That PCB
Circuit Design For That PCB
Fig. 4: Actual-size, single-side PCB layout for the speed checker Fig. 5: Component layout for the PCB
whenever reset switch S2 is pushed. timer IC3. The output of IC3 is used cade counter and an output decoder
For IC2, the monostable is triggered for driving piezobuzzer PZ1, which that converts the Johnson code into a
in the same way as IC1 when the ve- alerts the operator of speed-limit vio- 7-segment decoded output for driving
hicle intersects the laser beam incident lation. Resistor R9 and capacitor C5 DIS1 display. The counter advances by
on LDR2 to generate a small pulse for decide the time period for which the one count at the positive clock signal
stopping the count and for use in the piezobuzzer sounds. transition.
speed detection. LED2 glows for the The output of IC1 triggers the The carry-out (Cout) signal from
duration for which pin 3 of IC2 is high. bistable (IC4) through gate N2 at the CD4026 provides one clock after ev-
The outputs of IC1 and IC2 are fed leading edge of the count-start pulse. ery ten clock inputs to clock the suc-
to input pins 2 and 1 of NAND gate When pin 2 of IC4 goes low, the high ceeding decade counter in a
N1, respectively. When the outputs of output at its pin 3 enables astable clock multidecade counting chain. This is
IC1 and IC2 go high simultaneously generator IC5. Since the count-stop achieved by connecting pin 5 of each
(meaning that the vehicle has crossed pulse output of IC2 is connected to pin CD4026 to pin 1 of the next CD4026.
the preset speed limit), output pin 3 of 6 of IC4 via diode D1, it resets clock A high reset signal clears the de-
gate N1 goes low to trigger monostable generator IC5. IC5 can also be reset cade counter to its zero count. Pressing
CMYK