Department of Computer Science & Engineering

H.K.E Society’s Sir M V College of Engineering

(Affiliated to VTU - Belagavi, Approved by AICTE – New Delhi, Accredited by NAAC)
Yeramarus amp, Raichur – 584135

Question Bank-3

Subject Name with Code DDCO (22BCS302) Academic 2023-24

Year
Faculty Name Geetha. N

Module-1,2 and module-5

Q Questions Max CO RBT
No. Marks Mapped Level
Minimize the expression of sop using K-map and draw a
logic circuit using basic gates.
a> Y=Σm (5,1,3,4,0)
01 05 CO1 L1,L2
b> Y= Σm (4,5,12,9,7,13)
c> Y=πm (1,4,5,6,7,9,13,15)
d> Y= πm (0,6,7,8,12,13,14,15)
Find the reduced SOP form of the following functions using
K map.
a. F(ABCD)= Σm (1,3,7,11,15) + d(0,2,4)
02 05 CO1 L1,L2
b. F(ABCD)= Σm (0,7,8,9,10,12) + d(2,5,13)
c. F(ABCD)= πm(0,3,4,7,8,10,12,14) +d(2,6)
d. F(ABCD)= π m(0,2,3,8,12,14,15)+d(1,4,5,11)
Design a logic circuit using AND, OR, Inverter Gates with 4
inputs D,C,B,A that will produce 1 output Y. Output is high
03 05 CO1 L1,L2
whenever 2 adjacent input variables are 1`s and also D & A
is treated adjacent. Draw the K-Map
04 Explain NAND and NOR implementation with an example 05 CO1 L1,L2
05 Explain HDL program structure with an example 05 CO1 L1,L2
06 Explain half adder and full adder with its implementation 05 CO2 L1,L2
What is a multiplexer? Explain any 2 types of multiplexer.
07 Implement the following Boolean function using 8:1 mux, 05 CO2 L1,L2
F(ABCD)= Σm(0,1,3,4,8,9,15).
What is a decoder. Show that using 3 to 8 line decoder and
multi input OR gate, the following Boolean function can be
realized.
08 05 CO2 L1,L2
a. F1(ABC) = Σm(0,4,6)
b. F2(ABC) = Σm(0,5)
c. F3(ABC) = Σm(1,2,3,7)
09 What is encoder, Explain priority encoder. 05 CO2 L1,L2
10 What is a flip-flop. Explain SR, D, T, JK flip-flops 05 CO2 L1,L2
Write and explain the control sequence for execution of
11 05 CO5 L1,L2
the instruction ADD(R3), R1.
Explain the working of single bus organization of data path
12 05 CO5 L1,L2
with neat diagram.
What is pipeline? Explain the four stages pipeline with its
13 05 CO5 L1,L2
instruction execution steps and hardware organization
Explain how a word is fetched form memory with neat
14 05 CO5 L1,L2
timing diagram

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