ASAHI KASEI [AKD4360]

AKD4360
Evaluation board Rev.A for AK4360

GENERAL DESCRIPTION
The AKD4360 is an evaluation board for the 20bit audio D/A converter with headphone amp, AK4360.
The AKD4360 has the interface with AKM’s wave generator using ROM data and with AKM’s A/D
converter evaluation boards. Therefore, it is easy to evaluate the AK4360. The AKD4360 also has the
digital audio interface and can achieve the interface with digital audio systems via opt-connector.

„ Ordering guide

AKD4360 --- Evaluation board for AK4360

FUNCTION

• Head-phone Output circuit

• On-board clock generator
• Compatible with 2 types of interface
- Direct interface with AKM’s A/D converter evaluation boards and direct interface
with AKM’s signal generator (AKD43XX) by 10 pin header
- DIR with optical input/output
• BNC connector for an external clock input

VDD = 1.8 ∼ 3.3V GND

CS8412 Opt In
Lch (DIR)
Headphone 10pin Header
AK4360 A/D Input
ROM Data
Clock
Rch Generator

HP_VCC = 0.9 ∼ 3.3V

Figure 1. AKD4360 Block Diagram

* Circuit diagram and PCB layout are attached at the end of this manual.

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„ Analog Output Circuit

Analog signals are output through BNC connectors on the board or headphone jack. The output level is about 0.275Vpp
(@-11dB input).
J1
AOUTL
LINE
JP7

+
AOUTL pin HPL
R2
0.22u C20 16

JACK
220u
10

HP_GND pin
J2 HEADPHONE

JACK
JP9

+
AOUTR pin HPR
J3
0.22u C21 AOUTR
220u
LINE
10
R4
16

Figure 2. Output buffer circuit on board

* AKM assumes no responsibility for the trouble when using the circuit examples.

(1) Signal of AOUTL and AOUTR pins are output via J1 and J3.

JP7 JP9
HPL HPR

LINE JACK LINE JACK

(2) Signal of AOUTL and AOUTR pins are output via J2 (mini jack).

JP7 JP9
HPL HPR

LINE JACK LINE JACK

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„ Operation sequence

1) Set up the power supply lines.

[VDD] (orange) = 1.8 ∼ 3.3V : for VDD of AK4360 (typ. 2.0V)
[HP_VCC] (orange) = 0.9 ∼ 3.3V : for HP_VCC of AK4360 (typ. 1.2V)
[VP] (red) = 1.8 ∼ 5.0V : for 74HC4050 (typ. 2.0V)
[VD] (red) = 3.4 ∼ 5.0V : for logic (typ. 5.0V)
[AGND] (black) = 0V : for analog ground (including VSS of AK4360)
[DGND] (black) = 0V : for logic ground

Each supply line should be distributed from the power supply unit.
VP and VDD must be same voltage level.

2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)

3) Power on.
The AK4360 should be reset once bringing SW1 (PDN) “L” upon power-up.

Note : Does not install the AK4110 and the all parts for the AK4110 on the board.

„ Evaluation mode

Applicable Evaluation Mode

(1) Evaluation of D/A using DIR (Optical Link) <default>

(2) Evaluation of D/A using ideal sine wave generated by ROM data
(3) Evaluation of D/A using A/D converted data
(4) All interface signals including master clock are fed externally.

(1) Evaluation of D/A using DIR (Optical Link) <default>

PORT2 (TORX176) is used. DIR generates MCLK, BICK, LRCK and SDATA from the received data through
optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to
PORT1 (ROM).

JP3 JP5 JP10 JP11 JP13 JP14

BICK LRCK XTE XTI 8412_VD 4110_VD

ADC DIR ADC DIR ON OFF ON OFF

CS8412
AK4110

EXT
XTL

JP4 JP6 JP8 JP15

CS/AK_BICK CS/AK_LRCK CS/AK_SDATA CS8412/AK4110

4110 8412 4110 8412 4110 8412 4110 8412

Note : Does not install the AK4110 and the all parts for the AK4110 on the board.

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(2) Evaluation of D/A using ideal sine wave generated by ROM data

Digital signals generated by AKD43XX are used. PORT1 (ROM) is used for the interface with AKD43XX.
Master clock is sent from AKD4360 to AKD43XX and BICK, LRCK, SDATA are sent from AKD43XX to
AKD4360. Nothing should be connected to PORT2 (TORX176). In case of using external clock through a BNC
connector (J4), select EXT on JP11 (XTI) and short JP10 (XTE).

JP3 JP5 JP10 JP11 JP13 JP14

BICK LRCK XTE XTI 8412_VD 4110_VD

ADC DIR ADC DIR ON OFF ON OFF

CS8412
AK4110

EXT
XTL
(3) Evaluation of D/A using A/D converted data

It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s A/D evaluation boards with PORT1 (ROM). Nothing should be connected to PORT2 (TORX176). In
case of using external clock through a BNC connector (J4), select EXT on JP11 (XTI) and short JP10 (XTE).

JP3 JP5 JP10 JP11 JP13 JP14

BICK LRCK XTE XTI 8412_VD 4110_VD

ADC DIR ADC DIR ON OFF ON OFF

CS8412
AK4110

EXT
XTL

(4) All interface signals including master clock are fed externally.

Under the following set-up, all external signals needed for the AK4360 to operate could be fed through PORT1
(ROM). Nothing should be connected to PORT2 (TORX176).

JP3 JP5 JP10 JP11 JP13 JP14

BICK LRCK XTE XTI 8412_VD 4110_VD

ADC DIR ADC DIR ON OFF ON OFF

CS8412
AK4110

EXT
XTL

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„ BICK Frequency
JP12
[JP12]: When BICK is fed from 74HC4040 on board,
its frequency is selected with JP12. X_BICK
64fs : BICK = 64fs (Figure 3)
64fs
32fs : BICK = 32fs
32fs

Figure 3. BICK Frequency

„ Other jumper pins set up

[JP1] (GND): Analog ground and digital ground

open: separated <default>
short: common (The connector “DGND” can be open.)

[JP2] (BICK2): BICK phase of AK4360

THR: The phase of BICK is not inverted. <default>
INV: The phase of BICK is inverted.

„ DIP switch set up

Upper-side is “H” and lower-side is “L”.

[SW3] (4360_MODE) : Set the mode of AK4360.

No. PIN ON OFF

1 CKS 384fs 256fs
2 BOOST BOOST ON BOOST OFF
3 DEM Enable Disable
4 MT1
See Table 2
5 MT0
Table 1. Set the SW3

Gain mute time Level mute time MT1 MT0

x 1 (=21845/fs) 1024/fs 0 0
x 1/2 (=10923/fs) 1024/fs 0 1
x 1/4 (=5461/fs) 1024/fs 1 0
x 3/4 (=16384/fs) 1024/fs 1 1
Table 2. Set mute time (1=“H”, 0=“L”)

[SW5] : (DIR_MODE) Set the mode of CS8412 and AK4360.

PIN
PIN No. 1 2 3 4 5 6 7 8 JP2
Name M2 M1 M0 DIF BICK2
16bit LSB 1 0 1 0 THR
I2S 0 1 0 1 THR
Table 3 . Set the SW5 (Case of CS8412)

* SW5-8 is a switch for setting DIF pin of AK4360.

* SW5-4, 5, 6, 7 are not used.

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„ The function of the toggle SW

Upper-side is “H” and lower-side is “L”.

[SW1] (PDN): Resets the AK4360. Keep “H” during normal operation.
[SW2] (MUTE): Mute of the AK4360. “H” : MUTE, “L” : Normal operation.

„ Indication for LED

[LED1]: Indicate whether the input data of CS8412 is pre-emphasized or not.

[LED2] (VERF): Monitor ERF pin of the CS8412. LED turns on when some error has occurred to CS8412.

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„ Mute Function

In the normal operation (PDN = “H” and MUTEN = “H”), the analog outputs do the gain mute operation and level mute
operation when MUTEN pin goes “L”, the analog outputs are muted to HP_GND (0V) finally. The level mute operation is
fixed to 1024/fs. The gain mute time is set by MT0 and MT1 pins. If the sampling frequency is slow, the gain mute time
can be shortened by the set of MT0 and MT1 pins (Refer to Table 4). Figure 4 shows the mute on/off timing example. *fs
means sampling frequency.

When PDN pin goes “H” and MUTEN pin goes “L”, HP-AMP is only powered-down. And when PDN and MUTEN pins
go ”L”, HP-AMP and DAC are powered-down. Then, power supply current about a few 10uA is flowed to internal mute
control circuit from HP_VCC power supply. (Refer to Table 5)

MT1 MT0 Gain Mute Time Level Mute Time Total Time
L L x 1 (=21845/fs) 1024/fs 22869/fs
L H x 1/2 (=10923/fs) 1024/fs 11947/fs
H L x 1/4 (=5461/fs) 1024/fs 6485/fs
H H x 3/4 (=16384/fs) 1024/fs 17408/fs
Table 4. Mute Time Setting

Mode PDNpin MUTEN pin DAC State HP-Amp State

1 H H Normal operation Normal operation
2 H L Normal operation Power-down
3 L L Power-down Power-down
4 L H Inhibit
Table 5. About PDN and MUTEN pins

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(1)
(7) (7)

AOUTL(R) (3)
(Analog)

(5) (6) (4) (6) (5)

0V Output

PDN pin

MUTEN pin
(2)

DAC State Normal Operation Power down Normal Operation

HP-AMP Normal Operation Power down Normal Operation

State
(8)
Input Data Normal Operation Normal Operation
(Digital)
Clock In (MCLK, BICK, LRCK)

Figure 4. Mute on/off timing example

(1): PDN pin should change “H” into “L” after analog outputs are muted.
(2): This is time (about 1ms) until DAC and HP-AMP are powered up after PDN = “H”.
(3): After DAC and HP-AMP are powered-up, MUTEN pin should be “H”.
(4): When MUTEN pin goes “L”, analog outputs are connected to HP_GND.
(5): Level mute time: 1024/fs = 23ms@fs=44.kHz
(6): Gain mute time: 21845/fs = 495ms@fs=44.1kHz, MT1-0 = “00”
(7): Mute total time: 22869/fs = 518ms@fs=44.1kHz, MT1-0 = “00”
(8): When the external clocks (MCLK, BICK and LRCK) are stopped, the DAC and HP-AMP should be in the
power-down mode (PDN = “L”, MUTEN = “L”).

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MEASUREMENT RESULTS

[Measurement condition 1]
• Measurement unit : Audio Precision, System two
• MCLK : 256fs
• BICK : 64fs
• fs : 44.1kHz
• Bit : 20bit
• Power Supply : VDD = 2.0V, HP_VCC = 1.2V
• Interface : DIR
• Temperature : Room

Parameter Result (Lch / Rch) Unit

THD+N (0dB Output) -21.7 / -21.7 dB

THD+N (-11dB Output) -49.4 / -48.8 dB
D-Range (-60dB, A-weighted) 92.8 / 92.8 dB
S/N (A-weighted) 93.1 / 93.1 dB
Interchannel Isolation 83.4 / 84.7 dB

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„ Plot

AKM AK4360 THD+N vs. Input Level

VDD=2.0V, HPVCC=1.2V, fs=44.1kHz, fin=1kHz, BOOST=OFF

+0

-10

-20

-30

d -40
B
r -50

A -60

-70

-80

-90

-100
-120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0
dBFS

Figure 1. THD+N vs. Input Level

AKM AK4360 THD+N vs. Input Frequency

VDD=2.0V, HPVCC=1.2V, fs=44.1kHz, Input=-11dBFS, BOOST=OFF

-30

-40

-50

d
B -60
r
-70
A

-80

-90

-100
20 50 100 200 500 1k 2k 5k 10k 20k
Hz

Figure 2. THD+N vs. Input Frequency

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AKM AK4360 Linearity

VDD=2.0V, HPVCC=1.2V, fs=44.1kHz, fin=1kHz, BOOST=OFF

+0

-20

-40
d
B
r -60

A
-80

-100

-120
-120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0
dBFS

Figure 3. Linearity

AKM AK4360 Frequency Response

VDD=2.0V, HPVCC=1.2V, fs=44.1kHz, Input=0dBFS, BOOST=OFF

+1

-0

-1

-2

-3
d
B -4
r
-5
A -6

-7

-8

-9

-10
20 50 100 200 500 1k 2k 5k 10k 20k
Hz

Figure 4. Frequency Response (BOOST=OFF)

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AKM AK4360 Frequency Response

VDD=2.0V, HPVCC=1.2V, fs=44.1kHz, Input=0dBFS, BOOST=ON

+1

-0

-1

-2

-3
d
B -4
r
-5
A -6

-7

-8

-9

-10
20 50 100 200 500 1k 2k 5k 10k 20k
Hz

Figure 5. Frequency Response (BOOST=ON)

AKM AK4360 Crosstalk

VDD=2.0V, HPVCC=1.2V, fs=44.1kHz, Input=0dBFS, BOOST=OFF

-60

-65

-70

-75

d
-80
B

-85

-90

-95

-100
20 50 100 200 500 1k 2k 5k 10k 20k
Hz

Figure 6. Crosstalk

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AKM AK4360 FFT Plot (Input=0dBFS)

VDD=2.0V, HPVCC=1.2V, fs=44.1kHz, fin=1kHz, BOOST=OFF

+0

-20

-40

d -60
B
r -80

A -100

-120

-140

-160
20 50 100 200 500 1k 2k 5k 10k 20k
Hz

Figure 7. FFT Plot (Input=0dBFS)

AKM AK4360 FFT Plot (Input=-11dBFS)

VDD=2.0V, HPVCC=1.2V, fs=44.1kHz, fin=1kHz, BOOST=OFF

+0

-20

-40

d -60
B
r -80

A -100

-120

-140

-160
20 50 100 200 500 1k 2k 5k 10k 20k
Hz

Figure 8. FFT Plot (Input=-11dBFS)

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AKM AK4360 FFT Plot (Input=-60dBFS)

VDD=2.0V, HPVCC=1.2V, fs=44.1kHz, fin=1kHz, BOOST=OFF

+0

-20

-40

d -60
B
r -80

A -100

-120

-140

-160
20 50 100 200 500 1k 2k 5k 10k 20k
Hz

Figure 9. FFT Plot (Input=-60dBFS)

AKM AK4360 FFT Plot

VDD=2.0V, HPVCC=1.2V, fs=44.1kHz, fin=None, BOOST=OFF

+0

-20

-40

d -60
B
r -80

A -100

-120

-140

-160
20 50 100 200 500 1k 2k 5k 10k 20k
Hz

Figure 10. FFT Plot (Input=“0” data)

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 5 4 3 2 1

JP1 L1 HP_VCC
GND VDD (short) L2
Digital Ground Analog Ground 2 1 1 2
VD for 74HCU04, 74HC14, VP for 74HC4050 1 2
C2 + (short)
74HC4040 +
C1 C3 47u C4
47u 0.1u 0.1u
C5 + C6 + C10
47u 47u 0.1u
D C7 C8 C9 D
0.1u 0.1u 0.1u

C11 C12
0.1u 10u

U1A
1 2 INV
74HCU04
C14 C15 C16 C17 C18 C19
JP2 10u 0.1u 0.1u 1u 0.1u 1u
THR BICK2
+ + +
ADC

JP3
BICK X_BICK
DIR

C PORT1 C
MCLK 1 10
BICK 2 9
LRCK 3 8
SDTI 4 7 CS8412_BICK AK4110_BICK
AD/ROM5 6
8412 4110 U2A
JP4 74HC4050 U?
CS/AK_BICK 3 2 1 MCLK TST1 24
2 PDN TST2 23
3 BICK VDD 22
VD JP5 X_LRCK U2B 4 SDATA VSS 21
LRCK ADC 74HC4050 5 LRCK VREF 20
5 4 6 19
R1 PD- MT0 7
MT0 VCOM
18
DIR

10k MT1 8
MT1 TST3
17
DEM DEM HP_VCC
U2C 9 MUTEN HP_GND 16
74HC4050 BOOST 10 BOOST NC 15
CS8412_LRCK AK4110_LRCK 7 6 11 CKS AOUTL 14 J1
CKS 12 13 AOUTL
DIF DIF AOUTR
8412 4110 LINE
JP6 U2D AK4360
CS/AK_LRCK 74HC4050 JP7

+
9 10 HPL
R2
0.22u C20 16
U2E 220u

JACK
74HC4050
B
11 12 10 B

U2F
CS8412_SDATA AK4110_SDATA 74HC4050
8412 4110 MUTE 14 15
JP8
CS/AK_SDATA
J2 HEADPHONE

JACK
CS8412_MCLK AK4110_MCLK
JP9

+
HPR
X1 J3
11.2896MHz 0.22u C21 AOUTR
1 2 220u
LINE
10
R3 1M
JP10 R4
XTE U1B U1C 16
3 4 5 6 U4
10 CLK Q1 9
74HCU04 74HCU04 JP11 Q2 7
A C22 C23 AK4110 1 5 11 RST Q3 6 64fs JP12 A
CS8412 2 6 Q4 5 X_BICK
XTL 3 7 Q5 3
X_BICK
J4 EXT 4 8 Q6 2
EXT U1D Q7 4
9 8 XTI Q8 13 32fs
Q9 12
R5 74HCU04 Q10 14 fs X_LRCK Title
51 15
Q11
Q12 1 AKD4360
Size Document Number Rev
74HC4040
A3 AK4360 A
Date: Thursday, June 15, 2000 Sheet 1 of 2
5 4 3 2 1
 5 4 3 2 1

VD VD

1
R6 R7
D1 10k D2 10k
U5A U5B U5C U5D VP
2

2
1 2 3 4 5 6 9 8
PD- MUTE
D L H 74HC14 74HC14 L H 74HC14 74HC14 D
3

1
C24 C25 SW3
0.1u SW1 0.1u SW2 MT0 6 5
PD- MUTE MT1 7 4
DEM 8 3
BOOST
2

2
9 2
CKS 10 1

VD 4360_MODE

1
R8
D3 10k
U5F U5E

2
13 12 11 10
4110_PD RP1
L H 74HC14 74HC14 5
MT0
4
MT1

1
C26 3
DEM
0.1u SW4 2
BOOST
4110_PD 1
CKS
2
47k

VP VD
C C
CS8412_SDATA

SW5
DIF 9 8
10 7
VD M1 11 6
12 5
L3
ON

13 4
LED1 10u M0 14 3
JP13 1 2 1 2 M1 15 2
8412_VD M2 16 1
OFF

U6 U1E R9 LED2 VD
C27 1 C VERF 28 11 10 2 1 DIR_MODE
0.1u R11 2 Cd/F1 Ce/F2 27
R10 3 Cc/F0 SDATA 26 74HCU04 1k VERF
1k 4 Cb/E2 ERF 25
1k 5 Ca/E1 M1 24 M0
6 C0/E0 M0 23 RP2
7 22 1
8
VD+ VA+
21 C28 2
DIF
DGND AGND +
9 RXP FILT 20 R12 C30 3
10 RXN MCK 19 10u 0.1u 4
C31 11 FSYNC M2 18 C29 5
0.01u 12 17 1k 47n 6
13
SCK M3
16 7
M0
14
CS12/FCK SEL
15 8
M1
U CBL CS8412_MCLK 9
M2
B
CS8412 B
47k
CS8412_LRCK

CS8412_BICK

M2

VD
2

C32
L5 0.01u
10u
1

+
8412

PORT1 C37 C38

6 6 GND 4 10u 0.1u
VCC 3
GND 2
5 5 OUT 1 JP15
CS8412/AK4110
TORX176
A 4110 A

Title
AKD4360
Size Document Number Rev
A3 Interface A
Date: Wednesday, January 17, 2001 Sheet 2 of 2
5 4 3 2 1
 IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use
or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support,
or other hazard related device or system, and AKM assumes no responsibility relating to any such use,
except with the express written consent of the Representative Director of AKM. As used here:
a. A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or
damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.