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EV3101 1K DSP EVALUATION BOARD

EV3101 OVERVIEW
The EV3101 test board allows the user to evaluate the 1KM(AL3101). It can
be evaluated in both its serial and parallel mode via the supplied development
software. It can also be evaluated with boot code from an EEPROM. The EV3101
inputs and outputs can be either analog, Alesis format optical or from a user supplied
emulator interface. Numerous jumpers and testpoints aid in the flexibility. An area
on the board is set aside for any additional circuitry the user may want to add.
Expansion connectors are provided for system expansion.

EV3101 POWER/GND CONNECTIONS

The AC input power jack is at J2. The power cable for it is provided with the
EV3101 kit. The country of origin should be specified when ordering the EV3101 kit
as the user’s specific AC power requirements will be met with the correct power cable
supplied. The DC voltages for the board are created on-board from this AC power
through on-board regulators. The on-board DC voltages created are +5V(can be
monitored at T1), +12V(can be monitored at T3) and –12V(can be monitored at T4).
If the user wants to use other DC voltages besides these then the user must
disconnect the AC power cord and remove or cut R1/R2/R3 depending on the DC
voltages wanted. If the user wants to change to an off-board +5V then R2 must be
clipped/removed and the DC input applied at T1. If the user wants to change to an
off-board +12V then R1 must be clipped/removed and the DC input applied at T3. If
the user wants to change to an off-board -12V then R3 must be clipped/removed and
the DC input applied at T4. T2 is provided as a ground reference from/to these DC
sources.
T9, T15, T25, T33, T34, T40, T46, T54 and T55 are GND test points and can
be used for oscilloscope or other test equipment ground connections. There is one
ground on the board (see PCB layout section).
R9 is provided as a resistor to measure the current being supplied to the 1KM.
Use testpoint T28 to see what the VDD of the 1KM is. Use T28 to monitor the 3.3V
regulator line of the 1KM.

EV3101 AUDIO INPUT CONNECTIONS

There are two analog inputs, one for the Left Channel and one for the Right
Channel. These are unbalanced BNC inputs, J9 for the Left Channel and J18 for the
Right Channel. If a BNC cable is not available “alligator” clips or other similar devices
may be used to clip onto the signal side of the jack and onto the ground side of the
jack or onto T33/T55 ground pins. An 8Vpp signal at J9 or J18 is the maximum
amplitude signal allowable before clipping occurs at the ADC.
There is one Alesis optical digital input from J33’s Oprec side. A test point for
optical input is available on test point T52. A test point to monitor the error rate of
the optical input is provided on T49. A high on this error pin while the optical input
is in use indicates an error receiving data and the validity of the connection should be
checked before proceeding with AL3101 evaluation.

Alesis Semiconductor
EV3101-0800 12509 Beatrice Street .
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
 EV3101 AUDIO OUTPUT CONNECTIONS
There are two analog outputs, one for the Left Channel and one for the Right
Channel. These are unbalanced BNC outputs, J29 for the Left Channel and J31 for
the Right Channel. If a BNC cable is not available “alligator” clips or other similar
devices may be used to clip onto the signal side of the jack and onto the ground side
of the jack or onto T33/T55 ground pins. An 8Vpp signal is the maximum amplitude
output at J29 or J31.
There is one Alesis optical digital output from J33’s OpGen side. A test point
for optical output is available on test point T53. U0_IN(T51) and U1_IN(T50) are used
to output any user bits(non-audio) in the optical data stream. To be used these test
points must be tied to the appropriate external driving pin through a wire clip.
The noise floor of the audio output may be poorly affected by the RS-232 cable
creating a ground loop or corruption of the ground floor at low frequencies due to a
noisy computer environment. If undesirable to the user the RS-232 cable may be
disconnected after the program is loaded to the 1KM. When the connection is needed
again the cable can be plugged back in and testing continued.

EV3101 RS-232 CONNECTION

J32 is used to connect to the kit supplied RS-232 cable that interfaces to the
user’s designated serial port on the computer. The male side attaches to the EV3101
and the female side attaches to the computer serial port.

EV3101 EXPANSION CONNECTORS

J1 and J3 are the expansion connectors. Through J1 the 1KM can be
expanded to accept serial inputs and outputs directly from/to the connector. Also
+5V and GND can be expanded outward. J3 allows port pins to be accessed in an
emulator environment. It also allows for an external EEPROM interface and for +5V
and GND expansion.

EV3101 WORD CLOCK SELECT CIRCUITRY

The Master WCLK for the board is monitored at T29 and derived from right to
left with jumpers J22, J21 and J20. The Master WCLK is either generated on-board
via a divided-down 12.288MHz crystal (M2), externally with a user-supplied WCLK(via
T30 and a ground connection e.g. T25) or externally via the Alesis optical connection
and the AL1402(U16). Alternatively a WCLK can be supplied from a standalone
87c31 microprocessor or emulator on the U9 socket (U9 existing chip must be
removed).
The Jumpers J20/J21/J22 set the Master WCLK source for the board. See
Table 1 for the setting of the jumpers for each desired WCLK source.

MasterWCLK = Set J20 to Set J21 to Set J22 to

XTALWCLK WCLKBRD WCLK XTALWCLK
EXTWCLK WCLKBRD WCLK EXT_WCLK
OPWCLK WCLKBRD OPWCLK N/A
MICROWCLK MICROWCLK N/A N/A
TABLE 1. MasterWCLK Select.. “N/A” denotes that jumper can be either
way. EV3101 shipped with crystal(XTAL) as default setting.

Alesis Semiconductor
EV3101-0800 12509 Beatrice Street .
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
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 When using clocks other than the internal crystal clock J30 must be set to
“GND” to disable the internal clock. This will minimize interference from two clocks at
the same frequency on the board at the same time.
The AL3101, AL1101, AL1201, AL1401A only need the Master WCLK as a
clock input to function. The AL1402 is in Master Mode and supplies a WCLK(i.e.
OPWCLK). In crystal mode the MCLK(at T36) the BCLK(at T48) and the \BCLK(at
T47) are available as outputs to the user if needed but are not used to clock anything
on the board.
Use available inverters or user-supplied ICs to improve/change external clocks
or data as needed.

EV3101 RESET CIRCUITRY

J23 is the 1KM reset jumper. It should be set to “\RESET” which is the reset from
the EV3101 board, i.e. a power-up reset in combination with a switch selectable reset
at S1. It can be set to “\MICRORESET” for use with an emulator if desired.

1KM INTERFACE JUMPERS

J14 is the “\AUTOLOAD” jumper. It should be set to “\ALOADSEL” for proper
use with the supplied development software. It is set to “GND” when autoloading of
the EEPROM program on power-up is desired(see EEPROM USE section).
J19 is the serial/parallel mode select pin. It should be set to “\SERINSEL”
which is the configurable line from the microprocessor. This allows the mode to be
configured through the supplied development software. When the jumper is removed
the internal pull-up of the 1KM allows an autoload from EEPROM to happen. Setting
jumper to “GND” is not needed within the software development system. The board
uses D0 and D1 to interface serially to the 1KM when \SERINSEL is low.

1KM AUDIO INPUT SELECT CIRCUITRY

The inputs to the AL3101 audio serial inputs(SER_IN0-3) can be selected
through jumper settings and can be monitored on T5-T8. Each input is a stereo
pair(i.e. L/R). See Table 2 below to see how the serial input is selected.

For SERIN0= Set J5 to Set J4 to

ADCDATA ADCDATA SERIN
OPIN0 N/A OPIN0
MICROSERIN MICROSERIN SERIN
TABLE 2. Serin0 Select.. “N/A” denotes that jumper can be either way.
For SERIN(1/2/3) Select change OPIN0 TO OPIN(1/2/3) and J4 to J(6/7/8)
within table. In the SERIN mode of J4/5/6/7 multiple inputs can be fed by the
same source from J5. Each optical input pair(OPIN0-3) is fixed from a dedicated
optical input channel pair from U16. Microserin is designed for use with
emulator if desired.

Alesis Semiconductor
EV3101-0800 12509 Beatrice Street .
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
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 1KM AUDIO OUTPUT SELECT CIRCUITRY
The outputs at the 1KM audio serial outputs(ser_out0-3) can be selected
through jumper settings and can be monitored on T41-T44. Each output is a stereo
pair(L/R). See Table 3 below to see how the serial output direction is selected.

For SEROUT0 to go to Set J24 to Set J25 to

DACDATA DACDATA SEROUT
OPOUT0 N/A OPOUT0
MICROSEROUT MICROSEROUT SERIN
TABLE 3. Serout0 Select.. “N/A” denotes that jumper can be either way.
To select SEROUT(1/2/3) change OPOUT0 TO OPOUT(1/2/3) and J25 to
J(26/27/28) within table. In the SEROUT mode of J25/26/27/28 care should
be taken not to tie outputs together as only one SEROUT channel pair should be
selected as an output at a time. Each optical output pair(OPOUT0-3) is fixed to
go to a dedicated optical output channel pair(via U17). Microserout is designed
for use with an emulator if desired.

EV3101 STANDALONE EEPROM USE

The AT17C65 serial EEPROM(U4) is provided for use on the board to store a
standalone program. Complete data on it is available at WWW.ATMEL.COM. It is
shipped unprogrammed. The chip can be programmed using standard IC
programmers. The chip cannot be programmed in-system but this may change in the
future.
To load the code from the EEPROM to the AL3101 the “\AUTOLOAD”
jumper(J14) should be set to “GND” on power up and the “/SERIALM” jumper(J19)
should be removed to allow the internal pull-up of the “/SERIALM” pin to bring
“/SERIALM” high. The /PRGEN jumper(J13) should be set to “+5V” to enable
EEPROM loading to the AL3101. The “D1/SCC” jumper(J10) should be set to
“SCC”(serial communication clock). The “D0/SCD” jumper(J15) should be set to
“SCD”(serial communication data). The “SCC” jumper(J11) and the “SCD”
jumper(J16) should be set for INTernal mode if the on-board EEPROM is being used
or to EXTernal mode if an off-board EEPROM is being used(brought in through the
expansion J1 connector). If the INTernal(on-board) EEPROM is being used then the
“EEDATA” jumper(J17) and the “EECLK” jumper(J12) should be set to INTernal mode.
See the AL3101 data sheet under “Autoload Interface” for more information on loading
code from the EEPROM.

Alesis Semiconductor
EV3101-0800 12509 Beatrice Street .
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
-4-
 EV3101 CIRCUIT LAYOUT
The EV3101 uses a two-layer PCB with ground as a continuous copper pour
on the bottom of the PCB. This insures the best performance. One continuous
ground plane over the whole PCB is adequate. A ground plane directly under the chip
reduces any EMI emissions emanating from the chip. The PCB traces and
components are split into a digital side and an analog side. With this approach high
frequency digital traces are kept away from sensitive analog traces. All 0.1uF bypass
caps are as close as possible to their respective pins that they are trying to filter.
Surface mount capacitors allow the closest distance to the pin. Ceramic capacitors of
an X7R variety are used for the bypassing. Electrolytic capacitors(10uF) are connected
to the power lines. For the AL1101, AL1201, AL1401A and AL1402 circuit layouts
please see their respective datasheets and evaluation board documents.

Alesis Semiconductor
EV3101-0800 12509 Beatrice Street .
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
-5-
 NOTICE

Alesis Semiconductor reserves the right to make changes to their products or to discontinue
any product or service without notice. All products are sold subject to terms and conditions
of sale supplied at the time of order acknowledgement. Alesis Semiconductor assumes no
responsibility for the use of any circuits described herein, conveys no license under any
patent or other right, and makes no representation that the circuits are free of patent
infringement. Information contained herein is only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has
been carefully checked, no responsibility is assumed for inaccuracies.

Alesis Semiconductor products are not designed for use in applications which involve
potential risks of death, personal injury, or severe property or environmental damage or life
support applications where the failure or malfunction of the product can reasonably be
expected to cause failure of the life support system or to significantly affect its safety or
effectiveness.

All trademarks and registered trademarks are property of their respective owners.

Contact Information:

Alesis Semiconductor
12509 Beatrice Street
Los Angeles, CA 90066
Phone: (310) 301-0780
Fax: (310) 306-1551

Email: sales@alesis-semi.com

Copyright 2000 Alesis Semiconductor

Datasheet August 2000
Reproduction, in part or in whole, without the prior written consent of Alesis Semiconductor
is prohibited.

Alesis Semiconductor
EV3101-0800 12509 Beatrice Street .
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
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