Field Effect Transistors

What is FET?
FET is a type of semiconductor device which is having a semiconductor-based channel
connected to two electrodes. The two electrodes named the drain and the source connected to
either end. It has a third electrode named the gate which controls the current flow between the
given two electrodes named the drain and the source.
Working of FET Transistor
It has 3 terminals: gate, drain, and source. The working principle is as per the following:
To allow electrons or holes to flow between the source and drain terminals, they are doped
with material of the n-type or p-type variety.

An electric field is created in the channel area between the source and drain when a voltage is
applied to the gate terminal. This electric field modulates the conductivity of the channel,
behaving like a “valve” that controls the current flow between the source and drain. For an n-
channel FET, applying a positive voltage to the gate attracts free electrons into the channel,
increasing its conductivity and allowing more current to flow between the source and drain.
For a p-channel FET, a negative voltage on the gate repulses holes, expanding conductivity.
By changing the gate voltage, the conductivity and current flow through the channel can be
finely controlled. This permits FETs to be utilized as electronic switches and in amplifying
circuits. The electric field effect gives a high input impedance and low noise performance,
making FETs valuable in RF applications and as sensitive analog signal amplifiers.

There are two basic types of field effect transistors:

(i) Junction field effect transistor (JFET)
(ii) Metal oxide semiconductor field effect transistor (MOSFET
(i) Junction field effect transistor (JFET)
A junction field effect transistor is a three terminal semiconductor device in which current
conduc tion is by one type of carrier i.e., electrons or holes.
In a JFET, the current conduction is either by electrons or holes and is controlled by means of
an electric field between the gate electrode and the conducting channel of the device. The
JFET has high input impedance and low noise level.
Construction of JFET: A JFET consists of a p-type or n-type silicon bar containing two pn
junctions at the sides as shown in Fig.19.1. The bar forms the conducting channel for the
charge carriers. If the bar is of n-type, it is called n-channel JFET as shown in Fig. 19.1 (i)
and if the bar is of p-type, it is called a p-channel JFET as shown in Fig. 19.1 (ii). The two pn
junctions forming diodes are connected *internally and a common terminal called gate is
taken out. Other terminals are source and drain taken out from the bar as shown. Thus a JFET
has essentially three terminals viz., gate (G), source (S) and drain (D)

Principle of JFET: The two pn junctions at the sides form two depletion layers. The current
conduction by charge carriers (i.e. free electrons in this case) is through the channel between
the two depletion layers and out of the drain. The width and hence *resistance of this channel
can be controlled by changing the input voltage VGS. The greater the reverse voltage VGS,
the wider will be the depletion layers and nar rower will be the conducting channel. The
narrower channel means greater resistance and hence source to drain current decreases.
Reverse will happen should VGS decrease. Thus JFET operates on the prin ciple that width
and hence resistance of the conducting channel can be varied by changing the reverse voltage
VGS. In other words, the magnitude of drain current (ID) can be changed by altering VGS.

The working of JFET :

(i) When a voltage VDS is applied between drain and source terminals and voltage on the
gate is zero [ See Fig. 19.3 (i) ], the two pn junctions at the sides of the bar establish depletion
layers. The electrons will flow from source to drain through a channel between the depletion
layers. The
size of these layers determines the width of the channel and hence the current conduction
through the bar.
(ii) When a reverse voltage VGS is applied between the gate and source [See Fig. 19.3 (ii)],
the width of the depletion layers is increased. This reduces the width of conducting channel,
thereby increasing the resistance of n-type bar. Consequently, the current from source to drain
is decreased. On the other hand, if the reverse voltage on the gate is decreased, the width of
the depletion layers also decreases. This increases the width of the conducting channel and
hence source to drain current.
It is clear from the above discussion that current from source to drain can be controlled by the
application of potential (i.e. electric field) on the gate. For this reason, the device is called
field effect transistor. It may be noted that a p-chan nel JFET operates in the same manner as
an n -channel JFET except that channel current carriers will be the holes instead of electrons
and the polarities of VGS and VDS are reversed.
Schematic Symbol of JFET:

Difference Between JFET and Bipolar Transistor:

JFET
(i) In a JFET, there is only one type of
carrier, holes in p-type channel and
electrons in n-type channel. For this reason,
it is also called a unipolar transistor.
(ii) As the input circuit (i.e., gate to source)
of a JFET is reverse biased, therefore, the
device has high input impedance
(iii) The primary functional difference
between the JFET and the BJT is that no
current enters the gate of JFET (i.e. IG =
0A)
(iv) In JFET, there are no junctions as in an
ordinary transistor. The conduction is
through an n- type or p-type semi-conductor
material. For this reason, noise level in
JFET is very small.
Bipolar Transistor
(i) In an ordinary transistor, both holes and
electrons play part in conduction. Therefore,
an ordinary transistor is sometimes called a
bipolar transistor.
(ii) the input circuit of an ordinary transistor
is forward biased and hence has low input
impedance.
(iii) typical BJT base current might be a few
μA while JFET gate current a thousand
times smaller
(iv) Bipolar Transistor, there are junctions
as in an ordinary transistor. The conduction
is through an n- type or p-type semi-
conductor material. For this reason, noise
level in JFET is very high.

JFET Characteristics:

In the above image, a JFET is biased through a variable DC supply, which will control the
VGS of a JFET. We also applied a voltage across the Drain and Source. Using the variable VGS,
we can plot the I-V curve of a JFET.
In the above I-V image, we can see three graphs, for three different values of VGS voltages, 0V,
-2V and -4V. There are three different regions Ohmic, Saturation, and Breakdown region.
During the Ohmic region, the JFET acts like a voltage controlled resistor, where the current
flow is controlled by voltage applied to it. After that, the JFET gets into the saturation
region where the curve is almost straight. That means the current flow is stable enough where
the VDS would not interfere with the current flow. But when the VDS is much more than the
tolerance, the JFET gets into the breakdown mode where the current flow is uncontrolled.

This IV curve is almost the same for the P channel JFET too, but there are few differences
exist. The JFET will go into a cut-off mode when VGS and Pinch voltage or (VP) is same. Also
as in the above curve, for N channel JFET the drain current increase when the VGS increase.
But for the P-channel JFET the drain current decrease when the VGS increase.

DC Biasing OF JFET:

In fixed DC biasing technique of an N channel JFET, the gate of the JFET is connected in such
a way that the VGS of the JFET remains negative all the time. As the input impedance of a
JFET is very high there are no loading effects observed in the input signal. The current flow
through the resistor R1 remains zero. When we apply an AC signal across the input capacitor
C1, the signal appears across the gate. Now, if we calculate the voltage drop across the R1, as
per the Ohms law it will be V = I x R or Vdrop = Gate current x R1. As the current flowing to
the gate is 0 the Voltage drop across the gate remains zero. So, by this biasing technique, we
can control the JFET drain current by just changing the fixed voltage thus changing the VGS.

There are two basic types of MOSFETs viz.

1. Depletion-type MOSFET or D-MOSFET: The D-MOSFET can be operated in both the

depletion-mode and the enhancement-mode. For this reason, a D-MOSFET is sometimes called
depletion/enhancement MOSFET.
2. Enhancement-type MOSFET or E-MOSFET: The E-MOSFET can be operated only in
enhancement-mode.

There are two types of D-MOSFETs viz (i) n-channel D-MOSFET and (ii) p-channel D-
MOSFET.

(i) n-channel D-MOSFET: Fig. shows the various parts of n-channel D-MOSFET. The p-
type substrate constricts the channel between the source and drain so that only a small passage

remains at the left side. Electrons flowing from source (when drain is positive w.r.t. source)
must pass through this narrow channel. The gate appears like a capacitor plate. Just to the right
of the gate is a thick vertical line representing the channel. The drain lead comes out of the top
of the channel and the source lead connects to the bottom. The arrow is on the substrate and
points to the n-material, therefore we have n-channel D MOSFET. It is a usual practice to
connect the substrate to source internally. This gives rise to a three-terminal device.

(ii) p-channel D-MOSFET: Fig. shows the various parts of p-channel D-MOSFET. The n-
type substrate constricts the channel between the source and drain so that only a small passage
remains at the left side. The conduction takes place by the flow of holes from source to drain
through this narrow channel. It is a usual practice to connect the substrate to source internally.
This results in a three-terminal device whose schematic symbol is shown in Fig.

D-MOSFET Transfer Characteristic:

Fig. shows the transfer characteristic curve (or transconductance curve) for n-channel D-
MOSFET. The behaviour of this device can be beautifully explained with the help of this curve
as under :
 (i) The point on the curve where VGS = 0, ID = IDSS. It is expected because IDSS is the value
of ID when gate and source terminals are shorted i.e. VGS = 0.

(ii) As VGS goes negative, ID decreases below the value of IDSS till ID reaches zero when
VGS = VGS (off) just as with JFET.

(iii) When VGS is positive, ID increases above the value of IDSS. The maximum allowable
value of ID is given on the data sheet of D-MOSFET.