College of Engineering

Electrical Engineering Department

EE 2111: Logic Design

Logic Design Laboratory

Lab Manual
2023/2024

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Table of Contents
Safety Precautions and Guidelines for Electrical Engineering Labs. ............................................. 3
Laboratory Rules and Procedures ................................................................................................... 5
Laboratory Reports Rules ............................................................................................................... 6
Grading ........................................................................................................................................... 7
Introduction to the Lab.................................................................................................................... 8
Experiment #1: Introductory Lab.................................................................................................... 9
Experiment # 2: Introduction to Logic Gates ............................................................................... 20
Experiment # 3: Boolean Functions .............................................................................................. 33
Experiment # 4: Half and Full Adder/Subtractor .......................................................................... 42
Experiment # 5: Decoder-Encoder................................................................................................ 52
Experiment # 6: Multiplexer-Demultiplexer ................................................................................ 59
Experiment # 7: D and JK Flip-Flops ........................................................................................... 71
Experiment # 8: Design of Sequential Circuits and Sequence Recognizer .................................. 79
Experiment # 9: Ripple Counter ................................................................................................... 84

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Safety Precautions and Guidelines for Electrical Engineering Labs.
The following general rules and precautions are to be observed at all times in the laboratory.
These rules are for the benefit of the experimenter as well as those around him. Additional rules
and precautions may apply to a particular laboratory.
• There MUST be at least two people in the laboratory while working on live circuits or
chemical processing.
• Shoes MUST be worn at all times.
• All loose conductive jewelry and trinkets, including rings MUST be removed, which may
come in contact with exposed circuits. (Do not wear long loose ties, scarves, or other
loose clothing around machines.)
• Voltages above 50 V rms AC and 120 V DC are always dangerous. Extra precautions
should be considered as voltage levels are increased.
• Before equipment is energized ensure:
1) Circuit connections and layout have been checked by a Teaching Assistant (TA)
and/or technician.
2) All colleagues in your group give their assent.
• Know the correct handling, storage and disposal procedures for batteries, cells,
capacitors, inductors and other high energy-storage devices.
• Consider all circuits to be "hot" unless proven otherwise.
• When making measurements, form the habit of using only one hand at a time. No part of
a live circuit should be touched by the bare hand.
• Keep the body, or any part of it, away from the circuit. Where interconnecting wires and
cables are involved, they should be arranged so people will not trip over them.
• Be as neat a possible. Keep the work area and workbench clear of items not used in the
experiment.
• Always check to see that the power switch is OFF before plugging into the outlet. Also,
turn instrument or equipment OFF before unplugging from the outlet.
• When unplugging a power cord, pull on the plug, not on the cable.
• When disassembling a circuit, first remove the source of power.
• "Cheater" cords and 3-to-2 prong adapters are prohibited unless an adequate separate
ground lead is provided, the equipment or device is double insulated, or the laboratory
ground return is known to be floating.
• No ungrounded electrical or electronic apparatus is to be used in the laboratory unless it
is double insulated or battery operated.
• Keep fluids, chemicals, and beat away from instruments and circuits.
• Report any damages to equipment, hazards, and potential hazards to the laboratory
instructor.
• If in doubt about electrical safety, see the laboratory instructor. Regarding specific
equipment, consult the instruction manual provided by the manufacturer of the
equipment. Information regarding safe use and possible-hazards should be studied
carefully.

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 • Food, beverages, substances and related utensils shall not be brought into, stored or
consumed in any laboratory.
• Smoking is prohibited in all laboratories at all times.
• Learn and know what to do in an emergency or Electrical Fire.
N.B. Your TA must inspect your workstation prior to your leaving lab.
DO NOT LEAVE UNTIL THE TA HAS INSPECTED YOUR WORKSTATION AND
APPROVED ITS CONDITION.

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Laboratory Rules and Procedures
• Students have to attend all the scheduled experiments. If anybody misses an experiment,
he/she will make it up during the last week of the semester. Students who miss more than
two experiments shall have to repeat the course; i.e., they will have an “F” grade
automatically.
• Experiments are done by groups of students (a maximum of three).
• Experiments start at the scheduled time of the laboratory session when all the members of
the group are ready. Anyone who fails to join the group in 15 minutes will be assumed
absent.
• “Experiment sheets” is given to the students at least one week prior to the experiments.
Students are supposed to study the experiment sheets, read the necessary references, do
the preliminary calculations –if necessary-, and collect enough knowledge about the
experiment before coming to the laboratory. This will be checked by the instructor and
will affect the student’s grade.
• Two copies of the, blank “Experiment Data Sheet” should be prepared before the
experiment. “Experiment Data Sheet” is found at the end of each experiment section.
• All the experimental data (and graphics if necessary) must be written on these sheets.
• The laboratory instructor must sign the sheets. One copy of this sheet will be handed to
the instructor after the experiment. The other will be kept by the students to be used in
prepare the report.
• Students must take all precautions for their own and instruments safety. They will be
liable to replace the instruments or the components, which are damaged due to misuse.
• Students should obey all the “Laboratory Safety Rules” in the lab.
• Students should leave the bench clean and tidy after the experiment. Cleanliness and
orderliness of the laboratory should always be maintained. All instruments should be
switched off before leaving the lab.
• Students repeating a course should attend laboratories fully including submitting the
report. (They will not be exempted from the laboratories).

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Laboratory Reports Rules
• Each student of each group should submit a report of the experimental work with
“Experiment Data Sheet” in one week after the experiment completion date. Grades will
be reduced by 5 points-per-each delayed day. The reports will not be accepted after two
weeks of delay. The first report will be given in a wired file for archiving whereas the rest
will be given in the transparent file.
• The laboratory reports should include the following items:
1. Report cover page: Blank cover page of the experiment can be found at the
appendix. Students should complete this page and make it the first page of the
report.
2. Preliminary work: Should contain the short theory and method of the experiment.
It must not be a repetition of the “background section of the experiment”, given in
the “Experiment sheets”. Below items must be written in your own words:
a) The technical objective of the experiment,
b) Calculations and questions’ answers found in the “Experiment sheets”.
3. Experimental setup: This section should include following:
c) Neat drawing of the experimental setup (indicating all the measuring
instruments, with types and brand names),
d) Equipment list: the list should include the names, manufacturer’s brand names
and model numbers of the instrument,
e) List of the electronic components and other related tools, instruments used in
the experiment.
4. Experimental results: This section should contain following:
f) Calculated data in the preliminary work section in tabular form,
g) All measured values in tabular form,
h) All curves with suitable titles, units and scales on both coordinate axes, on
each graph.
5. Conclusion: It includes:
a) All discussion of the experimental results,
b) Comments on differences between the experimental and theoretical results,
c) Probable sources of errors and the ways of reducing these errors,
d) Personal opinions about the experiments.
• Even though lab reports might be handwritten in pen or in ink, clarity and neatness are
required. Marks can be lost for reports that are not presented in a convenient way.
• Marks are not given for the quantity of material written but for its quality. Comments,
which show that you understand or have thought about what is going on, are valuable.
• Clarity of ideas, thoughts and understanding are essential for increasing your mark.
• Lack of these will reduce your mark. Your report should be legible but does not have to
be a work of art. It is your ideas and experimental ability you will be graded on.

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Grading
The Lab weights 25% of the whole course grade, the following grading scheme will be used:

Technical Reports and Discussions 7%

Prelab 3%
Team Work and Attendance 5%
Concept of the Experiments 5%
Connection Test 5%

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Introduction to the Lab
• Each lab is a 2-hour session
• The lab objective is to introduce students to the practical world of digital system design
and the various digital components. This includes how design digital circuits, how to
simulates them using software packages, and how to construct them using standard
Integrated Circuits (ICs) and other hardware that are readily available commercially.
Students will also be familiarized with the procedure of designing, simplifying, simulating,
implementing and testing many combinational and sequential circuits that explained and
presented in lectures.
• Some parts of the labs do not give you step-by-step instructions on how to do them. They
require you to think carefully about how you are going to do them.
• You will do the labs with the Logisim/LogicWorks software as well as prototype boards
(IC trainer or breadboard) and components that are offered to you. Logisim/LogicWorks
are a free graphical tool for designing and simulating logic circuits. The Logisim and
LogicWorks software can be downloaded from: https://sourceforge.net/projects/circuit/,
and https://www.designworkssolutions.com/logicworks-5-windows/, respectively.
• Every effort will be made to cover the lab materials in class before the scheduled lab period.

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 Experiment #1: Introductory Lab
1. Objective:
• Capabilities and operation of Trainer Kit and basic digital Instruments and devices
necessary to run experiments
• Study the basic characteristics of Basic Digital Gates
• Implementation of Logic Circuits

2. Background
2.1 Digital Integrated Circuits (IC)
A logical device is a digital circuit whose related input and output signals are binary variables, for
example, gates, flip flops, and memories. A logic function is a function that expresses the
relationship between input logic variables and outputs. Logic gates are constructed from integrated
circuits (ICs). ICs contain diodes, transistors, and resistors, required to implement the device, on a
semiconductor base called a chip performing a great variety of logical functions. A logic symbol
is the graphic representation form of the logic function.
The chip itself is enclosed in a protective metal or plastic case called a package. Connecting pins
on the exterior of the package allows input/output signals and power to be transmitted between the
chip and the outside world. A common package is the dual in-line package (DIP); in such a
package, the connecting pins are arranged in two (dual) lines. The packages commonly have a total
of 14, 16, 18, 20, 24, 36, or 40 pins. The pin numbering scheme for 14-, 16-, and 24-pin DIP ICs
is shown below in Figure. A notch in the package usually identifies pin 1.

Figure 1: Dual in-line package.

The different sizes of integration of IC chips are usually defined in terms of the number of logic
gates in a single IC or package. They are classified in one of the following categories:

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 1. Small-scale integration (SSI) device: contains less than 10 gates.
2. Medium scale integration (MSI) device: contains 10 -100 gates
3. Large-scale integration (LSI) device: contains 100 to 10000 gates
4. Very large-scale integration (VLSI) device: contains more than 10000 gates
ICs are classified not only by their scale or logical functions but also by their logic family. An ICs
logic family is determined by the "basic circuit" upon which more complex circuits are based.
Some of the older logic families include:
• TTL (Transistor-Transistor Logic)
• ECL (Emitter-Coupled Logic)
• CMOS (Complementary Metal-Oxide Semiconductor logic)
Compatible physical representations of binary 0 and 1; meaning some families of chips will use
different voltages to represent logic 0 and 1. Therefore, it may not be compatible to build a logic
circuit out of two or more families of chips. The most commonly used physical binary logic system
implementation, and the one that will be used in this manual, unless otherwise mentioned, is called
transistor-transistor logic (TTL). In this system, the quantity of interest is HIGH or LOW voltage.
TTL logic devices are powered by a single +5-volt power supply. Thus, all signal voltages can
only range from 0 to 5 volts. Logic 0 is represented by voltages between 0 and 0.8 volts, and logic
1 by voltages between 2.4 and 5 volts. The region between 0.8 and 2.4 volts is called the threshold
region CMOS features low power consumption and can operate with a supply voltage from +3 to
+ 15 Volts, while TTL uses more power and the supply voltage range is +4.75 to +5.25 Volts. ECL
gates have lower propagation delays (higher speeds) than TTL gates. Typically, the circuit is
powered with Vcc = GND, and Vee = -5.2V. A modern ECL NOR gate is Motorola's M10KH100.
Based on power consumption, pickiness of the supply voltage and high noise margin, one might
always choose CMOS over TTL, but TTL will handle a bit more current drain on its output, a big
reason for choosing TTL over CMOS is that CMOS is easily destroyed by a small “zap” of static
electricity. When working with CMOS, one needs to wear a grounding strap. For this reason, we
will be using TTL logic gates.
Each digital IC has several identifying marks on its package. Generally, the identifier consists of
1. The manufacturer's name or symbol,
2. The number of the device,
3. Special Customer Number.

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Commercial TTL ICs has a number designation that starts with 74 and follows with a suffix that
identifies the subfamilies series type such as Standard: 74xx, High speed 74hxx, low power 74Lxx,
Schottky TTL 74Sxx, Low power Schottky 74LSxx, Advanced Schottky 74ASxx, Advanced low-
power Schottky 74ALSxx.
Most of the members of the non-enhanced TTL family have designations of the form 74XX, where
XX is some two-digit number. For example, a quad NAND gate has the industrial designation
7400. (The form for enhanced TTL is usually things like 74LSXX, while for CMOS it is usually
40XX.)
For example, the part number of the below figure:

Figure 2: 7408 IC pinout.

SN74LS08J
SN: stands for the manufacturer "Texas Instruments"
74: 7400 TTL series
LS: low Schottky type
08: function of a digital IC
J: Ceramic dual-in-line Package
Examples of manufacture's and their symbols are Texas Instruments (SN), National
Semiconductor (DM), and Motorola (MC). Each manufacturer has its own way of making its ICs
for identification and ordering purposes as described in its data books.
2.2 Dealing with IC's
Sometimes you will not damage an IC by shorting one of its outputs to ground. However, when a
TTL output trying to maintain a LOW level is shorted to the 5-volt power supply, damage will
result. Although TTL inputs may be tied directly to ground, they should never be connected
directly to the +5-volt power supply. If by some misfortune the voltage level at some input terminal

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exceeds that at the power supply terminal, the chip will be destroyed. Use TTL outputs contain a
current limiting resistor in the connection to +5 volts.
An unconnected input to a gate is called a floating input, because it floats at the threshold voltage
for the device. A floating TTL input usually acts as a HIGH input. However, open inputs are
susceptible to noise which can be received by an input via the package leads, which act as antennae
for noise. Even a few hundred millivolts of negative noise voltage is sufficient to drive a floating
input to the LOW state. Therefore, it is advisable to tie all unused inputs of any gate (when the
gate has more inputs than required) to HIGH or LOW voltage. In addition, the outputs of unused
gates in an IC package should be forced HIGH by appropriate connection of the inputs. This
provides a convenient HIGH, reduces the power dissipation (ICCH < ICCL), and prevents
oscillation of the gate's outputs, which also causes increased power dissipation and current spiking.
The following points are important to consider when you are dealing with IC's as follow:
● Before IC is used, make sure its pins are not bent or broken and firmly pressed into the
sockets
● For TTL, an output trying to maintain a low level shorted to the +5V can cause damage.
● If a drive signal is applied to the input of a device that doesn't have power and ground
connected, the input structure can be damaged
● Never change connection with power on.
● Don't apply input signals exceeding the supply voltages. Turn off power before inserting
or removing a device from a circuit to avoid high transient voltages
2.3 Circuit Construction
A logic diagram is a diagram that shows all logic symbols, and all physical elements necessary to
describe the circuit. A connection diagram is a logic diagram that shows each pin number, input
and output load names, component values. The Schematic diagram of one logic function is the
implementation of the logic function in terms of electronic components. In order to build logic
circuits you should perform the following steps:
● Draw a connection diagram showing all pins to be used and how the unused pins are
terminated; the pin numbers can be obtained from data books. Insert your IC in IC socket.
● Connect the GND to the power supply ground and connect Vcc to the proper supply
voltage.
● Apply logic signals to the logic inputs and observe the output through the LEDs.

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All IC's should be mounted with the same orientation with the notch pointing upwards. You should
begin connecting your circuits by wiring power, ground, and all unused inputs of gates (for gates
having more inputs than needed) to an appropriate constant source. This makes the first
connections those that are least likely to change during debugging. Try to keep the wires as short
as possible. Try not to cross too many wires, so that tracing and removal of the wires will be easier.
Furthermore, a color code scheme will simplify debugging the circuit later. For example, all power
supply wires could be red, all ground wires black, etc.
When you have finished wiring, examine each pin of each IC to verify its connection. Check all
pins without any wires attached to see if they really should have no connection. Be sure to double-
check all power connections before applying power to the circuit. The 5-volt power supply
provided is short-circuit protected, so that shorting the power supply will merely shut it down until
the short circuit is removed. Thus, there is no need to worry about getting a shock from 5 volts.
However, you should be concerned about damaging ICs by improper connections!
The one sure way to irreparably damage an IC is to reverse power and ground. Most IC's have
their ground pin in the lower-left hand corner and power in the upper right-hand corner, when
viewed from the bottom. Thus, mounting an IC backwards will blow it out. But be alert, some IC's
have power and ground in nonstandard locations
2.4 Digital Lab Kit (IC Trainer)
The IC trainer is a kit for plugging in integrated circuits (IC's) and other components for building
circuits. It has built-in power supply, switches, socket strips, LED and seven-segment displays,
frequency generator and other special feature with the following capabilities:
a) Power Supply
A DC Voltage +5 V, max 2A and 0V (GND) is usually available. These are short circuit relay
and fuses protected so that shorting the supply will interrupt the relay off or in the worst-case
blow-out the fuse. There is no worry about getting a shock from 5 volts. However, you should
worry about blowing out ICs by reversing power and ground. Most pins have ground pin in
the lower left-hand corner and power in the upper right-hand corner, therefore plugging in an
IC upside down will blow it out.
b) Sockets

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 There are 4x14-Pin, 4x16-Pin, 1x24-Pin sockets for inserting IC's .Usually you insert the ICs
into the appropriate Sockets without supplying power and with the lever pointing upward.
Insert the ICs, press the lever in order to ensure the contact of all IC Pins. There are holes for
the connecting IC's pins using flexible wires.
c) Data Switches
To provide test circuit input, the trainer kit has 8 Switches, max.10 mA per output or 6 TTL
gates or 12 LS TTL gate. To use the data switch, insert in a wire in the corresponding hole of
the output switch and attach to the desired point. The switches are push and toggle buttons
with. The contacts of a typical switch will bounce several times over a period of milliseconds
after being operated however clean transition or bounce contacts can be eliminated by using
an SR flip flop. There are built-in debouncing circuit for Our switches in the kit.
d) Indicators
Display Module of 8 LEDs with the consumption of 4.5mA to indicate the High/Low logic
states of any circuit's node. To monitor the logic level of any point in circuit, connect a wire to
that hole corresponding to one of the indicator LED's .A logical 1 lights the lamp and a logical
0 extinguish it. There are 4 Seven Segment Displays with built-in BCD-to-Seven segment
Decoder. Each display takes a 4-input which can be displayed as a decimal or Hexa digit.
e) Frequency generator
The kit has built-in pulse generator of 0.5 Hz to 10 kHz with frequency divider for 4 outputs.

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 Figure 3: IC trainer

2.5 Digital Trouble –shooting instruments

a) Digital IC Tester.
Before you start building your projects using the TTL chips (described later in this manual),
it’s a good idea to make sure that these devices are in good condition, and that they operate
according to their logical and electrical specifications. Since a bad chip will generate errors in
your circuit and will make the debugging process more difficult. Because of the above, we
recommend that you use the IC tester shown in the above figure to test all your TTL chips.
Though the result of IC test is correct, the result is not guaranteed under the operation of circuit.

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 Digital IC tester

3. Procedure:

3.1 Logic Lab Kit

1. Study different parts of components of your Lab Kit. You may note that the main purpose of
this module is to enable user to acquire conveniently DC power supply, signal generator, eight
bits LED display for four digital 7 segment LED display, data switches and IC sockets.
2. Connect the logic lab mainframe to the appropriate AC power source and set it ON.
3. Wire one data switch output connector (SW1-SW8), to one of the LED input connectors.
Verify its HIGH and LOW operation by setting the data switch. You may note the LED
illuminated for HIGH level and extinguished for logic low level. Then repeat for other data
switches and indicators.
4. Wire +5V output connector to one of the LED input and the GND to other LED input and note
the illumination of light.
5. Wire the output connector of the pulse switch to one of the LED input. Press the corresponding
key and note its difference from the data switch.
6. Pickup one of the TTL IC, study its numbering identification and its pin numbering system.
Select e.g. the 7404 HEX invertor, insert it to the 14-Pin Socket, wire it as shown in the below
figure:

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 ● Connect pin # 7 to GND and pin # 14 to +5V.
● Connect the input of the first gate (pin#1) to the data switch and pin#2 (output) to one of
the LED indicators.
● Change the input to high and low and note the LED output.
Keep the connection of 7404 on the kit for next procedures
3.2 Digital IC Tester
1. Observe the different parts of the IC tester.
2. Power on IC tester, wait till SELF TEST completes (“SELF-TESTING ...” is shown on its
display).
3. Select IC type and number for test (if IC number is unknown press “TYPE” first, then press
“SEARCH”).
4. Put the device into Enter TEST (or SEARCH) key.
5. Result shown on its display.
- For Test message
a) “Test-OK”: device test OK
b) “BAD!” device test fail
- For Search message
a) “END” no suitable IC number
b) “FIND” first suitable IC number
c) “FIND END” only one suitable IC number.
6. the ZIF socket in the position shown in the below figure.

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Summary
In this experiment the capabilities of the logic lab mainframe have been explored. The data
switches will supply a logic HIGH or low level to any point in the circuit. The LED indicators
will give visual representation of a HIGH or LOW logic level. Power supply pin of IC is connected
to +5V while GND pin of IC is connected to ground. +V supply gives dc voltage supply. A signal
generator generates different variable waveforms with different frequencies.

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Questions
1. Identify the IC shown in the below figure

2. Where pin # 7 and pin # 14 of the most TTL 14 pin ICs are connected?

3. Name the number of the pin indicated by the arrow of the above Figure

4. To program a logic 1 or true to any point in a circuit, the data switch must be set to the
position
a) HIGH b) LOW
5. A 100 Hz and 100 kHz waveforms can be generated simultaneously in our signed generator
mainframe lab
a) TRUE b) FALSE
6. The TTL logic family is defined HIGH at any level between ...... V.
7. A 1V is considered in the TTL family.
a) HIGH b) LOW c) non valid
9. The logic probe will indicate a non-valid logic when voltage on the node tested is
a- Greater than 2V b- Between 0.8 and 2V c- Less than 0.8 d- b and d
11. A LED indicator can’t respond to pulses of 1 kHz output.
a) TRUE b) FALSE
12. The logic pulser injects a .... pulse into the circuit
a- 0.2 microsecond, b- 1 m sec., c- 10 sec., d- 1 min.
13. When using the logic probe and the logic pulser, a short to common will be indicated by.
● HIGH indication on the probe which will not pulse when the pulse’s trigger switch is depressed.
● HIGH indication on the probe which will pulse when the pulser’s trigger switch is depressed
● LOW indication on the probe which will not pulse when the pulser’s trigger switch is
depressed.
● LOW indication on the probe which will pulse when the pulser’s trigger switch is depressed.
● None of the above.

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 Experiment # 2: Introduction to Logic Gates
1. Objective:
The main objective of this experiment is to study the working of the basic gates (AND, OR,
NOT) and verified the basic concepts of multiple inputs and propagation delay. Other gates
such as NAND, NOR, XOR will be examined.
2. Components:
− IC trainer kit
− 7400 Quadruple 2 input NAND gates.
− 7402 Quadruple 2 input NOR gates
− 7408 Quadruple 2 input AND gates
− 7432 Quadruple 2 input OR gates
− 7404 Hex inverters
3. Background
Binary logic consists of binary variables and logical operations. Each variable can have only
distinct possible values: 1 and 0. The basic logical operations are NOT, AND and OR. These
operations are represented by symbols, each symbols have inputs and output variables. For
each combination of the values of input variables (e.g., X and Y), there is a value of output Z
specified by the definition of the logical operation, these definitions may be listed in a compact
form using truth tables. A truth table is a table of all possible combinations of the variables
showing the relation between the values that the input variable may take and the result of
operation.
• AND:
This operation is represented by a dot or by the absence of an operator, e.g. 𝑥 ∙ 𝑦 = 𝑧
or 𝑥𝑦 = 𝑧, it read "𝑥 AND 𝑦 is equal to 𝑧". This operation means that 𝑧 = 1 if and only
if 𝑥 = 1 and 𝑦 = 1; otherwise, 𝑧 = 0.
𝒙 𝒚 𝒛
0 0 0
0 1 0
1 0 0
1 1 1
Truth table of AND gate Graphical Symbol of AND gate

• OR:

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 This operation is represented by a plus sign e.g. 𝑥 + 𝑦 = 𝑧, it reads "x OR y is equal to
z". This operation means that 𝑧 = 1 if 𝑥 = 1 or 𝑦 = 1 or both equal 1. If both equal
𝑥 = 𝑦 = 0 then 𝑧 = 0.
𝒙 𝒚 𝒛
0 0 0
0 1 1
1 0 1
1 1 1
The truth table of OR gate Graphical symbol of OR gate

• NOT:
This operation is represented by a prime (sometimes by a bar), e.g., 𝑧 = 𝑥′, it reads "
𝑥 NOT equal to 𝑧", meaning that if 𝑥 = 1 then 𝑧 = 0 but if 𝑥 = 0 then 𝑧 = 1.
𝑥 𝑧
0 1
1 0
The truth table of NOT gate Graphical symbol of NOT gate
• XOR:
This operation is represented by plus inside circle e.g., 𝑥 ⊕ 𝑦 = 𝑧
𝒙 𝒚 𝒛
0 0 0
0 1 1
1 0 1
1 1 0
The truth table of XOR gate Graphical symbol of XOR gate

• NAND:
This is an AND gate with an inverted output.

• NOR:
This is an OR gate with an inverted output.

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4. Data Sheet Specification of IC’s

a. DC Electrical Specifications

Quantity Description min nom max units

1 𝑉𝑐𝑐 Supply voltage 4.75 5 5.25 V
2 𝑉𝐼𝐻 High-level input voltage 2 V
3 𝑉𝐼𝐿 Low-level input voltage 0.8 V
4 𝑉𝑂𝐻 𝑉𝑐𝑐 = 𝑚𝑖𝑛, 𝑉𝐼𝐿 = 0.8𝑉, 𝐼𝑂𝐻 = −0.4𝑚𝐴 2.4 3.4 V
5 𝑉𝑂𝐿 𝑉𝑐𝑐 = 𝑚𝑖𝑛, 𝑉𝐼𝐿 = 2.0𝑉, 𝐼𝑂𝐻 = 16.0𝑚𝐴 0.2 0.4 V
6 𝐼𝑂𝐻 High-level output current -0.4 mA
7 𝐼𝑂𝐿 Low-level output current 16 mA
8 𝐼𝐼𝐻 𝑉𝑐𝑐 = 𝑚𝑎𝑥, 𝑉𝐼 = 2.4𝑉 40 µA
9 𝐼𝐼𝐿 𝑉𝑐𝑐 = 𝑚𝑎𝑥, 𝑉𝐼 = 0.4𝑉 -1.6 mA

Datasheets give the "worst-case" values. The "Worst-case" is the manufacturer's guarantee
of performance. The worst-case can be a minimum or maximum depending on which
would be less desirable. Typical values are sometimes given. These should be used for
comparisons only. Worst-case values should be used when designing circuits

Figure 1: worst-case of logic gates.

• High-level output voltage (VOH): The minimum voltage on the output pin when
the input condition establishes logic HIGH at the output.
• Low-level output voltage (VOL): The maximum voltage on the output pin when
the input condition establishes logic LOW at the output.
• Low-level input voltage (VIL): The maximum voltage applied at the input that is
recognized as a legal LOW level.

22
 • High-level input voltage (VIH): The minimum voltage that needs to be applied at
the input to be recognized as a legal HIGH level.
• Output short circuit current (IOS): It is a troubleshooting technique to short a
high-level output to ground temporarily to verify that a circuit is working correctly
b. DC Noise Immunity (Noise Margin)

It is the ability to tolerate a certain amount of unwanted voltage fluctuation on its inputs
without changing its output state. In other words, the noise margin is the maximum noise
voltage added to the input signal of a digital circuit that doesn't cause an undesirable change
in the circuit output Noise margin is defined as the worst-case difference between the low-
level input and output voltage, or between the high-level input and output voltage. A large
noise margin is desirable.

Figure 2: DC noise margin of logic gates.

For example, the noise margin (NM) for 74HC00 and 74LS00 is given by:

74HC with VCC = 4.7V, VOH = 4.4V, VOL = 0.1 V, VIH = 3.15V, VIL = 0.9 V
VNH = VOH – VIH = 4.4 – 3.15 = 1.75 V
VNL = VIL – VOL = 0.9 – 0.1 = 0.8 V
✓ For a 74HC00, NM = smaller of {0.8 V, 1,75V} = 0.8V
✓ For a 74LS00, NM = 0.2V
c. DC Fan-out

The "fan-out" of a logic gate refers to the maximum number of devices it can drive before
its output is loaded down to the point where logic levels are unrecognizable, or where the
23
 logic levels begin to fall in the prohibited range. Since the current draw is different for
logic high and logic low levels, the fan out for each level must be calculated.

Figure 3: DC Fan-out.
The effect of loading an output with more than its rated fan-out is to increase its LOW-
state output voltage and decrease its HIGH-state output voltage. Because of TTL's DC
noise margins, a slightly overloaded circuit will still work in noise-free conditions, but of
course, the noise margins are reduced.
Example: How many SN74ALS06 inputs can be driven by a single SN74LS00 output?
Solution:
The SN74ALS06 is the input chip whose IIL is -0.1mA, and IIH is 0.02mA. The SN74LS00
is the output chip whose IOL is 8mA, and IOH is -0.4mA. Note that the direction of the
currents (their positive or negative sign) is ignored.
Fan-out Low = 8mA/.1mA = 80
Fan-out High = 0.4mA/0.02mA = 20
Because you don't want a current to exceed a specification that could damage an IC, choose
the lowest number. The number of SN74ALS06 inputs that can be driven by one
SN74LS00 is 20.
d. Switching Characteristics
• tPHL (propagation delay high to low): time delay between a specified level on
the input waveform and a specified level on the output waveform going low.
• tPLH (propagation delay low to low): time delay between a specified level on the
input waveform and a specified level on the output waveform going high.
• Propagation time delay (tD or tPD): the average delay of tPHL and tPLH

24
 Figure 4: Timing properties of logic gates.
e. Power Requirements

Real ICs consume energy to operate. This energy is not used for external useful work. It
is wasted as heat. Typically, we would like this to be as small as possible. Power
requirements vary the most between logic families. IC power consumption is measured as
Icc * Vcc with outputs open. A 5 W power source can supply 100 74LS ICs at 50 mW each.

f. Vcc Ranges

TTL ICs are typically powered from a 5.00 V, +/- 5% source. The specified range of
operation for a 74LS00 is 4.75 V to 5.25 V. Correct operation is not guaranteed outside
of this range. HC devices can operate with a large range of supply voltages. Typically:
2.0 V <Vcc < 6.0 V. Two, 3, or 4 AA batteries can supply several ICs. A phenomenon
associated with TTL devices is current spiking. When the output of a TTL device is
HIGH, a constant supply current ICCH is drawn from the power supply by the IC. When
the output is LOW, a constant supply current ICCL is drawn from the power supply. For
a 7400 NAND gate, ICCH = 4 mA and ICCL = 12 mA per IC. However, when the gate
output changes state, a short burst of current is drawn during the transition. The result is
current spikes (narrow pulses) in the power supply line. The largest spike occurs in the
LOW to HIGH transition. To prevent these current spikes from corrupting the power
supply and ground and thus appearing as noise, one decoupling capacitor (0.01 μF to 0.1
μF) for each five to ten IC packages are generally connected from the power to ground
near the IC pins. It was mentioned that the power supply should never be connected

25
 directly to gate inputs as the gate could be destroyed if the input voltage ever exceeded
the supply voltage to the IC: a virtually unlimited amount of current is then allowed to
flow backward through the IC. Current spiking can lead to just such a situation if power
were connected directly to a gate's inputs. Thus, another TTL gate should always be used
to provide a constant HIGH voltage if required.

5. Procedure:
PART-1: Operation of basic gates

A- The AND gate

Figure 5: And gate 7408.

1. Insert a 7408 quad ( four in one package ) 2-input AND gate into the breadboard, and
study its schematic diagram from its application sheet.
2. Wire as shown in Figure 5, connect pin 14 as usual to +5V and pin 7 to common (GND).
3. Set the data switches to the different combinations to verify its truth table and observe
its output.
4. Construct the two-level 3-input AND gate which implements the function F=(AB)C or
A.B.C using the 2-input AND gates. Study its truth table and verify its output logic
operation.

26
 B- The OR gate

Figure 6: OR gate 7432.

1. Insert a 7432 quad 2-input OR gate into the logic breadboard

2. Wire as shown in Figure 6, connect pin 14 as usual to +5V and pin 7 to common (GND).
3. Set the data switches to the different combinations to verify its truth table and observe its
output.
4. Construct the two-level 3-input OR gate which implements the function F=(A+B)+C or
A+B+C using the 2-input OR gates. Study its truth table and verify its output logic
operation.

C. The NOT gate

Figure 7: NOT gate 7404.

1. Insert the 7404 HEX inverter (six in one package) into the logic breadboard.
2. Connect it as shown in Figure 7. Set the input to high and low and observe its output (verify
its truth table).
3. Construct a series of NOT gates as shown in Figure 8, and connect the input of the first
gate to the switch and the output of the second gate (pin#4) to the LED. Verify its truth
table

27
 Figure 8: Series of NOT gates
D. NAND gate

Figure 9: NAND gate 7400.

1. Insert a 7400 quad 2-input NAND gate, connect one of its gates as shown in Figure 9, set
the data switches for its input, and verify its truth table (you may note that the NAND is
equivalent to a cascaded AND-NOT gate)
2. Connect the two inputs of or gate of 7400, shown in Figure 10 to one data switch, set the
data switch to different contributions, and verify the truth table. You may note that the two
connected inputs of the NAND are acting like an inverter.

Figure 10: NOT gate using NAND gate.

3. Construct the three-level, 3-input NAND gate which implements the function f= (ABC)’
as shown in Figure 11, and verify its truth table.

Figure 11: Three-input NAND gate.

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E- NOR gate

Figure 12: NOR gate 7402.

1. Insert a 7402 quad 2-input NOR gate into the logic breadboard
2. Follow the above procedure for the NOR gate according to the shown in Figure 12.
3. Keep one of the input wires floating and check the output. Is the floating input
considered low or high for the gate output?

F- XOR gate

Figure 13: XOR gate 7486.

1. Insert a 7486 quad 2-input XOR gate into the logic breadboard
2. Follow the above procedure for the NOR gate according to the shown in Figure 13.
3. Keep one of the input wires floating and check the output. Is the floating input
considered low or high? for the gate output

PART-2: Truth tables of logic circuits

Connect the circuits shown in Figure 14 and write the corresponding truth tables

29
Figure 14: Logic circuit.

30
Questions
1. How many 2-input AND gates are required to construct a 5-input AND gate?

a) 2 b) 3 c) 5 d) 4 e) none

2. Which is better for a 4-input AND gate? The connection of A or B, F why?

a) A b) B

3. If only 2-input OR gates are available, what is the minimum gate level possible to
implement an 8-input OR gate?

a) 2 b) 3 c) 4 d) 6 e) 7

4. What is the propagation delay for Cout of the following circuit?

a) 30 ns b) 45 ns c) 35 ns d) 10 ns e) 20 ns

5. If the fan-out of gate A is 10, can we connect the 16 input gate together directly to A
(without using the two-series inverter).

a) True b) false c) undetermined

6. If a three NAND gate had two inputs connected to +5Volts and the third input to A.
The output would be

a) A b) A c) high d) low

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 7. How many output states do a 3-input OR or AND or NOT gate have?

a) 1 b) 2 c) 3 d) 4 e) not determined

8. If one input to a NOR gate is high and the other inputs are unknown (may be high or
low), the output is

a) Low b) High c) Undetermined d) illegal combination

9. Construct a 3-input NOR circuit using only 2-input NOR gates?

10. Write a truth table for each circuit.

Design Problem:

11. A burglar alarm for a car has a normally low switch on each of the four doors. If any
door is opened the output of that switch goes HIGH. The alarm is set off with an active-
LOW output signal. What type of gate will provide this logic? Support your answer
with an explanation.

12. Write the equation of the alarm of a car that is set when you are in the car and it’s
running and you didn’t put the belt assuming the following variables:

X=1 when you are in the car

Y=1 when the car is off
Z=1 when you put the belt
F=1 when alarm is on

32
 Experiment # 3: Boolean Functions
1. Objective:
• To emphasize the basic operations and laws of Boolean algebra, applying these laws to
manipulate algebraic expressions.
• To Implement the Boolean functions in terms of truth tables or the desired behavior of a
logic network will be stressed.

2. Components:
− IC trainer kit
− 7400 Quadruple 2 input NAND gates
− 7402 Quadruple 2 input NOR gates
3. Background
The basic mathematics needed for the study of logic design of digital systems is Boolean
algebra. Boolean expressions are formed by the application of the basic operations (AND,
OR, NOT) to one or more variables or constants. Each expression corresponds directly to a
network of logic gates. Each appearance of a variable or its complement in an expression will
be referred to as literal. When an expression is realized using logic gates, each literal in the
expression corresponds to a gate input.
A truth table specifies the values of a Boolean expression for every possible combination of
values of the variables in the expression. In other words, a Boolean function may be
represented in a truth table. To represent a function in a truth table we need a list of 2n
combinations of 1's and 0's of the n binary variables and a column showing the combinations
for which the function is equal to 1 or 0. It is possible to find two algebraic expressions that
specify the same function e.g., they have, in their truth tables, the same values for every
possible combination of the variables. These expressions can be deducted from each other by
following the postulates and theorems of Boolean algebra. The application of these rules is
applied mostly to the problem of finding simpler expressions for the same functions.
A Boolean function can be minimized by algebraic manipulations employing postulates, basic
theorems, and other manipulation methods. Table (1) lists six theorems of Boolean algebra and
four of its postulates. You may note the table is divided into two parts (a and b). One part is
obtained from each other if the binary operators and the identity elements (0 and 1) are
interchanged. This important property of Boolean algebra is called the duality principle. It
states that every algebraic expression deducible from the postulate of Boolean algebra remains

33
 valid if the operators and identity elements are interchanged e.g., if the dual of an algebraic
expression is required, we simply interchange OR and AND operators and replace 1's and 0's
and 0's by 1's.
Table 1: Postulates and Theorems of Boolean Algebra

The complement of a function F may be derived algebraically through DeMorgan's Theorem which
states that the complement of a function is obtained by interchanging AND and OR operators and
complementing each literal.
A Boolean function may be expressed algebraically from a given truth table by forming a minterm
for each combination of the variables which produces a 1 in the function and then taking the OR
of all those terms. A minterm for each combination is formed by Anded the input variable (being
primed or unprimed) combinations such that its output produce 1.
The other method for expressing the Boolean functions from a given truth table is by forming
maxterms for each combination of the variables which produce a 0 in the function and then taking
the And of all these terms. A maxterm for each combination is formed by ORed the input variable
combination (primed or unprimed) in such that its output produces 0.
Boolean functions expressed as a sum of minterms or product of maxterms are said to be in
canonical form, (note that the term sum denotes the ORing and the product denotes the Anded
operation). Another way to express the Boolean function is in standard form. In this configuration,
the terms that form the function may contain one, two, or any number of literals. There are two
types of standard forms, the sum of products and the product of sums.

34
4. Procedure:
Consider the Boolean function F. The function has four variables x, y, z, and t and it's written as
the sum of four terms.
F = x'.y.t + x.y.t + y.z' + y'z

1. Determine the truth table of the function (Table 2).

Table 2: Truth table of the Boolean function F

2. Simplify F by using algebraic manipulation and express it as a three-variable function.

35
3. Complete the new truth table for F below (Table 3).
Table 3: Truth table of the new Boolean function F

4. Now, suppose that the function F has the following expression:

F = y.t + y.z' + y'.z
a) Express the Boolean function F with two-Inputs NAND gates

36
b) Draw the logic diagram from the expression obtained in (a)

c) Construct the circuit drawn above using 74LS00 IC (as much as you need) on the IC
trainer. Experimentally determine the truth table of the constructed circuit. Record
your results below in Table 4.
Table 4: Experimental Truth table of F (using NAND gates)

d) Express the Boolean function F with two-Inputs NOR gates

37
e) Draw the logic diagram from the expression obtained in (d)

f) Construct the circuit drawn above using 74LS02 IC (as much as you need) on the IC
trainer. Experimentally determine the truth table of the constructed circuit. Record
your results below in Table 5.
Table 5: Experimental Truth table of F (using NOR gates)

g) Compare between all results of F obtained in Table 3, Table 4, and Table 5.

38
Questions:

Q.1 By DeMorgan's Theorem the function ̅̅̅̅̅̅̅̅

𝐹=𝐴 + 𝐵 is equal to

a. 𝐴̅ 𝐵̅ b. AB c. 𝐴̅ + 𝐵̅ d. A+B

Q.2 Given the following logic circuit, the output by DeMorgan's Theorem would be

̅̅̅̅
a. 𝐴𝐵 b. AB c. 𝐴̅ + 𝐵̅ d. A+B

Q.3 Are the following logic circuits equivalent?

a. Yes b. No.

Q.4 The duality of 𝑓 = 𝑥𝑦 + 𝑥𝑦

̅̅̅ is

a. (𝑥̅ + 𝑦̅)(𝑥̅ + 𝑦) b. (𝑥 + 𝑦) ∙ (𝑥̅ + 𝑦) c. (𝑥 + 𝑦) ∙ ̅̅̅̅̅̅̅̅̅̅

(𝑥 + 𝑦) d. none of them

Q.5 The Boolean function of the following logic circuit is:

a. (𝐴 ∙ 𝐵) + 𝐶 b. 𝐴̅𝐵̅ + 𝐶 c. 𝐴̅𝐵̅ + 𝐶̅ d. none of them

Q.6 What is the minterm m5 for a function of three input variables (x,y,z) (consider z is
the least significant variable)?

a. 𝑥𝑦̅𝑧 b. 𝑥̅ 𝑦̅𝑧 c. 𝑥𝑦𝑧̅ d. 𝑥̅ + 𝑦 + 𝑧̅

Q.7 Following Q.6 what is the maxterm M4?

a. 𝑥̅ + 𝑦 + 𝑧 b. 𝑥 + 𝑦̅ + 𝑧 c. 𝑥̅ + 𝑦̅ + 𝑧 d. 𝑥̅ 𝑦𝑧

Q.8 If a function F(x,y,z) is equal 1 only for m0 and m3 we can express F as

39
 a. F = m0+ m3 b. F = M1.M2 c. F = M1+M2+M3 d. both a and b

Q.9 The following two logic circuits are equivalent

a. Yes b. No

Q.10 The simplification of the following expression: 𝐹 = 𝑥(𝑥 + 𝑦) is

a. 𝑥𝑦 b. 𝑥 c. 𝑥 + 𝑦 d. none of them

Q.11 If a function of two variables has only M0 and M1 its complement can be expressed as
a. 𝐹̅ = 𝑚2 + 𝑚3 b. 𝐹̅ = 𝑀2 + 𝑀3 c. 𝐹̅ = 𝑀2 ∙ 𝑀3 d. 𝐹̅ = 𝑀0 + 𝑀1

Q.12 Following Q.11 the function F can be expressed as

a. 𝑀2 ∙ 𝑀3 b. 𝑚0 ∙ 𝑚1 c. 𝑀2 + 𝑀3 d. 𝑀0 ∙ 𝑀1

Q.13 The Boolean function F for the following circuit is:

a. A+B b. (A.B) c. NOR (A+B) d. NAND (AB)

Q.14 Simplify the following Boolean functions

F (A, B, C, D) = m (0, 1, 4, 5, 8, 9, 10, 12, 13)

Q.15 Derive a truth table for the following Boolean Functions. obtain the simplified function for
F.

𝐹 = 𝐴’𝐷 + 𝐵’𝐷 + 𝐵𝐶 + 𝐴𝐵’𝐷.

Q.17 What will be the truth table for the following circuit in terms of W, X, Y
And what is the function of F?

40
Q.18 Express F as a sum of minterm’s, F (x, y, z) =∑ (…) in the following equation

𝐹 = 𝑥 + (𝑦𝑧) + (𝑥 + 𝑦)

Design Problem

Q.18 Four chairs A, B, C, and D are placed in a row. Each chair may be occupied (“l”) or
empty (“0”). A Boolean Function F is “l” if and only if there are two or more adjacent
chairs that are empty.

1. Give the truth table defining the Boolean Function F

2. Express F as a minterm expansion (standard sum of product) or What values of input F
becomes “1”.
3. Express F as a maxterm expansion (standard product of sum) or What Values F becomes
“0’.
4. Using postulates and theorems of Boolean algebra, simplify the minterm
expansion of F

Q.19 Fill the truth table defining the Boolean Function Y such that the output will be 1 when
there is a risk for feeding or at critical cases

1. Express Y as Sum of minterms

2. Express Y as a Product of maxterms
Simplify the Boolean equation for Y in part 1

41
 Experiment # 4: Half and Full Adder/Subtractor
1. Objectives:
The main objectives of this experiment are:
• To construct and test various adder circuits.
• To construct and test various subtractor circuits.
• To construct and test a magnitude comparator circuit.
2. Components
• IC trainer Kit
• IC type 7486 quad 2-input XOR gates
• IC type 7408 quad 2-input AND gates
• IC type 7404 HEX inverter
• IC type 7483 4-bit binary adder
• IC type 7485 4-bit magnitude comparator
3. Background:
The basic binary adder is called a half adder that adds two single-bit operands 𝑥 and 𝑦
producing the sum (s) and the carry out (Cout).

Figure 1: Half Adder.

42
To add operands with more than one bit, we must provide for carries between bit positions.
The basic building block for this operation is called a full adder. Besides the addend-bit inputs
X, Y, a full adder has a carry-bit input, Cin or Z. We can write its equations:

𝑆 = 𝑋⨁𝑌⨁𝑍
𝐶𝑜𝑢𝑡 = 𝑍 ∙ (𝑋 + 𝑌) + 𝑋𝑌

Figure 2: Full adder, symbol circuit, and truth table.

Two binary numbers, each with 𝑛 bits, can be added using an adder that consists of a cascade
of 𝑛 full adder stages, each of which handles one bit. Figure 3 shows the circuit for a 4-bit
ripple adder. The carry input to the least significant bit (Cin) is normally set to 0, and the carry
output of each full adder is connected to the carry input of the next most significant full adder.
A ripple adder is slow since in the worst case a carry must propagate from the least significant
full adder to the most significant one. A faster adder can be built by obtaining each sum outputs
Si with just two-level logic. This is accomplished by writing an equation for Si in terms of Xo-
Xi, Yo-Yi, and Co, "multiplying" or "adding out" to obtain a sum of product or product of sums.
Unfortunately, beyond S2, the resulting expressions have too many terms. Nevertheless, it is

43
possible to build adders with just a few levels of delay using a more reasonable number of
gates such as carry look-ahead adders, which are beyond the scope of this experiment.

Figure 3: 4-bit adder.

A full subtractor handles one bit of the binary subtraction algorithm, having input bits X
(minuend), Y (subtractend) and Z (borrow in), and output bits , D (difference) and B (borrow
out) .We can write the logic equations:
𝐷 = 𝑋⨁𝑌⨁𝑍
𝐶𝑜𝑢𝑡 = 𝑋̅𝑌 + 𝑋̅𝑍 + 𝑌𝑍
These equations are very similar for a full adder. Compared with the equations for a full adder
the above equations tell us that we can build a full subtractor from a full adder.

7483 IC
IC type 7483 is a 4-bit binary adder with fast carry. The pin assignment is shown in Figure 4.
In this Figure, the two 4-bit input binary numbers are A1 through A4 and B1 through B4. The
4-bit sum is obtained from S1 through S4. Ci is the input carry and Co the output carry.

44
 Figure 4: 7483 4-bit adder.

The 74LS83 can be used as a 4-bit ripple subtractor as well as a 4-bit ripple adder. It is known that
the subtraction of two binary numbers can be done by taking the 2's complement of the subtractend
and adding it to the minuend. The 2's complement can be obtained by adding 1 to the 1's
complement of the number. To perform 𝐴 − 𝐵, we complement the four bits of B, add them to the
four bits of A, and add 1 through the input carry. This is done as shown in the following figure.

Figure 5: 7483 4-bit adder/subtractor.

45
The four XOR gates complement the bits of B when the mode select M=1 (because X+1 = X)
and leave the bits of B unchanged when M=0 (because X+0 = X) Thus when the mode select M
is equal 1, the input carry Co is equal to 1 and the sum output is A Plus the 2's complement of B.
When M is equal to 0, the input carry is equal to 0 and the sum generates A+B. So this circuit
can be called adder-subtractor circuit.
An arithmetic and logic unit is a combinational circuit that can perform any number of different
arithmetic and logical operations on a pair of n-bit operands. Typical medium-scale integration
(MSI) arithmetic logic units (ALUs) have 4-bit operands and three to five function select inputs
allowing up to 32 different functions to be performed.

Magnitude Comparator: IC 7485

The IC 7485 is a 4-bit magnitude comparator. It compares two 4-Bit binary numbers (labeled as
A&B) generates an output of 1 at one of three outputs labeled A > B, A < B, A = B. Three inputs
are available for cascading comparators as shown in Figure 6.

Figure 6: 4-bit magnitude comparator.

46
4. Procedure:
1. Construct and test the full adder circuit.
Inputs Outputs
A B Cin S Cout
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

2. Using the 74LS83 Adder realize a 4-bit full adder and complete the table below for the given

numbers A and B.

3. Connect the adder-subtractor circuit as shown in Figure 5. Perform the following operations
and record the values of the output sum and the output carry Co.

47
 • Show that Co =1 when the sum exceeds 15.
• Comment on sum and Co for the subtraction operations when A > B and A < B.

4. Use IC7485 to compare the following two 4-bit numbers A and B. Record the outputs in table
for results.
Outputs
A B
A>B A=B A<B
1101 1101
1100 0011
0011 1100

48
Questions:
Q.1 A half adder considers the possibility of a carry from the previous addition:
(a) True (b) False

Q.2 A full adder combines two half adders and ORs their...... outputs.
(a) Sum (b) Carry (c) none of them

Q.3 The half subtractor is used in the subtraction circuit:

(a) for the least significant bit (b) for the most significant bit
(c) whenever borrow is present (d) none of them

Q.4 The full subtractor ORs the.............outputs of the two half subtractors:
(a) difference (b) borrow

Q.5 Ripple adders is adder consisting of a cascaded a full adder stages:

(a) True (b) False

Q.6 Which is faster, ripple adder or a carry look ahead adders:

(a) ripple adders (b) carry look ahead adders

Q.7 The 74LS83 is a..........binary adder:

(a) 4-bit (b) full bit
(c) n-bit (d) none of them

Q.8 What is the operation of Adder_Subtractor Circuit when M=1?

(a) A – B (b) B-A (c) A+B (d) none of them

Q.9 The data output of the Adder_Subtractor circuit if A = 8, B = 5, M = 0:

(a) blank (b) “13” (c) 3 (d) over 14 (e) none of them

Q.10 The data output of the adder - subtractor circuit if A = 7, B = 10, M = 1 would be:
(a) 13 (b) “17” (c) 3 (d) over (e) none of them

Q.11 The output of the adder-subtractor circuit if A = 10, B = 7, M = 1 would be:

(a) over (b) 17 (c) 2 (d) 3 (e) none of them

Q.12 The output carry of the adder-subtractor circuit for A = 12, B = 10, M = 1 would be:
(a) 0 (b) 1 (c) 2 (d) 22 (d) none of them

Q.13 Draw the circuit diagram of a two-bit comparator circuit with two outputs A=B and A>B.

49
Q.14 what is the output of S and C in term of A.

Q.15 What you would change in the Adder_Subtractor circuit so the results of sum is the
operation of (B – A)?

Q.16 For the magnitude comparator IC 7483. What type of numbers A, B are considered for
comparison?

(a) Signed (b) Unsigned (c) Floating (d) none of them

Design Problems:
Q.17 A magnitude comparator can be constructed by using a subtractor as in the following
Figure and an additional combinational circuit. This is done with a combinational circuit
which has

5 inputs S1, S2, S3, S4, and Co, and three outputs X, Y, Z see below figure
X = 1 if A = B Where S = 0000
Y = 1 if A < B Where Co = 0
Z = 1 if A > B Where Co = 1 S ≠ 0000

Design and construct this logic circuit with minimum number of gates.

50
Q.18 You may note for the Adder/subtractor circuit that Co is used as a sign indicator for the
number when M=1 (subtract) . The number is positive when Co=1 and the number is
negative when Co=0. The number need to be in 2’s complement to get the correct reading
of the negative number. Modify your Adder-subtractor circuit so that your circuit would
complement the number when the result is negative.

Q.17 Design the comparator circuit of two-bits signed numbers A, B with two outputs A=B
and A>B. Show how your design can be modified for the comparison of 3-bits numbers.

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 Experiment # 5: Decoder-Encoder
1. Objectives:
The objectives of this experiment are:
• To be familiar with Decoders and Encoders.
• To know how to implement functions using Decoders.
2. Components:
✓ Digital Lab trainer
✓ Wires
✓ IC chip – 74138
✓ 7432 Quadruple 2 input OR gates
✓ 7404 Hex inverters

3. Background
A decoder is a combinational circuit that converts binary data from 𝑛 input lines to a maximum of
2n distinct output lines for each decoded data. If the n-bit coded data has unused combinations, the
decoder may have fewer than 2n outputs. As an example, consider the three-to-eight-line shown in
Figure 1. The three inputs are decoded into eight outputs, each representing one of the minterms
of the three input variables. The three inverters provide the complement of the inputs, and each
one of the eight AND gates generates one of the minterms. A particular application of this decoder
is binary-to-octal conversion. The input variables represent a binary number, and the outputs
represent the eight digits of a number in the octal number system.

52
 Figure 1: Three-to-eight-line decoder.
The operation of the decoder may be clarified by the truth table listed in Table 1.
Table 1: Truth Table of a Three-to-Eight-Line Decoder.

Furthermore, decoders include one or more enable inputs to control the circuit operation. A block
diagram of a two-to-four-line decoder with an enable input is shown in Figure 2. As indicated by
the truth table (Table 2), only one output can be equal to 1 at any given time; all other outputs are
equal to 0.

Figure 2: block diagram of a two-to-four-line decoder.

Table 2: Truth table of 2 to 4 decoder with enable.
E A1 A0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

53
Moreover, decoders with enable inputs can be connected together to form a larger decoder circuit.
Figure 3 shows two 3-to-8-line decoders with enable inputs connected to form a 4-to-16-line
decoder.

Figure 3: 4 × 16 decoder constructed with two 3 × 8 decoders.

A decoder provides the 2n minterms of n input variables. Each asserted output of the decoder is
associated with a unique pattern of input bits. Since any Boolean function can be expressed in
sum-of-minterms form, a decoder that generates the minterms of the function, together with an
external OR gate that forms their logical sum, provides a hardware implementation of the function.
In this way, any combinational circuit with n inputs and m outputs can be implemented with an n-
to-2n-line decoder and 𝑚 OR gates. For example, a full adder can be implemented using a 3-to-8-
line decoder as shown in Figure 4.

Figure 4: Implementation of a full adder with a decoder.

Encoders
An encoder is a device, circuit, transducer, software program, algorithm or person that converts
information from one format or code to another, for the purposes of standardization, speed,
secrecy, security, or saving space by shrinking size. Encoder is a digital circuit that performs the

54
inverse operation of a decoder, generates a unique binary code from several input lines. Generally,
encoders produce 2-bit, 3-bit or 4-bit code. n bit encoder has 2n inputs.
A priority encoder is an encoder circuit that includes the priority function. The operation of the
priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having
the highest priority will take precedence. The truth table of a four-input priority encoder is given
in Table 3. Moreover, the priority encoder is implemented as shown in Figure 5 according to the
following Boolean functions:

Figure 5: Four-input priority encoder.

74LS138 – 3 to 8 Line Decoder IC

74LS138 is a member from ‘74xx’family of TTL logic gates. The chip is designed for applications
and comes with 3 inputs to 8 output setup. The pin configuration of this IC type is shown in Figure
6. This IC type comes with complemented output.

55
 Figure 6: Pin configuration of 74LS138 3-to-8-line decoder IC type.
4. Procedure
4.1 Implantation of Full adder using 74LS138
• Connect the 74LC138 IC and verify its function.
Input Output
𝐸̅1 𝐸̅2 𝐸3 𝐴 𝐵 𝐶 𝑌0 𝑌1 𝑌2 𝑌3 𝑌4 𝑌5 𝑌6 𝑌7
1 X X X X X
X 1 X X X X
X X 0 X X X
0 0 1 0 0 0
0 0 1 0 0 1
0 0 1 0 1 0
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 0 1
0 0 1 1 1 0
0 0 1 1 1 1

56
 • Implement the full adder using 3-to-8-line decoder as shown in Figure 4 and fill Table
3.
Table 3
x y Cin Cout S
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

4.2 Construct 4-to-16-line decoder using

• Construct the 4 × 16 decoder using two 3 × 8 decoders as shown in Figure 3. Record
your results

57
4.3 Construct the four-input priority encoder
• Construct the four-input priority encoder as shown in Figure 5 and fill the table below.
Input Output

𝑫𝟎 𝑫𝟏 𝑫𝟐 𝑫𝟑 𝒙 𝒚 𝑽

0 0 0 0

1 0 0 0

X 1 0 0

X X 1 0

X X X 1

58
 Experiment # 6: Multiplexer-Demultiplexer

1. Objectives:
• Design, build, and test a variety of Decoders, Encoders.
• Demonstrate the operations and applications of Decoders, Encoders.
• Implement logic functions using Decoders.
2. Components:
• IC trainer kit
• 7408 Quadruple 2 input AND gates
• 7432 Quadruple 2 input OR gates
• 7404 Hex inverters
• 74151 IC chip 3-to-1 multiplexer

3. Background
A multiplexer is a device that has several inputs and a single output, and the value of the output
will be the value of one of the inputs, the selection of which will be determined by certain
select lines. A multiplexer is also commonly referred to as a MUX. The two lines to one line
data multiplexer shown in Figure 1, often known as the 2 × 1 data multiplexer, is the simplest
form of multiplexer.
𝑌 = 𝑆̅𝐼0 + 𝑆𝐼1

Figure 1: 2-to-1 multiplexer, logic and block diagrams.

A multiplexer of 2𝑛 inputs has 𝑛 select lines that are used to select which input line to send to
the output. A 2n-to-1 (2𝑛 × 1) multiplexer sends one of 2n input lines to a single output line.
Multiplexers can also be used effectively in the implementation of Boolean functions. For a
Boolean function of 𝑛 variables, the following steps are used:
1. Select the type of multiplexer (2n-1-to-1).
2. Select (𝑛 − 1) as selection line.

59
 3. The other input connects as input.
For example, the function 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∑(1, 3, 4, 11, 12, 13, 14, 15) can be implemented
using multiplexer.
Here 𝑛 = 4, then
1. The type of Mux [23-to-1] == 8-to-1 mux
2. Select (3) as selection line ➔ For example (A, B, and C)
3. The other input connects as input. ➔ (D)

Figure 2: Implementing a Boolean function 𝐹 with a multiplexer

• The 8-to-1 Multiplexer (74151)
The 74151 is a multiplexer (mux) that selects binary information from one of 8
input lines and directs it to a single output line. The circuit has complemented
output. The selection of a particular input line is controlled by three selection lines.
A strobe control S acts as an enable signal. The block diagram of the 74151 is
shown in Figure 3.

60
 Figure 3: Block diagram of IC type 74151.
Table 1: Truth table of 8-to-1 mux.

4. Procedure
D.1. Referring to Figure 3, complete Table 2.
Table 2: Pins number and their designation for the 74151 IC

D.2. Write the Boolean expression of the output by using only data inputs and select inputs.

61
 ………………………………………………………………………………………………

………………………………………………………………………………………………

………………………………………………………………………………………………

………………………………………………………………………………………………

………………………………………………………………………………………………

………………………………………………………………………………………………

………………………………………………………………………………………………

………………………………………………………………………………………………

……………………

D.3. Let F1 = xyz + x'yz' + x'y'z' + xyz',

D.3.1 Draw the circuit diagram of F1 in Figure 3 and fill Table 2.
Step 1: Determine the state of each data input and the state of each select input.
…………………………………………………………………………………………………

…………………………………………………………………………………………………

…………………………………………………………………………………………………

…………………………………………………………………………………………………

……………………

…………………………………………………………………………………………………

…………………………………………………………………………………………………

…………………………………………………………………………………………………

…………………………………………………………………………………………………

……………………

62
 Step2: Draw the circuit and fill the table.

Figure 4: Implementing the Boolean function F1 with a multiplexer.

Table 3: Truth table of the function F1 .

D.4. Let F2 = x'yzt + x'yz't' + x'y'zt + x'y'z't',

D.4.1 Draw the circuit diagram of F2 in Figure 5 and fill the Table (Table 4).
Step 1: Determine the state of each data input and the state of each select input.
………………………………………………………………………………………………………

………………………………………………………………………………………………………

………………………………………………………………………………………………………

………………………………………………………………………………………………………

………………………………………………………………………………………………………

………………………………………………………………………………………………………

………………………………………………………………………………………………………

63
Step 2: Draw the circuit and fill the table.

Figure 5: Implementing the Boolean function F2 with a multiplexer.

Table 4: Truth table of the function F2.

64
D.5 Practical implementation of F1 and F2:
Step 1: Place the 74151 on the IC trainer kit.
Step 2: Connect Pin8 (GND) to 0V and Pin16 (Vcc) to +5V.
Step 3: Implementation of F1:
✓ According to the circuit obtained in Figure 4, implement the function F1.
✓ Test the circuit and fill the Table (Table 5).
Table 5

Step 4: Implementation of F2:

✓ According to the circuit obtained in Figure 5, implement the function F2.
✓ Test the circuit and fill the Table (Table 6).
Table 6

65
B. The Demultiplex (De-Mux)
The logic symbol of a demultiplexer is shown in Figure 5.

Figure 5: Logic symbole of De-Mux.

B-1: Choice the correct answer.
✓ The demultiplexer of Figure 5 is a:

B-2: Express the Boolean function of each output

Y0=…………………

Y1=…………………

Y2=…………………

Y3=…………………

66
B-3: Complete the following truth table

67
Appendix:

68
69
70
 Experiment # 7: D and JK Flip-Flops
1. Objectives:
The objectives of this experiment are:
• Introduces the basic building of Flip-Flops.
• Operations and characteristics of Flip-Flops
• Conversions of Flip-Flops
• Investigates the operation of D Flip-Flop using IC 7474.
• Investigates the operation of JK Flip-Flop using IC 7476.
2. Equipment Components needed:
- 7474 IC (Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear).
- 7476 IC (Dual Master-slave JK Flip-Flops With Preset And Clear).
- 7404 IC (Six Not gates).
- IC trainer Kit
3. Background:
In the last experiment, the logic circuits introduced were combinational. These circuits do
not have memory cells and their output depends only upon the current value of the input.
Memory cells are very important in digital systems. Their usage in digital circuits provides
temporary storage of the outputs produced by a combinational logic circuit for use at a later
time in the operation of a digital system. Logic circuits that incorporate memory cells are
called sequential logic circuits; their output depends not only upon the present value of the
input but also upon the previous values. Sequential logic circuits often require a timing
generator (a clock) for their operation. The latch (flip-flop) is a basic bi-stable memory
element widely used in sequential logic circuits. Usually there are two outputs, Q and its
complementary value. They are called state variables. State variables which change only
between logic 1 and logic 0 are called binary state variables. There are various types of
latches. Some of the most widely used latches are listed below.

3.1 S-R Flip-Flop:

An S-R latch consists of two cross-coupled NOR gates and possibly two inverters, as
shown in Figure 1. An S-R flip-flop can also be design using cross-coupled NAND gates
as shown in the Figure. Table shows the truth tables for both cases. Note that a negative
logic signal such as R is considered asserted (logical 1) when low. A clocked S-R flip-flop
shown in Figure 2 has an additional clock input so that the S and R inputs are active only
when the clock is high. When the clock goes low, the state of flip-flop is latched and cannot

71
 change until the clock goes high again. Therefore, the clocked S-R flip-flop is also called
“enabled” S-R flip-flop.

Figure 1: S-R flip Flop

Figure 2: Clocked S-R Flip-Flop.

3.2 D-Latch and Edge Triggered Flip-Flop:

A D-latch flip-flop combines the S and R inputs of an S-R latch into one input by adding
an inverter, as indicated in the below figure. When the clock is high, the output follows the
D input, and when the clock goes low, the state is latched

Figure 3: D-Latch Flip-Flop.

An edge-triggered D flip-flop combines two D latches, as shown in below figure. The input
latch is called the master and follows the input while the clock is low. When the clock goes
high, the master is latched and its output is transferred to the second latch, called the slave.

72
 The slave output is seen by the user. Hence the edge-triggered D flip-flop senses the input
data present at the rising edge of the clock and provides a corresponding output. The output
can only change at the rising clock edge. The small triangle on the “CLK” terminal on the
symbol represents its edge-triggering.

Figure 4: Edge triggered D Flip-Flop.

3.3 JK Flip–Flops
A JK flip-flop has two inputs, labeled J and K. The J input corresponds to the SET input in
an SR flip-flop, and the K input corresponds to the RESET input. The difference between
a JK flip-flop and an SR flip-flop is that in a JK flip-flop, both inputs can be HIGH. When
both the J and K inputs are HIGH, the Q output is toggled, which means that the output
alternates between HIGH and LOW. Additionally, the timing diagram for a typical JK FF
is shown in Figure 6.

Figure 5: J-K Flip-Flop.

73
 Figure 6: Timing diagram of JK Flip-Flop.

3.4 T Flip-Flop
If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is
strobed. If the T input is low, the flip-flop holds the previous value. This behavior is
described by the characteristic equation:

Figure 7: T Flip-Flop and its timing diagram.

74
3.5 Summary of Flip-Flops
There are basically four main types of flip-flops: SR, D, JK, and T. The major differences
in these flip-flop types are in the number of inputs they have and how they change state.
Each type can have different variations such as active high or low inputs, whether they
change state at the rising or falling edge of the clock signal, and whether they have
asynchronous inputs or not. The flip-flops can be described fully and uniquely by its logic
symbol, characteristic table, characteristic equation, state diagram, or excitation table, and
are summarized in Table 1.
Table 1: Flip-flop types.

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3.6 Conversion of Flip Flops
3.6.1 Construction of D Flip-Flop using JK Flip-Flop

3.6.2 Construction of T Flip-Flop using JK Flip-Flop

3.6.2 Construction of JK Flip-Flop using D Flip-Flop

76
4. Procedure:

A. Construct the D-type latch shown below and analyze the operation of the circuit.
Complete the truth-table.

CLK D Q(t+1)
0 X
1 0
1 1
B. The 7476 is a dual JK master-slave flip-flops with preset and clear inputs. The
function given in the following table defines the operation of the flip-flop.

A. Look at the data sheet for the 7476 and Insert the chip into the breadboard on your trainer.
Connect power and ground to pins 5 and 13, respectively. Connect asynchronous inputs
preset and clear to high state, inputs J, K to switches, and don't forget the clock input.
Observe your circuit carefully and verify the operation of the JK flip flop. Fill the table
and the draw the timing diagram.

77
B. Connect the 7476 for the SET mode by connecting J = 1, K = 0. With CLOCK (CP) = 0;
test the effect of PRE, CLR by putting a 0 on each, one at a time. Put CLR = 0, then pulse
the clock (CP) by putting a HIGH then a LOW, on the clock. Does the CLR input override
J input?
C. Convert your JK FF to T FF and D FF and check its characteristic and excitation table

78
Experiment # 8: Design of Sequential Circuits and Sequence Recognizer

1. Objective:

● Design and implementation of synchronous sequential circuits using SSI IC's

● Construction of state diagrams and state tables and the design techniques for counters and
sequence detector circuits

2. Components:
✓ IC trainer
✓ IC 7476
✓ IC 7474
✓ IC 7408
✓ IC 7432
3. Background:

Sequential circuits differ from combinatorial circuits in that the outputs of the circuit depend not
only on the present state of the inputs but also on the past history of the inputs. Thus, a sequential
circuit has memory. Memory is provided for each bit needed to define a state by using a bit storage
device such as a flip-flop. Any type of flip-flop is suitable, but with some designs the J-K type
may be better in the sense that the combinatorial logic required for the feedback path is usually
(but not always) minimized by this choice. The combinatorial part of the circuit can be
implemented using gates, MUXs, Decoder's, ROMs or any method that is capable of providing the
necessary feedback logic

The design of the circuit consists of choosing the flip-flops and then finding a combinational gate
structure that, together with the flip-flops, produces a circuit that fulfills the stated specifications.
The number of flip-flops is determined from the number of states needed in the circuit.

The combinational circuit is derived from the state table by evaluating the flip-flop input equations
and output equations. The procedure for designing synchronous sequential circuits can be
summarized by the following steps:

1. Derive a state diagram from given specifications and obtain a state table from given
specifications or state diagram.

2. Reduce the number of states if necessary.

3. Choose the type of flip-flops to be used.

4. Derive the simplified flip-flop input equations and output equations.

5. Draw the logic diagram.

Example 1: Implementation of a design whose state diagram is given in the below figure

79
Example 2: Sequence Detector

An application of sequential logic circuit is to implement finite state automaton. We will design
an one-input, one output sequence detector which produces an output 1 every time the sequence
0101 is detected, and an output 0 at all other times. Design and construct the sequence detector
using D flip-flops.

80
X=001010011101001
Z=000010000001000
Follow the same procedure as before beginning from the state graph.

Example 3:

Design a circuit that detects a sequence of three or more consecutive 1’s in a string of bits
coming through an input line
Start with S0.
if input is 0, stay in S0.
if input is 1, go to S1.
Once in S1
if input is 1, go to S2.
if input is 0, go to S0.
Once in S2
if input is 0, go to S0.
if input is 1, go to S3.
Once in S3,
if input is 0, go to S0.
if input is 1, stay in S3, set output to 1.
Output is 1 when the circuit is in S3, 0 otherwise

81
82
4. Procedure

1. You are required to construct a sequence recognizer circuit as shown in example 2. The circuit
should have a single-bit serial input and a single-bit output. Design the sequence detector which
produces an output 1 every time the sequence 010 is detected with overlapping allowed. The
circuit should be implemented using D FF

2. Redesign the sequence detector using T FF and implement it using IC 7476 JK FF.

3. Redesign your circuit with overlapping is not allowed.

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 Experiment # 9: Ripple Counter
1. Objectives:
The objectives of this experiment are:
• To implement the Ripple (Asynchronous) binary counter using flip-flops and verifying
the function
2. Components:
- 7476 IC (Dual Master-slave JK Flip-Flops With Preset And Clear).
- 7408 IC (AND gates).
- IC trainer Kit
3. Background:
A counter is a sequential logic circuit that goes through a prescribed sequence of states upon
the application of input pulses. The prescribed sequence can be a binary sequence or any
other sequence. A counter that goes through 2N (N is the number of flip-flops in the series)
states is called a binary counter. The modulus of a counter is the number of different states
it is allowed to have. Counter modulus is normally 2N unless controlled by a feedback
circuit which limits the number of possible states (an example being the decimal counter).
Counters are very widely used in almost all computers and other digital electronic systems.
There are two major categories of counters: asynchronous counters and synchronous
counters.
3.1 Asynchronous Counters
Counters arranged so that the output of one flip-flop generates the clock input of the next
higher stage are generally called asynchronous counters (or ripple counter). In other words,
in asynchronous counters, the CLK inputs of all flip-flops (except the first one) are triggered
not by the incoming pulses but rather by the transition that occurs in other flip-
flops. Therefore, the change of state of a particular flip-flop is dependent upon the present
state of other flip-flops. Fig. 1 shows a count-up ripple counter. When a transition from,
say, 0111 to 1000 occurs, the one-to-zero transition of the low-order three bits ripples from
bit to bit. Since each flip-flop has a non-zero propagation delay, ripple counters are
relatively slow. Therefore, an upper limit on the number of flip-flops in the flip-flop chain
ought to be imposed.

84
 Figure 1: 4-bit ripple counter.
3.2 Synchronous Counters
Synchronous counters eliminate the cumulative flip-flop delay seen in ripple counter. Each
flip-flop is clocked by the same clock signal. Each gate selectively controls when each more
significant bit flip-flop is to change state (toggle) on the next clock transition. Such control
(enable) can be realized by setting, for example, the J and K inputs of a J-K flip-
flop. Because of this control, the addition of a common clock will synchronize data transfer
and all flip-flops will change state simultaneously. The important feature of a synchronous
counter is that the transitions of the individual flip-flops are synchronized to a master clock
signal.
J-K flip-flops are normally used in the synchronous counters due to the enabling
(controlling) feature of the J and K inputs. There are two basic schemes for generating the
J and K inputs. One of them is illustrated in the four-bit binary counter shown in Fig.
2. Notice that the information to the J-K inputs is formed in a parallel fashion. The counter
is accordingly termed as synchronous parallel counter. In the parallel scheme the number
of inputs to each AND gate increases linearly with the number of stages. For this added
expense one gets the fastest possible synchronous counting circuit.

Figure 2: 4-bit synchronous counter.

85
4. Procedure:
A. Connect the count-up ripple counter shown in Figure 1 using two 74LS76 IC type.
Set data switch SW1 from logic 0 to logic 1 (clear all flip-flops). Now connect CLK
to a pulse generator in your pencil box (J-K flip-flops in 74LS76 are negative edge
triggered) and start counting by pushing the pulser button. Continue the process and
record the output of each transition in a truth table. Does it count correctly?
B. We can convert the count-up ripple counter to a count-down ripple counter by
connecting the clock of the flip-flops to Q instead of Q (the LEDs are still connected
to Q). Make the modification and try out the circuit.
C. Connect the 4-bit synchronous parallel counter as shown in Figure 2. Repeat the
same procedures in the ripple counter experiment. From the transition table of the
counter and the excitation table of the J-K flip flop, verify that the J-K inputs to the
flip flops are correct.

86