Block RAM (BRAM) in an FPGA

They are used for FIFOs, Dual Port Memories

BRAMs are used for storing large amounts of data inside FPGA. They are one of four
commonly identified components on an FPGA datasheet. The other three are Flip-
Flops, Look-Up Tables (LUTs), and Digital Signal Processors (DSPs).

Usually, the bigger and more expensive the FPGA, the more Block RAM it will have on
it. Since this is found right at the top of an FPGA product overview, it must be
important!
 Block RAM (BRAM) in an FPGA
As an example, the image below shows the Product overview line comparing
different Intel Cyclone V FPGAs.
 Block RAM (BRAM) in an FPGA
A BRAM is also called embedded memory, or Embedded Block RAM (EBR)), is a discrete part of an
FPGA, meaning there are only so many of them available on the chip.

Each FPGA has a different amount, so depending on your application one may need more or less
BRAM. Knowing how much one will need gets easier as you become a better Digital Designer.

It’s used to store “large” amounts of data inside of the FPGA. It’s also possible to store data outside of
the FPGA, but that would be done with a device like an SRAM, DRAM, EPROM, SD Card, etc.

BRAMs come in a finite size, 4/8/16/32 Kb (kilobits) are common. They

have a customizable width and depth. And they’re useful for lots of
applications.
 Block RAM (BRAM) in an FPGA
Single Port BRAM Configuration

The Single Port BRAM configuration is useful when there is just one interface that
needs to retrieve data. This is also the simplest configuration and is useful for some
applications.

One example would be storing Read-Only Data that is written to a fixed value when
the FPGA is programmed.

The way they work is all based on a Clock. Data will be read out on the positive edge of the clock cycle at the address
specified by Addr as long as Wr En signal is not active. Read values come out on Rd Data, this is the data stored in the
BRAM. Note that you can only read one Rd Data value per clock cycle. So if Block RAM is 1024 values deep, it will
take at least 1024 clock cycles to read the entire thing out.

If one want to write some data into the BRAM buffer, then read it out at a later time. This would involve driving Wr
En high for one clock cycle and Wr Data would have the write data. For the single port configuration, one can either
read or write data on Port A, one can’t do both at the same time.
 Block RAM (BRAM) in an FPGA
Dual Port BRAM Configuration

The Dual Port Block RAM (DPRAM) configuration behaves exactly the
same way as the single port configuration, except it has another port
available for reading and writing data.

Both Port-A and Port-B behave exactly the similar. Port A can perform a
read on Address 0 on the same clock cycle that Port B is writing to
address 200.

DPRAM can perform a write operation on one address while reading from
a completely different address. More use cases for DPRAMs than Single-
Port RAMs.

DPRAMs are commonly turned into FIFOs, which are probably one of the most common use-
cases for BRAM on an FPGA.
 FIFO BRAM Configuration

First In First Outs (FIFO) are used all over

the place in FPGA design. Any time one need
to buffer some data between two interfaces
then FIFO is required.
 FIFO BRAM Configuration
BRAM is a type of random-access memory embedded throughout an FPGA for
data storage.

BRAM used to accomplish the following tasks:

▪ Transfer data between multiple clock domains by using local FIFOs

▪ Transfer data between an FPGA target and a host processor by using a DMA
FIFO
▪ Transfer data between FPGA targets by using a peer-to-peer FIFO
▪ Store large data sets on an FPGA target more efficiently than RAM built from
look-up tables
 Distributed RAM in an FPGA
Distributed RAM is, as its name suggests, distributed
throughout the FPGA.

A single 6-input LUT can store 64 bits, while a 4-input LUT can
store 16 bits. Distributed ram is read asynchronously but
written to synchronously (requires a clock).

BRAM is implemented using dedicated ram circuitry within the FPGA and is ideal for
memories from a few hundred bits up to hundreds of kilobits. But BRAM is not just better
than distributed RAM for larger memories: BRAM is one of the great things about
developing hardware with FPGAs.
 Distributed RAM in an FPGA

BRAM is a dedicated RAM that does not consume any additional LUT in
the design whereas Distributed RAM is built up with LUT.

In terms of speed the Distributed RAM is faster than BRAMs.

Generally, if not high memory size is needed one can consider to

implement it as a Distributed RAM
BRAM Distributed RAM