SIR UNIVERSITY ‘Submitted By: Name: Muhammad Shamil Imran ID No: 210734 Class/Sec: BEEE-6-A Submitted To: Engr. Mashood Ahmad Instructor's Remarks: Submission Time: Ta Late im Working Days Time [0 7] 1 ]2 )]3 4 Marks: Total Marks Obtained Marks Additional Remarks: Instructor's Signature:Problem +e2L LATCH - | The Basic memory elementythe Latch as shown in Fgure @ baled; W x y 2 @ It consists of twe cross coupled log fe inverters, Gi ard Gz. The inverters form o positive Feedback it’s operabien we break the feed back loop. 16 investigate ¥ Gy on leop at the input of one of the inverters say apply ar input signal Vw, 26 shown in (b) 1) i rf the input impedance is large (Ga), breaking feedbick ‘loop wills net change the leep VTC. We plet Ve vesuc Uw in figure (©) which ig Volisge tmnefer characteristic of two cascaded Inverters Scanned with CamScannerB Problem +E NOR Gate Implementation of SR Flip-Flop :- The simplest type of Fup-Flep is the set/ reset GsR) Lip Flee shown be law in Figure @ F Q 3 Q [+ is formed by Cross coupling tue NoR 9 ates, and thus it incorporates a latch. The seond inputs of & and Gy sere as trigger inpets of flip-flp . They labeled S (Fr Set) ang R Chr Reset). When both inputs are low(O),the flipflp holds its ctate. Setting Ste high Wy and R t low Co) makes the output @ high C1), white stb Rte high CL) and ste low (0) makes the autpet Q/ high (1) Scanned with CamScannerWhen bethinpts are high), r results in ah undetined stake. It is shown below jn Vtruth table in Agere (b)- R § Qria Qn ® Problern 443 _ “CIOS _irplementeckion of Six, FUpeRere Tra cmos implementation of an SR Pu Pens" cross-coupled inverters are used. Each inverter 'S composed cf both a Pmes and an NMOS transistor The inputs S ancl Ro control the states f the transistors, the oukpt setes (Q and Q’). fh offers low determini ise i i it Power consumption and high rie naan to its su ow Voo A complermenteary structure in fare below - I Scanned with CamScanner"ENG Preceding deseription oF -Alip-Tlep switching is Predicated on “twe assumptions :- ’ i 1) Transistors Qs and Qe ser gdficient current te Pull the node Q downte a voltrge at least slighty below the threshold of the C@s, Qy) inverter. This !S essential for the enerative process to in We the mitiaL “trigger athe Flip-Flop wi fait V to switch. 2) The set signal remain high for an iwterval a enough + cause regeneration to “belte over the Switch Process. Ain estimate lof the reinimum width required for the set pulse can be obtnined 6 the sum 0 the intel daring which VO 's reduced -from Vip te Von. and the interval for the voltage Va te respene Yoo 2 ond rise © Vey . Surinety indicates that process wi the reset Process+ Problem KY D.- Flip Flop: ee Tre Yoh Principal Fa D-Fip fiep ts pretty straight forward . The dD inpot represents the data want to stere or transfer The Clock CP) contreL signal The O flip Asp oper the Felling edge . When the Clock signal transitions the D Flip fiep evaluates the value present at the D-inpot . UF D is high, Fup Flep sets ites output Q te high or vice-versa - Scanned with CamScanner (Wl be seme for tha we inp serves as a 8 the nity cdg °Bebween cleck transitions the flip flep retains the value Present at the D input . This means thak the output Q remains stable until the hext cleck edge. There might be a sight delay between the clock” edge andl the conrespondira charge in output &.This di , \s rnowh a Prepogestion delay. Figures are beloul; PL Do It is. e o S| U ® Scanned with CamScanner