Program : B.

Tech
Subject Name: Microcontroller & Embedded System
Subject Code: EC-604
Semester: 6th
Downloaded from www.rgpvnotes.in

Microcontroller & Embedded System (EC604)

UNIT II: Microcontroller 8096: Introduction to 16-bit Microcontroller, functional block-diagram, memory
status, complete 8096 instruction set, classification of instruction set, addressing modes, programming
examples using 8096, hardware features of 8096,parallel ports, control &status Registers, Introduction to
16/32 bit PIC microcontrollers and DSPIC.
-------------------------------------------------------------------------------------------------------------------------------------------
Introduction to 16-bit Microcontroller:
The 8096 is a 16-bit microcontroller. It is specially suited for embedded control applications. It has all the
features of 8051 with additional features present in 8096 are A/D converter, high speed inputs, high speed
outputs, generation of analog output analog voltage and mechanism for self-checking in runtime. It has a
powerful instruction set and addressing modes. It has the following important key features,
Hardware Features of 8096:
(i) It is a 16-bit microcontroller.
(ii) 8096 is been designed for high speed/high performance control applications.
(iii) It has 8 multiplexed input analogs to digital converter with 10-bit resolution.
(iv)The high speed I/O section of 8096 comprises a 16-bit timer, a 16-bit counter and 4 input
programmable edge detector, 4 software timers and 6 output programmable event generator.
(v) Its serial port support different modes of operation with programmable baud rates.
(vi) It supports register to register architecture which increases processing speed.
(vii) It is programmable pulse width modulation (PWM) output signals can be used as control signals to
drive a motor or any other application.
(viii) It has 100 instructions that can operate on bit, byte, word, double words.
(ix) It consists of a complete set of 16-bit arithmetic instructions that include multiply and divide
operations.
(x) It allows bit operations. They are done on any bit in the register file or in the special function register.
(xi) Logical are arithmetic instructions support byte and word operations.
(xii) The watchdog timer can be used to reset the system if software fails to operate properly.

Functional Block-Diagram:

Fig. 2.1: Functional Block Diagram of 8096 Microcontroller

Page no: 1 Get real-time updates from RGPV

Downloaded from www.rgpvnotes.in

The 8096 family of microcontrollers has several sections, the major sections include a 16 bit CPU, a
programmable high speed input/output unit, on-chip RAM, on-chip ROM, analog to digital converter, serial
port and pulse-width modulated output for analog to digital converter. Fig. 2.1 shows the internal
architecture of 8096 microcontroller. It consists of several functional units. They are.
(i) CPU with 232 byte register file and register ALU.
(ii) 8KB internal ROM.
(iii) Programmable high speed I/O unit.
(iv) Two 16 bit timers/counters.
(v) Serial ports.
(vi) Pulse width modulator.
(vii) Watchdog timer
(viii) Memory controller.
(ix) Eight multiplexed inputs A/D converter with 10 bit resolution.
The two main buses, address bus and data bus are used for inter-processor communication. It has address
bus of 8 bit and data bus is 16 bit. The data bus transfers data between RALU and register file or special
function registers. (SFRs). The address bus provides addresses for multiplexed address/data bus
connecting to the memory controller. The memory controller provides the addresses for the internal ROM
and external memory.

RALU: The register arithmetic and logic unit (RALU) contains:

(i) 17 bit ALU (ii) Program counter along with incrementer. (iii) Program status word.
(iv) Loop counter (5 bit). (v) Two shift registers (17 bit). (vi) Temporary registers (17 bit).

Fig. 2.2: RALU Internal Logic Diagram

• For instruction requiring shift for execution, shift registers are provided. e.g.: shift left, shift right,
normalize, multiply, divide etc.
• When a 16-bit data is to be shifted, an upper word register/shifter is used. The lower word/shifter
is used along with upper word register/shifter in case of 32-bit shift.
• For the instructions that require repetitive shifts (e.g. shift right by 5 bits), a 5 bit loop counter is
useful.

Page no: 2 Get real-time updates from RGPV

Downloaded from www.rgpvnotes.in

• For execution of two operand instructions, a temporary register is provided. This temporary
register stores the multiplier during the execution of multiplication instruction, or divisor during
execution of division instruction.
• For the execution of increment/decrement instructions some constants are defined. The constants
0,1,2 are stored in RALU to execute the instruction faster.
• The A bus (address bus) is 8 bit wide. It is used to transfer 16 bit address or data information to
memory controller or other units. A delay circuit is provided. It facilitate transfer of lower byte
followed by delay followed by upper byte to the memory controller.
• Program counter and incrementer are provided in RALU to increment the PC after execution of
each instruction. Thus, it points to the next instruction to be executed.
• In case of jump instructions being executed, the program counter is modified through ALU.

Program Status Word:

The program status word signifies the status of interrupt flags as well as condition flags at any instant.
Fig. 2.33 show PSW.

Fig. 2.3: Program Status Word

N: Indicates that the last instruction generated negative result.
V: Result generated in outside the range that can be expressed in the destination data type thus
causing overflow.
VT : When the V flag is set, VT (overflow trap) is also set. However, it can be reset by certain explicit
instructions. It is useful in debugging the program.
C: Indicates that a bit is shifted out of MSB or ISB position because of arithmetic or shift operations.
ST : Can be used for controlling rounding after right shift called “sticky bit”. It indicates that 1 has
been shifted first to c flag and then out during right shift.
I: It is set by EI instruction and cleared by DI instruction. It indicates global interrupt enable/disable.
These conditional flags (except I) can be used in conditional jump instructions.

Memory Status (Memory Mapping):

The 8096 can access up to 64 KB memory. The scratch pad register (called as register file), special function
registers, on-chip RAM, on-chip ROM and external memory space are the main constituents of memory.
Fig. 2.2 shows the map of 64kB addressable memory space.

Fig. 2.4: Memory Map

Page no: 3 Get real-time updates from RGPV

Downloaded from www.rgpvnotes.in

The basic blocks are:

(i) Internal RAM containing
(a) Special function registers (00 to 17H).
(b) Stack pointer (18H and 19 H)
(c) Register file (1AH to EFH)
(d) Power down RAM (F0H to FFH)
This memory area is accessed as data memory. No code can be executed from this area. The program
memory area of 00 to FFH is reserved for internal use of intel development systems.
(ii) Internal ROM
If the chip has on-chip ROM then it has interrupt vectors, factory test code, internal program storage. It is
available at addresses (2000H – 3FFFH).
If the chip does not contain ROM, then these are defined in the external memory.
(iii) External memory or I/O are available at addresses (0100H – 1FFDH) and (4000H – FFFFH).
(iv) Port 3 and 4 locations (1FFEH and IFFFH) for the reconfiguration if they are not used as address/data
lines.
When the 8096 is reset, address 2080H is loaded to the program counter to give 8 KB of contiguous
memory.

I/O Ports 0, 1, 2, 3 and 4

8096 has five 8 bit I/O ports. Some of them are input ports while some of the ports are output ports and
other ports are bidirectional and have alternate functions.
• The input ports connect to the internal bus through an input buffer.
• The output ports connect through the output buffer to an internal register that holds the output bits.
• Bidirectional ports comprise of an internal register, an input buffer and an output buffer.
• When an instruction accesses a bidirectional port as source register, the value comes from the port
pins, not the internal register.

Port 0: Port 0 is an input port. It shares its pins with the analog inputs to the A/D converter.

Port 1:
• A is a quasi-bidirectional I/O port. The word “quasi-bidirectional” means that the port pin has a
weak internal pull up that is always active and an internal pull-down than can be on/off.
• The pin’s logic level can be controlled by an external pull-down if the internal pull-down is left off.
(i.e. a 1 is written).
• A quasi-bidirectional port will source current if externally held it. It will pull itself high if it is left
unconnected.
• If the processor writes to the pins of a quasi-bidirectional port it actually writes into the register
that drives the port pin.
• If the port pin is to be used as an input then the software must write a one to SFR bit. This causes
the low impedance pull down device to turn off and leave the pin pulled with a high impedance
pull up device that can be driven by the device that drives the input.

Page no: 4 Get real-time updates from RGPV

Downloaded from www.rgpvnotes.in

Port-2: It is a multi-functional port. Table gives Port 2 functions.

Port Function Alternate Function Controlled by

P2.0 Output TxD (Serial Port Transmit) IOC1.5
P2.1 Input RxD (Serial Port Receive) in Model -3 N/A
P2.1 Output RxD (Serial Output Port) in Mode 0 N/A
P2.2 Input External interrupt IOC1.1
P2.3 Input T2CLK (Timer 2 input) IOC1.7
P2.4 Input R2RST (Timer 2 Reset) IOC0.5
P2.5 Output PWM (Pulse Width Modulation) IOC1.0
P2.6 Quasi-bidirectional N/A
P2.7 Quasi-bidirectional N/A

Ports 3 and 4/ AD0 – AD15:

• These pins serve as bidirectional ports with open drain outputs or system bus pins used by memory
controller when it accesses external memory.
• If the (EA)* line is low, it serves as system bus. If (EA)* line is set, then they are used as Ports. The
port pins and their system bus functions are given below:

Status and Control Registers:

I/O Control Registers: There are two I/O control register, IOC0 and IOC1. IOC0 controls Timer 2 and HSI
lines. IOC1 controls some pin function, interrupt sources and two HSO pins.

Page no: 5 Get real-time updates from RGPV

Downloaded from www.rgpvnotes.in

I/O Control Registers 0 (IOC0):

• The address of IOC0 control register is 0015H. Fig. 2.5 shows format for I/O control register0
(IOC0).
• The four HSI lines can be enabled or disabled to the HSI unit by setting or clearing bits in IOC0.
• The Timer 2 functions include clock and reset sources can be determined by IOC0.

Fig. 2.5: I/O Control Register 0 (IOC0) Fig. 2.6: I/O Control Register 1 (IOC1)

I/O Control Register 1 (IOC1):

The address of IOC1 control register is 0016H. Fig. 2.6 shows format of I/O control register 1. It is used to
select some pin functions and enable / disable some interrupt sources.
• Pin P2.5 can be selected to PWM output. The external interrupt source can be selected to EXTINT
or analog channel 7(A CH7).
• Timer 1 and 2 overflow interrupts also can be individually enabled or disabled.
• The HSI interrupt can be selected in order to activate either when there is 1 FIFO entry or 7.
• The port pint P2.0 can be selected to TXD output. HSO.4 and HSO.5 can be enabled or disabled to
HSO unit.
I/O Status Register 0 (IOS0):
Its address is 0015H. Fig. 2.7 shows IOS0 register. It holds the current status of HSO lines and CAM.

Fig. 2.7: I/O Status Register 0 (IOS0) Fig. 2.8: I/O Status Register 1 (IOS1)

Page no: 6 Get real-time updates from RGPV

Downloaded from www.rgpvnotes.in

I/O Status Register 1 (IOS1):

Its address is 0016H. It shares the address of IOC1 control register. Fig. 2.8 shows IOS1 status register. It
contains the status bits for timers and HS I/O. Each access to this register clears all time related flags.
Hence, it is important to store a byte in temporary location before attempting to test bit.

Watch Dog Timer:

• An on chip 16-bit watch dog timer is available in 8096 which helps to recover the controller from the
software upsets.
• This 16-bit WDT is a counter which is incremented every state time. This counter is cleared by program
after periodic interval and not allowed to overflow.
• However, if the program does not progress properly by any reason such as Electrostatic Discharge
(ESD) or due to any hardware related problems, the overflow occurs.
• The hardware reset is initiated to restart the microcontroller. This process avoids the system from
having a malfunction for longer than 16mS under 12MHz frequency operation When the WDT
overflows, it pulls down the RESET pin for at least two state times resetting 8096 and any other devices
connected to the RESET line.

Addressing Modes: The 8096-instruction set supports six addressing modes. They are
• Immediate addressing mode
• Register direct addressing mode
• Indirect addressing mode
• Indirect with auto increment mode
• Short indexed mode
• Long indexed mode.
These addressing modes increase the flexibility and overall execution speed of 8096 controller. Each
instruction uses at least one of the addressing modes. The register, direct and immediate addressing
modes execute faster than the other addressing modes. Both of the indirect addressing modes use the
value in a word register as the address of the operand. The indirect auto increment mode increments a
word address by one after a byte operation and two after a word operation.

Page no: 7 Get real-time updates from RGPV

 We hope you find these notes useful.
You can get previous year question papers at
https://qp.rgpvnotes.in .

If you have any queries or you want to submit your

study notes please write us at
rgpvnotes.in@gmail.com