Logic 2

Digital Computer Systems
• Digital systems consider discrete amounts of data.

• Examples
– 26 letters in the alphabet
– 10 decimal digits
• Larger quantities can be built from discrete values:
– Words made of letters
– Numbers made of decimal digits (e.g. 239875.32)
• Computers operate on binary values (0 and 1)
• Easy to represent binary values electrically
– Voltages and currents.
– Can be implemented using circuits
– Create the building blocks of modern computers
Logic Circuits -Dr. Mohamad Alwan 1
Understanding Decimal Numbers
• Decimal numbers are made of decimal digits: (0,1,2,3,4,5,6,7,8,9)

• Decimal number:
– 8653 = 8x103 + 6x102 + 5x101 + 3x100
• What about fractions?
– 97654.35 = 9x104 + 7x103 + 6x102 + 5x101 + 4x100 + 3x10-1 + 5x10-2
– In formal notation -> (97654.35)10
• Why do we use 10 digits, anyway?
1
Understanding Binary Numbers
• Binary numbers are made of binary digits (bits):

– 0 and 1
• binary number:
– (1011)2 = 1x23 + 0x22 + 1x21 + 1x20 = (11)10
• What about fractions?
– (110.10)2 = 1x22 + 1x21 + 0x20 + 1x2-1 + 0x2-2
• Groups of eight bits are called a byte
– (11001001) 2
• Groups of four bits are called a nibble.
– (1101) 2
Conversion Between Number Bases
Decimal(base 10) Binary(base 2)
Hexadecimal
(base16)
° Learn to convert between bases.
2
Decimal review
• Numbers consist of a bunch of digits, each with a weight
1 6 2 . 3 7 5 Digits
100 10 1 1/10 1/100 1/1000 Weights
• These weights are all powers of the base, which is 10. We can rewrite
this:
1 6 2 . 3 7 5 Digits
102 101 100 10-1 10-2 10-3 Weights
• To find the decimal value of a number, multiply each digit by its weight
and sum the products.
(1 x 102) + (6 x 101) + (2 x 100) + (3 x 10-1) + (7 x 10-2) + (5 x 10-3) = 162.375
Converting binary to decimal

• We can use the same trick to convert binary, or base 2, numbers to
decimal. This time, the weights are powers of 2.
– Example: 1101.01 in binary
1 1 0 1 . 0 1 Binary digits, or bits
23 22 21 20 2-1 2-2 Weights (in base 10)
– The decimal value is:
(1 x 23) + (1 x 22) + (0 x 21) + (1 x 20) + (0 x 2-1) + (1 x 2-2) =

8 + 4 + 0 + 1 + 0 + 0.25 = 13.25
Powers of 2: Useful abbreviations:

20 = 1 24 = 16 28 = 256 K = 210 = 1,024
1
2 =2 25 = 32 29 = 512 M = 220 = 1,048,576
22 = 4 26 = 64 210 = 1024 G = 230 = 1,073,741,824
3
2 =8 27 = 128
3
Converting decimal to binary
• To convert a decimal integer into binary, keep dividing by 2 until the
quotient is 0. Collect the remainders in reverse order.
• To convert a fraction, keep multiplying the fractional part by 2 until it
becomes 0. Collect the integer parts in forward order.
• Example: 162.375:
162 / 2 = 81 rem 0 0.375 x 2 = 0.750

81 / 2 = 40 rem 1 0.750 x 2 = 1.500
40 / 2 = 20 rem 0 0.500 x 2 = 1.000
20 / 2 = 10 rem 0
10 / 2 =5 rem 0
5/2 =2 rem 1
2/2 =1 rem 0
1/2 =0 rem 1
• So, 162.37510 = 10100010.0112
Base 16 is useful too

• The hexadecimal system uses 16 digits:
Decimal Binary Hex
0123456789ABCDEF 0 0000 0
• You can convert between base 10 and base 1 0001 1
16 using techniques like the ones we just 2 0010 2
showed for converting between decimal and 3 0011 3
binary. 4 0100 4
5 0101 5
• For our purposes, base 16 is most useful as
6 0110 6
a “shorthand” notation for binary numbers.
7 0111 7
– Since 16 = 24, one hexadecimal digit is 8 1000 8
equivalent to 4 binary digits. 9 1001 9
– It’s often easier to work with a number 10 1010 A
like B4 instead of 1011 0100. 11 1011 B
12 1100 C
13 1101 D
14 1110 E
15 1111 F
4
Binary and hexadecimal conversions
• Converting from hexadecimal to binary is easy: just replace each hex
digit with its equivalent 4-bit binary sequence.
261.3516 = 2 6 1 . 3 516
= 0010 0110 0001 . 0011 01012
• To convert from binary to hex, make groups of 4 bits, starting from the
binary point. Add 0s to the ends of the number if needed. Then, just
convert each bit group to its corresponding hex digit.
10110100.0010112 = 1011 0100 . 0010 11002

= B 4 . 2 C16
Hex Binary Hex Binary Hex Binary Hex Binary

0 0000 4 0100 8 1000 C 1100
1 0001 5 0101 9 1001 D 1101
2 0010 6 0110 A 1010 E 1110
3 0011 7 0111 B 1011 F 1111
Hex to Decimal
This time, the weights are powers of 16.

8 7 C 9 =8 x 163+7 x 162+C x 161+9 x 160=34 761
8 7 C 9
x 16
128
+ 7
135
x 16
2,160
+ 12
2,172
x 16
34,752
+ 9
34,761Logic Circuits -Dr. Mohamad Alwan
10
5
Convert Decimal to Hex
Integer Part: Divide by the base,

keep track of the remainder, and read up.
16 34,761
16 2,172 rem 9
16 135 rem 12 = C Read up
16 8 rem 7
0 rem 8
34,76110 = 87C916
Questions
100101012 = ? (decimal)
6
Questions
100101012 = ? (decimal)
1 0 0 1 0 1 0 1
27 26 25 24 23 22 21 20
The decimal Value:
(1 x 27) + (0 x 26) + (0 x 25) + (1 x 24) + (0 x 23) + (1 x 22) + (0 x 21) + (1 x 20) =

128 + 0 + 0 + 16 + 0 + 4 + 0 + 1 =
(149)10
Questions
85710 = ?16
7
Questions
BED16 = ?2
8
9
Exercise 1:
Convert these decimal numbers: 17.76 - 1958.56
- To binary
- To octal (directly from decimal)
- To hexadecimal (directly from decimal)
- To octal (from binary)
- To hexadecimal (from binary)
Exercise 2:
Find the decimal numerical values of:
- The binary numbers: 1101.1 - 101.0101 - 110101.101
- The octal numbers: 236 - 702.41 - 1011.1
- The hexadecimal numbers: A0B.5 – 1011.1 - FC3.0E
17.76=10001.11000010100011110101 1100
1958.56= 11110100110.100011110101110000101
0.56*2=1.12 0.64*2=1.28
0.12*2=0.24 0.28*2=0.56
0.24*2=0.48 0.56*2=1.12
0.48*2=0.96
0.96*2=1.92
0.92*2=1.84
0.84*2=1.68
0.68*2=1.36
0.36*2=0.72
0.72*2=1.44
0.44*2=0.88
0.88*2=1.76
0.76*2=1.52
0.52*2=1.04
0.04*2=0.08
0.08*2=0.16
0.16*2=0.32
Logic Circuits -Dr. Mohamad Alwan
0.32*2=0.64 20
10
17.76 = (21.60507534121727024365)8 0.76*8=6.08 0.72*8=5.76
0.08*8=0.64 0.76*8=6.08
0.64*8=5.12
0.12*8=0.96
0.96*8=7.68
0.68*8=5.44
0.44*8=3.52
0.52*8=4.16
0.16*8=1.28
0.28*8=2.24
0.24*8=1.92
0.92*8=7.36
0.36*8=2.88
0.88*8=7.04
0.04*8=0.32
0.32*8=2.56
0.56*8=4.48
0.48*8=3.84
0.84*8=6.72
(1958.56)10=(3646.43656050753412172703)8
0.76*16=C.16
-(17.76)10 = ? Base 16 = 11.C2F5 0.16*16=2.56
0.56*16=8.96
0.96*16=F.36
0.36*16=5.76
0.76*16=C.16
-(1958.56)10=? Base 16=7A6.8F5C2 8F5C2
16 0.56*16=8.96
1958
0.16*16=F.36
6 122 16 0.36*16=5.75
7 16 0.76*16=C.16
A 0.16*16=2.56
7 0
0.56*16=8.96
11
Exercise 1:
Convert these decimal numbers: 17.76 - 1958.56
- To binary
- To octal (directly from decimal)
- To hexadecimal (directly from decimal)
Exercise 2:
- The octal numbers: 236 - 702.41 - 1011.1
(17.76)10 =10001.11000010100011110101 1100
010/001.110/000/101/000/111/101/01 1/100
2 1 . 6 0 5 0 7 5 3 4
1958.56= 11110100110.100011110101110000101
0011/110/100/110.100/011/110/101/110/000/101
3 6 4 6 . 4 3 6 5 6 0 5
12
(17.76)10 =10001.11000010100011110101 1100
001/0001.1100/0010/1000/1111/0101/ 1100
1 1 . C 2 8 F 5 C
(1958.56)= 11110100110.100011110101110000101
0111/1010/0110.1000/1111/0101/1100/0010/1000
7 A 6 . 8 F 5 C 2 8
Exercise 2:

1101.1 =? Base 10
1 1 0 1 . 1
23 22 21 20 . 2-1 Weight of power 2
The decimal Value : (multiply each digit by its weight and sum the products)
1101.1 = (1 x 23) +(1x 22 )+(0x 21)+ (1x 20) . ( 1x 2-1 )= (13.5)10
- 101.0101=?Base 10
1 0 1 . 0 1 0 1
22 21 20 . 2-1 2-2 2-3 2-4
101.0101= (5.3125)10
13
110101.101= ? Base 10
1 1 0 1 0 1 . 1 0 1
25 24 23 22 21 20 . 2-1 2-2 2-3
The decimal value :

110101.101 = (53.625)10

The octal numbers: 236 - 702.41 - 1011.1
2 3 6
82 81 80
(236)8= (158)10
(702.41)8 = (450.515625)
(1011.1)8= (521.125) Logic Circuits -Dr. Mohamad Alwan 27

A0B.5=2571.3125
1011.1=4113.0625
FC3.0E=4035.0546875
14
Chapter 2: Arithmetic Operations
we will focus our efforts on the basics that allow us to understand how digital
machines (i.e. computers) perform basic arithmetic operations.
Binary Addition
The addition of two binary numbers is perfectly analogous to the addition of
two decimal numbers.
However, there are only four cases, which can occur when adding two binary
digits . These four cases are:
15
• Binary addition is very simple.
• This is best shown in an example of adding two binary numbers…
Binary Addition
• Binary addition is very simple.

• This is best shown in an example of adding two binary numbers…
1 1 1 1 1
1 carries
1
1 1 1 0 1
+ 1 0 1 1 1
---------------------
1 0 1 0 1 0 0
16
Binary addition example worked out
• Some terms are given here
• Exercise: what are these numbers equivalent to in decimal?
The initial carry

in is implicitly 0
1 1 1 0 (Carries)
1 0 1 1 (Augend)
+ 1 1 1 0 (Addend)
1 1 0 0 1 (Sum)
most significant least significant

bit (MSB) bit (LSB)
Subtraction
Binary Number Subtraction Value
0–0 0
1–0 1
0–1 1 (Borrow 1 from next high order digit)
1–1 0
17
Binary Subtraction
° We can also perform subtraction (with borrows in place of

carries).
° Let’s subtract (10111)2 from (1001101)2…
1 10 borrows
0 10 10 0 0 10
1 0 0 1 1 0 1
- 1 0 1 1 1
------------------------
1 1 0 1 1 0
• Example
18
Binary Multiplication
Binary Multiplication
• Binary multiplication is much the same as decimal multiplication,

except that the multiplication operations are much simpler…
1 0 1 1 1
X 1 0 1 0
-----------------------
0 0 0 0 0
1 0 1 1 1
0 0 0 0 0
1 0 1 1 1
-----------------------
1 1 1 0 0 1 1 0
19
Binary Division
Representation of negative numbers and the two’s (2 th)

complement of a binary number
1’s Complement
• Algorithm – the 1’s complement of a binary number is the number

that results when we complement each bit.
• Since each bit drives an inverter :
– Finding the 1’s complement of (01100101)2

1’s complement : C1(N) =10011010)
20
Two’s Complement Shortcuts
• Algorithm – Simply complement each bit and then add 1 to the
result.
• The value of 2’s complement (C2(N)) to represent negative
numbers.
Two’s Complement Shortcuts
– Finding the 2’s complement of (01100101)2 and of its 2’s

complement…
N = 01100101 [N] = 10011011

10011010 01100100
+ 1 + 1
--------------- ---------------
C2(N) 10011011 01100101
21
Signed and unsigned numbers
Signed and unsigned numbers
22
Table 2.2
Positive and Negative Binary Numbers
Signed decimal Hex Binary Unsigned decimal
-128 80 10000000 128
-127 81 10000001 129
-126 82 10000010 130
… … … …
… … … …
… … … …
-3 FD 11111101 253
-2 FE 11111110 254
-1 FF 11111111 255
0 00 00000000 0
1 01 00000001 1
2 02 00000010 2
3 03 00000011 3
… … … …
… … …
… … …
125 7D 01111101 125
126 7E 01111110 126
127 7F 01111111 127
Signed Numbers
4-bit: 8H = -8 to 7H = +7
1000 to 0111
8-bit: 80H = -128 to 7F = +127
16-bit: 8000H = -32,768 to

7FFFH = +32,767
32-bit: 80000000H = -2,147,483,648 to

7FFFFFFFH = +2,147,483,647
23
Subtract by Adding
Subtract by adding
73 73
-35 10’s complement +65
38 138
Ignore carry
Subtract by Adding
Subtract by adding (8-bits)

73 73 01001001
-35 35 00100011
38 C1(N) 11011100 flip
+1
-----------
01001001 -35 11011101

2’s comp
+1 10111 01
100100110 8 - bits
overflow (38)10
Sign bit
24
Subtract by Adding
Questions
What is the two’s complement of

00101100?
What hex number represents the

decimal number -40?
25
BCD
Binary Coded
Decimal
Binary Coded Decimal

Digit BCD Code Digit BCD Code
0 0000 5 0101
1 0001 6 0110
2 0010 7 0111
3 0011 8 1000
4 0100 9 1001
• Binary coded decimal (BCD) represents each decimal digit with four bits
– Ex. 0011 0010 1001 = 329BCD
3 2 9
• This is NOT the same as 0011001010012
26
Putting It All Together
° BCD not very efficient

° Used in early
computers.
° Used to encode
numbers for seven-
segment displays.
We have only 10
combinations of BCD.
° Easier to read?
The Excess-3 code

The excess-3 code is an important 4-bit code sometimes used with binary-
code decimal (BCD) numbers. To convert any decimal number into its
excess -3 form, add 3 to each decimal digit, and then convert the sum
to a BCD number.
For exemple ,How to convert 12 to an excess-3 number:
First add 3 to each number:
1 2
+3 +3
___ ___
4 5
Second , convertt the sum to BCD form
4 5
0100 0101
So , 0100 0101 in the excee-3 code stands for decimal 12.
27
The excess-3 code
• Take another exemple; convert 29 to an excess-3
2 9
+3 +3
__ __
5 12
0101 1100
After adding 9 and 3, do not carry 1 into the next column; instead, leave
the result intact as 12, and the convert as shown. Therefore :
0101 1100 in the excee-3 code stands for decimal 29.
Gray Code
• Each Gray code number differs from the preceding number by single
bit.
28
Transcoder
ASCII CODES
29
ASCII
• The most commonly used code for representing letters, numerals

and punctuation characters (alphanumeric data)
• Each character is represented with a 7-bit string; for example:
‘3’ = 00110011 (hex 33)
‘ ’ = 00100000 (hex 20)
• An 8-bit extension of ASCII has also been defined
ASCII Code
• American Standard Code for Information Interchange

• ASCII is a 7-bit code, frequently used with an 8th bit for error
detection (more about that in a bit).
Character ASCII (bin) ASCII (hex) Decimal

A 1000001 41 65
B 1000010 42 66
C 1000011 43 67
…
Z
a
…
1
‘
30
ASCII Properties
Q1:
What is relationship between a decimal digit (0, 1, …) and
its ASCII code?
ASCII Properties (2)
Q2:
What is the difference between an upper-case letter
(A, B, …) and its lower-case equivalent (a, b, …)?
31
ASCII Properties (2)
Parity Bit
The ASCII code is used for sending digital data over telephone lines, 1-
bit errors my occur in transmitted data. To catch these errors, a parity
bit is usually transmitted along with the original bits. Then a parity
checker at the receiving end can test for even or add odd parity,
whichever parity has been prearranged between the sender and the
receiver. Since ASCII cide uses 7 bits, the addition of a parity bit to
the transmitted data produces an 8-bit number in this format:
X7X6X5X4X3X2X1X0
Parity bit
Exemple :
A computer sends a message to another computer using an odd-party
bit.Here is the message in ASCII code, plus parity bit :
1100 1000
0100 0101
0100 1100
0100 1100
0100 1111 -Dr. Mohamad Alwan
Logic Circuits 64
32
33
Logic Gates
The Modest Switch
• Manual Switch
• A switch is pushed manually, raised to a high voltage
• Which makes the current flow through the bulb
•Auto Switch or Controllable Switch

• No hands output
input
•High voltage at input: switch on
Otherwise it is off
•Output=Input
34
Using the switch
Input Output is high (voltage) if and only if

the input is high
Output
Now we can make one circuit control

another switch…
Input Output
Lets use them creatively
Input1 Output is high if both the inputs

input1 AND input2 are high
If either of the inputs is low, the
Output output is low.
This is called an AND gate
Input2
Now, can you make an OR gate with

switches?
35
OR Gate
Input1
Output
Input2
Output is low iff both inputs are low
I.e. Output is high if either of the inputs (or both) are

high (input1 OR input2)
Basic Gates
• There are three basic kinds of logic gates
Operation: AND OR of two NOT

of two inputs inputs (complement)
on one input
Logic gate:
36
Describing Circuit Functionality: Inverter
Truth Table
A Y
A Y 0 1
1 0
Symbol
Input Output
• Basic logic functions have symbols.
• The same functionality can be represented with truth tables.
– Truth table completely specifies outputs for all input combinations.
• The above circuit is an inverter.
– An input of 0 is inverted to a 1.
– An input of 1 is inverted to a 0.
The AND Gate
A
Y
B
• This is an AND gate.

• So, if the two inputs signals
Truth Table
are asserted (high) the
output will also be asserted. A B Y
Otherwise, the output will
0 0 0
be deasserted (low).
0 1 0
1 0 0
1 1 1
37
The OR Gate
A
Y
B
• This is an OR gate. A B Y
• So, if either of the two
0 0 0
input signals are
asserted, or both of 0 1 1
them are, the output
1 0 1
will be asserted.
1 1 1
Describing Circuit Functionality: Waveforms
• Waveforms provide another approach for representing functionality.

• Values are either high (logic 1) or low (logic 0).
• Can you create a truth table from the waveforms?
38
Consider three-input gates
3 Input OR Gate
Ordering Boolean Functions
• How to interpret A•B+C?

– Is it A•B ORed with C ?
– Is it A ANDed with B+C ?
• Order of precedence for Boolean algebra: AND before OR.
• Note that parentheses are needed here :
39
Boolean Algebra
• A Boolean algebra is defined as a closed algebraic system containing

two or more elements and the two operators, . and +.
• Useful for identifying and minimizing circuit functionality
• Identity elements
– a+0=a
– a.1=a
• 0 is the identity element for the + operation.
• 1 is the identity element for the . operation.
Commutativity and Associativity of the Operators
• The Commutative Property:

For every a and b in K,
– a+b=b+a
– a.b=b.a
• The Associative Property:
For every a, b, and c in K,
– a + (b + c) = (a + b) + c
– a . (b . c) = (a . b) . c
40
Distributivity of the Operators and Complements
• The Distributive Property:
For every a, b, and c in K,
– a+(b.c)=(a+b).(a+c)
– a.(b+c)=(a.b)+(a.c)
• The Existence of the Complement:
For every a in K there exists a unique element called a’
(complement of a) such that,
– a + a’ = 1
– a . a’ = 0
• To simplify notation, the . operator is frequently omitted. When
two elements are written next to each other, the AND (.) operator
is implied…
– a+b.c=(a+b).(a+c)
– a + bc = ( a + b )( a + c )
Duality
• The principle of duality is an important concept. This says that if an

expression is valid in Boolean algebra, the dual of that expression is
also valid.
• To form the dual of an expression, replace all + operators with .
operators, all . operators with + operators, all ones with zeros, and
all zeros with ones.
• Form the dual of the expression
a + (bc) = (a + b)(a + c)
• Following the replacement rules…
a(b + c) = ab + ac
• Take care not to alter the location of the parentheses if they are
present.
41
Involution
• This theorem states:

a’’ = a
• Remember that aa’ = 0 and a+a’=1.
– Therefore, a’ is the complement of a and a is also the
complement of a’.
– As the complement of a’ is unique, it follows that a’’=a.
• Taking the double inverse of a value will give the initial value.
Absorption
• This theorem states:

a + ab = a a(a+b) = a
• To prove the first half of this theorem:
a + ab = a . 1 + ab
= a (1 + b)
= a (b + 1)
= a (1)
a + ab = a
42
DeMorgan’s Theorem
• A key theorem in simplifying Boolean algebra expression is

DeMorgan’s Theorem. It states:
(a + b)’ = a’b’ (ab)’ = a’ + b’
• Complement the expression

a(b + z(x + a’)) and simplify.
(a(b+z(x + a’)))’ = a’ + (b + z(x + a’))’

= a’ + b’(z(x + a’))’
= a’ + b’(z’ + (x + a’)’)
= a’ + b’(z’ + x’a’’)
= a’ + b’(z’ + x’a)
Additional gates
• We’ve already seen all the basic Boolean operations

and the associated primitive logic gates.
• There are a few additional gates that are often used
in logic design.
– They are all equivalent to some combination of
primitive gates.
– But they have some interesting properties in their
own right.
43
Additional Boolean operations
NAND NOR XOR

Operation:
(NOT-AND) (NOT-OR) (eXclusive OR)
Expressions: (xy)’ = x’ + y’ (x + y)’ = x’ y’ x ⊕ y = x’y + xy’
Truth table: x y (xy)’ x y (x+y)’ x y ⊕y

x⊕
0 0 1 0 0 1 0 0 0
0 1 1 0 1 0 0 1 1
1 0 1 1 0 0 1 0 1
1 1 0 1 1 0 1 1 0
Logic gates:
NAND/OR Gates Illustrations
NAND in the form of AND

NAND
(NOT-AND)
NOR in the form of OR

NOR
(NOT-OR)
44
XOR gates
• A two-input XOR gate outputs true when exactly one of its inputs is
true:
x y ⊕y
x⊕
0 0 0
0 1 1 x ⊕ y = x’ y + x y’
1 0 1
1 1 0
• Several fascinating properties of the XOR operation:
x⊕0=x x ⊕ 1 = x’
x⊕x=0 x ⊕ x’ = 1
x ⊕ (y ⊕ z) = (x ⊕ y) ⊕ z [ Associative ]
x⊕y=y⊕x [ Commutative ]
More XOR tidbits

• The general XOR function is true when an odd number of its arguments
are true.
• For example, we can use Boolean algebra to simplify a three-input XOR
to the following expression and truth table.
x y z x⊕y⊕z
x ⊕ (y ⊕ z) 0 0 0 0
= x ⊕ (y’z + yz’) [ Definition of XOR ] 0 0 1 1
= x’(y’z + yz’) + x(y’z + yz’)’ [ Definition of XOR ] 0 1 0 1
= x’y’z + x’yz’ + x(y’z + yz’)’ [ Distributive ] 0 1 1 0
= x’y’z + x’yz’ + x((y’z)’ (yz’)’) [ DeMorgan’s ]
1 0 0 1
= x’y’z + x’yz’ + x((y + z’)(y’ + z)) [ DeMorgan’s ]
= x’y’z + x’yz’ + x(yz + y’z’) [ Distributive ] 1 0 1 0
= x’y’z + x’yz’ + xyz + xy’z’ [ Distributive ] 1 1 0 0
1 1 1 1
• XOR is especially useful for building adders (as we’ll see on later) and
error detection/correction circuits.
45
XNOR gates
• Finally, the complement of the XOR function is the XNOR function.
• A two-input XNOR gate is true when its inputs are equal:
x ⊕y)’
y (x⊕
0 0 1
0 1 0 (x ⊕ y)’ = x’y’ + xy
1 0 0
1 1 1
Implementation with
one Gate type
92
46
More Gates: NAND - NOR
X Y Z=(XY)’
0 0 1
X
NAND Z F = (XY)’ 0 1 1
Y 1 0 1
1 1 0
X Y Z=(X+Y)’
X 0 0 1
NOR Z F = (X+Y)’
Y 0 1 0
1 0 0
1 1 0
•Sometimes it is desirable to build circuits using NAND gates only or NOR

gates only
NAND Gate is Universal
X X’ X
NOT X’
X
X X XY
AND XY
Y Y
X X X+Y
OR X+Y
Y Y
•Therefore, we can build all functions we learned so far using NAND

gates ONLY (Exercise: Prove that NOT can be built with NAND)
•NAND is a UNIVERSAL gate
47
Implementation using NANDs
•Example: Consider F = AB + CD
A
A
B
F B F
C
C
D
D
Proof:
F = ((AB)’.(CD)’)’
= ((AB)’)’ + ((CD)’)’
= AB + CD
Rules for 2-Level NAND Implementations
1. Simplify the function and express it in sum-of-

products form
2. Draw a NAND gate for each product term (with 2
literals or more)
3. Draw a single NAND gate at the 2nd level (in place
of the OR gate)
4. A term with single literal requires a NOT
What about multi-level circuits?
48
NOR Gate is Universal
X X’ X X’
NOT
X
X X (X’+Y’)’ = XY
AND XY
Y Y
X X (X+Y)’’ = X+Y
OR X+Y
Y Y
•Therefore, we can build all functions we learned so far using NOR

gates ONLY (Exercise: Prove that NOT can be built with NOR)
•NOR is a UNIVERSAL gate
Implementation using NOR gates
•Consider F = (A+B)(C+D)E
NOR
NOR
A A
B B
F F
C C
D D
E E’
49
Rules for 2-Level NOR Implementations
1. Simplify the function and express it in product of

sums form
2. Draw a NOR gate (using OR-NOT symbol) for each
sum term (with 2 literals or more)
3. Draw a single NOR gate (using NOT-AND symbol)
the 2nd level (in place of the AND gate)
4. A term with single literal requires a NOT
What about multi-level circuits?
Normal Form
SOP/POS
50
Overview
• Expressing Boolean functions

• Relationships between algebraic equations, symbols, and truth tables
• Minterms and Maxterms
• AND-OR representations
– Product of sums
– Sum of products
Representation Conversion
• Need a transition between boolean expression, truth table, and

circuit (symbols).
Circuit Boolean
Expression
Truth
Table
51
Normal Form
• A function is said to be in Normal form, if all the terms in the Boolean

function contains all the variables
• Example:
– F(a,b,c)= a’bc+a’b’c+abc  Normal form
– F(a,b,c)= abc+a’c+bc  not in Normal form
• To change to Normal form
• F(a,b,c)= abc+a’c(b+b’)+bc(a+a’)=abc+a’bc+a’b’c+abc+a’bc
=abc+a’bc+a’b’c
Truth Table to Expression
• Converting a truth table to an expression

– Each row with output of 1 becomes a product term
– Sum product terms together.
x y z G Any Boolean Expression can be

0 0 0 0 represented in sum of products form!
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
xyz + xyz’ + x’yz
52
Equivalent Representations of Circuits
• All three formats are equivalent
• Number of 1’s in truth table output column equals AND terms for Sum-of-
Products (SOP)
x y z G
0 0 0 0
x
0 0 1 0 x x
0 1 0 0 x
G
x
0 1 1 1 x
1 0 0 0 x
x x
1 0 1 0
1 1 0 1
1 1 1 1
x y z
G = xyz + xyz’ + x’yz
Reducing Boolean Expressions

• Is this the smallest possible implementation of this expression? No!
• Use Boolean Algebra rules to reduce complexity while preserving
functionality.
• Step 1: Use Theorm 1 (a + a = a)
– So xyz + xyz’ + x’yz = xyz + xyz + xyz’ + x’yz
• Step 2: Use distributive rule a(b + c) = ab + ac
– So xyz + xyz + xyz’ + x’yz = xy(z + z’) + yz(x + x’)
• Step 3: Use Postulate 3 (a + a’ = 1)
– So xy(z + z’) + yz(x + x’) = xy.1 + yz.1
• Step 4: Use Postulate 2 (a . 1 = a)
– So xy.1 + yz.1 = xy + yz = xyz + xyz’ + x’yz
53
Reduced Hardware Implementation
• Reduced equation requires less hardware!
• Same function implemented!
x y z G
0 0 0 0
0 0 1 0 x x
0 1 0 0 G
0 1 1 1
1 0 0 0
1 0 1 0 x
x
1 1 0 1
1 1 1 1
x y z
G = xyz + xyz’ + x’yz = xy + yz
Minterms and Maxterms
• Each variable in a Boolean expression is a literal

• Boolean variables can appear in normal (x) or complement form (x’)
• Each AND combination of terms is a minterm
• Each OR combination of terms is a maxterm
For example: For example:

Minterms Maxterms
x y z Minterm x y z Maxterm
0 0 0 x’y’z’ m0 0 0 0 x+y+z M0
0 0 1 x’y’z m1 0 0 1 x+y+z’ M1
… …
1 0 0 xy’z’ m4 1 0 0 x’+y+z M4
… …
1 1 1 xyz m7 1 1 1 x’+y’+z’ M7
54
Representing Functions with Minterms
• Minterm number same as row position in truth table (starting from top
from 0)
• Shorthand way to represent functions
x y z G
0 0 0 0 G = xyz + xyz’ + x’yz
0 0 1 0
0 1 0 0
0 1 1 1
G = m7 + m6 + m3 = Σm(3, 6, 7)
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Conversion Between SOP and POS Forms
• Easy to convert between minterm and maxterm representations

• For maxterm representation, select rows with 0’s

x y z G
0 0 0 0
0 0 1 0 G = m7 + m6 + m3 = Σ(3, 6, 7)
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0 G = M0M1M2M4M5 = Π(0,1,2,4,5)
1 1 0 1
1 1 1 1
G = (x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)(x’+y+z’)
55
Expression Reduction
Techniques

111
Expression reduction techniques
• 2 reduction techniques
– Algebric reduction technique
– Karnauph Map or K-Map technique

112
56
Algebric Reduction Technique
• Example:
• F(A,B,C)=A’B’C+A’BC+AB’C+ABC
=A’C(B’+B)+AC(B’+B)=A’C+AC=(A’+A)C=C
 NO specific rules for this kind of technique

 Depends on Boolean Algebra Theorems
 Some times, it takes a lot of manipulation to get to
the most reduced function.

113
Karnaugh Map Concept
• K-maps: an alternate approach to representing Boolean functions

• K-map representation can be used to minimize Boolean functions
• Easy conversion from truth table to K-map to minimized SOP
representation.
• Simple rules (steps) used to perform minimization
• Leads to minimized SOP representation.
– Much faster and more efficient than previous minimization techniques
with Boolean algebra.

114
57
2-variable Karnaugh Maps
A B F B
0 1
Example 0 0 0 A
0 1 1 00 1
F(A,B)=AB +A′B +AB ′ 1 0 1
1 1 1 11 1
Rules for K-Maps

• We can reduce functions by circling 1’s in the K-map
+
F=A +B
• Each circle represents minterm reduction
• Every cell containing a 1 must be included at least once.
• The largest possible “power of 2 rectangle” must be
enclosed.
• The 1’s must be enclosed in the smallest possible number
of rectangles.
•

115
3-variable Karnaugh Maps
F(A,B,C)=AB’C’ +AB ′C +ABC +ABC ′ + A’B’C + A’BC’
A B C F
0 0 0 0 BC
0 0 1 1 00 01 11 10
0 1 0 1 A
0 1 1 0 00 1 0 1
1 0 0 1 F=A+B ′C +BC ′
1 0 1 1 11 1 1 1
1 1 0 1
+
1 1 1 1

116
58
Four variable Karnaugh Maps
A B C D f
0 0 0 0 0 CD
0 0 0 1 0 00 01 11 10
0 0 1 0 1
AB
0 0 1 1 0
00 0 0 0 1
0
0
1
1
0
0
0
1
1
1
01 1 1 0 1
0 1 1 0 1 11 1 1 1 1
0 1 1 1 0
+
1
+
0 0 0 1
10 1 0 1 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1 F=BC ′+CD ′+ AC+ AD ′
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

117
Karnaugh maps: Don’t cares
• In some cases, outputs are undefined

• We “don’t care” if the logic produces a 0 or a 1
• This knowledge can be used to simplify functions.
- Treat X’s like either 1’s or 0’s

- Very useful
- OK to leave some X’s uncovered

118
59
Karnaugh maps: Don’t cares
• f(A,B,C,D) = Σ m(1,3,5,7,9) + d(6,12,13)
CD
AB 00 01 11 10 A B C D f
0 0 0 0 0
00 0 1 1 0
0 0 0 1 1
0 0 1 0 0
01 0 1 1 x
0 0 1 1 1
0 1 0 0 0
11 x x 0 0 0 1 0 1 1
10 0 1 1 0 X
0 1 0 0 0 1 1 1 1
+ +
1 0 0 0 0
1 0 0 1 1
F=A’D+C’D 1 0 1 0 0
1 0 1 1 0
1 1 0 0 X
1 1 0 1 X
1 1 1 0 0
1 1 1 1 0

119
More example on Don’t care
CD
00 01 11 10
AB
00 0 1 0 0
01 x x x 1 F=A′C′D+B+AC
11 1 1 1 x
10 x 0 1 1

120
60
Use k-map to find the simplified logic function of outputs. Draw the
logic circuit using AND, OR, NOT gates.
B1B0
B3B2 00 01 11 10
00 0 0 0 0
01 0 1 1 1
11 x x x x
10 1 1 x x
X3=
B1B0
B3B2 00 01 11 10
00 0 1 1 1
01 1 0 0 0
11 x x x x
10 0 1 x x
X2=
61
B1B0
B3B2 00 01 11 10
00 1 0 1 0
01 1 0 1 0
11 X X X X
10 1 0 X X
X1=
B1B0
B3B2 00 01 11 10
00 1 0 0 1
01 1 0 0 1
11 X X X X
10 1 0 X X
X0=
• X3=B3+B2B0+B21
• X2=B2B1’B0’+B2’B0+B1B3’B2’
• X3=B1’B0’+B1B0
• X4=B1’B0’+B1B0’
62
B1B0 00 01 11 10
A1A0
00 0 0 0 0
01 1 0 0 0 G=A1.B1’+A0.B1’B0’+A1A0.B0’
11 1 1 0 1
10 1 1 0 0
B1B0
A1A0 00 01 11 10
S=A1’B1+A1’A0’B0+ A0’B1B0
00 0 1 1 1
01 0 0 1 1
11 0 0 0 0
10 0 0 1 0
B1B0 00 01 11 10
A1A0
00 1 0 0 0 E=A1’A0’B1’B0’+A1’A0B1’B0+A1A0B1B0+A1A0’B1B0’
01 0 1 0 0
11 0 0 1 0
10 0 0 0 1 Logic Circuits -Dr. Mohamad Alwan 126
63
Multiplexer/De-multiplexer

127
Multiplexers
• Multiplexers, or muxes, are used to choose between resources.
• A real-life example: in the old days before networking, several
computers could share one printer through the use of a switch.

128
64
Rotary Switch
C0
C1
Y
C2
C3

129
Rotary Switch
C0
C1
Y
C2
C3

130
65
Rotary Switch
C0
C1
Y
C2
C3

131
Rotary switch
C0
C1
Y
C2
C3

132
66
Multiplexers
n n
• A 2 -to-1 multiplexer sends one of 2 input lines to a single output line.
– A multiplexer has two sets of inputs:
• 2n data input lines
• n select lines, to pick one of the 2n data inputs
– The mux output is a single bit, which is one of the 2n data inputs.

133
Multiplexers
4x1
MUX
C0 s1 s0 Y
C1 0 0 C0
Y 0 1 C1
C2 1 0 C2
C3 1 1 C3
s1 s0
A multiplexer is a
0 0
digital switch (automatic switch)

134
67
Multiplexers
4x1
MUX
s1 s0 Y
C0
C1 0 0 C0
Y 0 1 C1
C2 1 0 C2
C3 1 1 C3
s1 s0
0 1

135
Multiplexers
4x1
MUX
s1 s0 Y
C0
C1 0 0 C0
Y 0 1 C1
C2 1 0 C2
C3 1 1 C3
s1 s0
1 0

136
68
Multiplexers
4x1
MUX
s1 s0 Y
C0
C1 0 0 C0
Y 0 1 C1
C2 1 0 C2
C3 1 1 C3
s1 s0
1 1

137
A 4-to-1 multiplexer
• Here is a block diagram and abbreviated truth table for a 4-to-1 mux.
S1 S0 Q
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Q = S1’ S0’ D0 + S1’ S0 D1 + S1 S0’ D2 + S1 S0 D3

138
69
4-to-1 MUX Logic Diagram
S1
S0
D0
D1
Q
D2
D3
Implementing functions with multiplexers

• Muxes can be used to implement arbitrary functions.
n
• One way to implement a function of n variables is to use an 2 -to-1 mux:
– For each minterm mi of the function, connect 1 to mux data input Di.
Each data input corresponds to one row of the truth table.
– Connect the function’s input variables to the mux select inputs.
These are used to indicate a particular input combination.
• For example, let’s look at f(x,y,z) = Σm(1,2,6,7).
x y z f
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
140
70
A more efficient way
• We can actually implement f(x,y,z) = Σm(1,2,6,7) with x y z f
just a 4-to-1 mux, instead of an 8-to-1.
0 0 0 0
• Step 1: Find the truth table for the function, and 0 0 1 1
group the rows into pairs. Within each pair of rows, x
0 1 0 1
and y are the same, so f is a function of z only.
0 1 1 0
– When xy=00, f=z 1 0 0 0
– When xy=01, f=z’ 1 0 1 0
– When xy=10, f=0
1 1 0 1
– When xy=11, f=1
1 1 1 1
• Step 2: Connect the first two input variables of the
truth table (here, x and y) to the select bits S1 S0 of
the 4-to-1 mux.
• Step 3: Connect the equations above for f(z) to the

data inputs D0-D3.

141
Rotary switch/Demultiplexers
Y0
Y1
YIN
Y2
Y3

142
71
Rotary Switch/Demultiplexers
Y0
Y1
YIN
Y2
Y3

143
Y0
Y1
YIN
Y2
Y3

144
72
Y0
Y1
YIN
Y2
Y3

145
Digital or Automatic De-multiplexers
S1 S0 Y0 Y1 Y2 Y3
Y0
1x4 Y1 0 0 YIN 0 0 0
YIN DeMUX 0 1 0 YIN 0 0
Y2 1 0 0 0 YIN 0
Y3 1 1 0 0 0 YIN
S1 S0

146
73
Demultiplexers
1x4
DeMUX
S1 S0 Y0 Y1 Y2 Y3
Y0
Y1 0 0 YIN 0 0 0
YIN 0 1 0 YIN 0 0
Y2 1 0 0 0 YIN 0
Y3 1 1 0 0 0 IN
S1 S0
0 0

147
Demultiplexers
1x4
DeMUX
S1 S0 Y0 Y1 Y2 Y3
Y0
Y1 0 0 YIN 0 0 0
YIN 0 1 0 YIN 0 0
Y2 1 0 0 0 YIN 0
Y3 1 1 0 0 0 YIN
S1 S0
0 1

148
74
Demultiplexers
1x4
DeMUX
S1 S0 Y0 Y1 Y2 Y3
Y0
Y1 0 0 YIN 0 0 0
YIN 0 1 0 YIN 0 0
Y2 1 0 0 0 YIN 0
Y3 1 1 0 0 0 YIN
S1 S0
1 0

149
Demultiplexers
1x4
DeMUX
S1 S0 Y0 Y1 Y2 Y3
Y0
Y1 0 0 YIN 0 0 0
YIN 0 1 0 YIN 0 0
Y2 1 0 0 0 YIN 0
Y3 1 1 0 0 0 YIN
S1 S0
1 1

150
75
Demultiplexers
S1 S0 Y0 Y1 Y2 Y3
0 0 YIN 0 0 0
Y0 0 1 0 YIN 0 0
1x4 Y1 1 0 0 0 YIN 0
YIN DeMUX 1 1 0 0 0 YIN
Y2
Y3
Y0 = YIN S1’ S0'
S1 S0 Y1 = YIN S1’ S0
Y2 = YIN S1 S0’
Y3 = YIN S1 S0

151
1-to-4 De-MUX Logic Diagram

S1
S0
YI
N
Y0
Y1
Y2
Y3
76
Mux-DeMux Combination (Communication Application)
C0 Y0
C1 4x 1 Y YIN 1x 4 Y1
MUX DeMUX
C2 Y2
C3 Y3
s1 s0 d1 d0

153
4x1 1x4
MUX DeMUX
C0 Y0
C1 Y YIN Y1
C2 Y2
C3 Y3
s1 s0
0 0

154
77
4x1 1x4
MUX DeMUX
C0 Y0
C1 Y YIN Y1
C2 Y2
C3 Y3
s1 s0
0 1

155
4x1 1x4
MUX DeMUX
C0 Y0
C1 Y YIN Y1
C2 Y2
C3 Y3
s1 s0
1 0

156
78
4x1 1x4
MUX DeMUX
C0 Y0
C1 Y YIN Y1
C2 Y2
C3 Y3
s1 s0
1 1

157
What a decoder does

n n
• A n-to-2 decoder takes an n-bit input and produces 2 outputs. The n
n
inputs represent a binary number that determines which of the 2
outputs is uniquely true.
• A 2-to-4 decoder operates according to the following truth table.
– The 2-bit input is called S1-S0, and the four outputs are Q0-Q3.
– If the input is the binary number i, then output Qi is uniquely true.
S1 S0 Q0 Q1 Q2 Q3
S1 Decoder Q0
0 0 1 0 0 0
2-to-4 Q1
0 1 0 1 0 0
S0 Q2
1 0 0 0 1 0
Q3
1 1 0 0 0 1
• For instance, if the input S1 S0 = 10 (decimal 2), then output Q2 is

true, and Q0, Q1, Q3 are all false.
• This circuit “decodes” a binary number into a “one-of-four” code.

158
79
How can you build a 2-to-4 decoder?
• Follow the design procedures from last time! We have a truth table, so
we can write equations for each of the four outputs (Q0-Q3), based on
the two inputs (S0-S1).
S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
• In this case there’s not much to be simplified. Here are the equations:
Q0 = S1’ S0’
Q1 = S1’ S0
Q2 = S1 S0’
Q3 = S1 S0

159
A picture of a 2-to-4 decoder
S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

160
80
Enable inputs
• Many devices have an additional enable input, which is used to “activate”
or “deactivate” the device.
• For a decoder,
– EN=1 activates the decoder, so it behaves as specified earlier.
Exactly one of the outputs will be 1.
– EN=0 “deactivates” the decoder. By convention, that means all of
the decoder’s outputs are 0.
• We can include this additional input in the decoder’s truth table:
EN S1 S0 Q0 Q1 Q2 Q3
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

161
An aside: abbreviated truth tables

• In this table, note that whenever EN S1 S0 Q0 Q1 Q2 Q3
EN=0, the outputs are always 0, 0 0 0 0 0 0 0
regardless of inputs S1 and S0.
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
• We can abbreviate the table by EN S1 S0 Q0 Q1 Q2 Q3

writing x’s in the input columns 0 x x 0 0 0 0
for S1 and S0.
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

162
81
Blocks and abstraction
• Decoders are common enough that we want to encapsulate them and
treat them as an individual entity.
• Block diagrams for 2-to-4 decoders are shown here. The names of the
inputs and outputs, not their order, is what matters.
Q0 = S1’ S0’
Q1 = S1’ S0
Q2 = S1 S0’
Q3 = S1 S0
• A decoder block provides abstraction:

– You can use the decoder as long as you know its truth table or
equations, without knowing exactly what’s inside.
– It makes diagrams simpler by hiding the internal circuitry.
– It simplifies hardware reuse. You don’t have to keep rebuilding the
decoder from scratch every time you need it.
• These blocks are like functions in programming!

163
A 3-to-8 decoder
• Larger decoders are similar. Here is a 3-to-8 decoder.
– The block symbol is on the right.
– A truth table (without EN) is below.
– Output equations are at the bottom right.
• Again, only one output is true for any input combination.
S2 S1 S0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0 Q0 = S2’ S1’ S0’
0 0 1 0 1 0 0 0 0 0 0 Q1 = S2’ S1’ S0
0 1 0 0 0 1 0 0 0 0 0 Q2 = S2’ S1 S0’
0 1 1 0 0 0 1 0 0 0 0 Q3 = S2’ S1 S0
1 0 0 0 0 0 0 1 0 0 0 Q4 = S2 S1’ S0’
1 0 1 0 0 0 0 0 1 0 0 Q5 = S2 S1’ S0
1 1 0 0 0 0 0 0 0 1 0 Q6 = S2 S1 S0’
1 1 1 0 0 0 0 0 0 0 1 Q7 = S2 S1 S0

164
82
A variation of the standard decoder
• The decoders we’ve seen so far are active-high decoders.
EN S1 S0 Q0 Q1 Q2 Q3
0 x x 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
• An active-low decoder is the same thing, but with an inverted EN input

and inverted outputs.
EN’ S1’ S0’ Q0’ Q1’ Q2’ Q3’

0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 x x 1 1 1 1

165
Implementing Functions Using Decoders
• Example:
S(x, y, z) = Σ (1,2,4,7) x y z C S
0 0 0 0 0
C(x, y, z) = Σ (3,5,6,7) 0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
3-to-8 0
Decode 1 S
r 2
x S2 3
y S1 4
5 C
z S0 6
7

166
83
Active-low decoder example
• So we can use active-low decoders to implement arbitrary functions
too, but as a product of maxterms.
• For example, here is an implementation of the function,
f(x,y,z) = ΠM(4,5,7), using an active-low decoder.
• The “ground” symbol connected to EN represents logical 0, so this

decoder is always enabled.
• Remember that you need an AND gate for a product of sums.

167
Encoders
I0 I0 I1 I2 I3 B A
I1 4-to-2 A
Encoder 1 0 0 0 0 0
I2 B 0 1 0 0 0 1
I3 0 0 1 0 1 0
0 0 0 1 1 1

168
84
Encoders
Assume only 1 input

can be high at any time. I0 I1 I2 I3 B A
1 0 0 0 0 0
A = I1 + I3 0 1 0 0 0 1
B = I2 + I3 0 0 1 0 1 0
I0 0 0 0 1 1 1
I1
A = I1 + I3
I2
I3
B = I2 + I3

169
8-to-3 Encoder
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Y2 = I7 + I6 + I5 + I4
Y1 = I7 + I6 + I3 + I2
Y0 = I7 + I5 + I3 + I1
170
85
Half-Adder and Full-Adder
Half-Adder and Full-Adder
• Arithmetic is the most basic thing you can do with a computer, but it’s
not as easy as you might expect!
• These next few lectures focus on addition, subtraction, multiplication
and arithmetic-logic units, or ALUs, which are the “heart” of CPUs.
• ALUs are a good example of many of the issues we’ve seen so far,
including Boolean algebra, circuit analysis, data representation, and
hierarchical, modular design.

172
86
Binary addition by hand
• You can add two binary numbers one column at a time starting from the
right, just as you add two decimal numbers.
• But remember that it’s binary. For example, 1 + 1 = 10 and you have to
carry!
The initial carry
in is implicitly 0
1 1 1 0 Carry in
1 0 1 1 Augend
+ 1 1 1 0 Addend
1 1 0 0 1 Sum
most significant least significant

bit, or MSB bit, or LSB

173
Adding two bits

• We’ll make a hardware adder by copying the human addition algorithm.
• We start with a half adder, which adds two bits and produces a two-bit
result: a sum (the right bit) and a carry out (the left bit).
• Here are truth tables, equations, circuit and block symbol.
X Y C S
0 0 0 0 0 +0 =0
0 1 0 1 0 +1 =1
1 0 0 1 1 +0 =1
1 1 1 0 1 +1 = 10
C = XY
S = X’ Y + X Y’
=X⊕Y

174
87
Full adder equations
• A full adder circuit takes three bits of input, and produces a two-bit
output consisting of a sum and a carry out.
• Using Boolean algebra, we get the equations shown here.
– XOR operations simplify the equations a bit.
– We used algebra because you can’t easily derive XORs from K-maps.
X Y C in C out S S = Σm(1,2,4,7)
0 0 0 0 0
= X’ Y’ Cin + X’ Y Cin’ + X Y’ Cin’ + X Y Cin
= X’ (Y’ Cin + Y Cin’) + X (Y’ Cin’ + Y Cin)
0 0 1 0 1
= X’ (Y ⊕ Cin) + X (Y ⊕ Cin)’
0 1 0 0 1
= X ⊕ Y ⊕ Cin
0 1 1 1 0
1 0 0 0 1 Cout = Σm(3,5,6,7)
1 0 1 1 0 = X’ Y Cin + X Y’ Cin + X Y Cin’ + X Y Cin
1 1 0 1 0 = (X’ Y + X Y’) Cin + XY(Cin’ + Cin)
1 1 1 1 1 = (X ⊕ Y) Cin + XY

175
Full adder circuit

• These things are called half adders and full adders because you can
build a full adder by putting together two half adders!
S = X ⊕ Y ⊕ Cin
Cout = (X ⊕ Y) Cin + XY

176
88
A 4-bit adder
• Four full adders together make a 4-bit adder.
• There are nine total inputs:
– Two 4-bit numbers, A3 A2 A1 A0 and B3 B2 B1 B0
– An initial carry in, CI
• The five outputs are:
– A 4-bit sum, S3 S2 S1 S0
– A carry out, CO
• Imagine designing a nine-input adder without this
hierarchical structure—you’d have a 512-row truth
table with five outputs!

177
An example of 4-bit addition

• Let’s try our initial example: A=1011 (eleven), B=1110 (fourteen).
1 1 1 0 1 1 0 1
0
1 1 0
1 1 0 0 1
1. Fill in all the inputs, including CI=0

2. The circuit produces C1 and S0 (1 + 0 + 0 = 01)
3. Use C1 to find C2 and S1 (1 + 1 + 0 = 10)
4. Use C2 to compute C3 and S2 (0 + 1 + 1 = 10)
5. Use C3 to compute CO and S3 (1 + 1 + 1 = 11)
Woohoo! The final answer is 11001 (twenty-five).

178
89
Overflow
• In this case, note that the answer (11001) is five bits long, while the
inputs were each only four bits (1011 and 1110). This is called overflow.
• Although the answer 11001 is correct, we cannot use that answer in any
subsequent computations with this 4-bit adder.
• For unsigned addition, overflow occurs when the carry out is 1.

179
Hierarchical adder design

• When you add two 4-bit numbers the carry in is always 0, so why does
the 4-bit adder have a CI input?
• One reason is so we can put 4-bit adders together to make even larger
adders! This is just like how we put four full adders together to make
the 4-bit adder in the first place.
• Here is an 8-bit adder, for example.

180
90
Comparator

181
Comparator
• The comparison of two numbers Truth table
– outputs: A>B, A=B, A<B A1 A0 B1 B0 E G L
– 2-bit numbers 0 0 0 0 1 0 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 0 1 0
A1
A0 A<B 0 1 0 1 1 0 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
Comparator A=B 1 0 0 0 0 1 0
B1 1 0 0 1 0 1 0
B0 A>B 1 0 1 0 1 0 0
1 0 1 1 0 0 1
1 1 0 0 0 1 0
1 1 0 1 0 1 0
1 1 1 0 0 1 0
1 1 1 1 1 0 0
91
K-MAP
B1B0
00 01 11 10 E=A1’A0’B1’B0’+A1’A0B1’B0+A1A0B1B0+A1A0’B1B0’
A1A0
00 1 0 0 0 =A1’B1’(A0’B0’+A0B0)+A1B1(A0B0+A0’B0’)
01 0 1 0 0 =(A1’B1’+A1B1)(A0’B0’+A0B0)
11 0 0 1 0 =(A1(+)B1)’ (A0(+)B0)’
10 0 0 0 1 = ((A1(+)B1)+(A0(+)B0))’
B1B0
00 01 11 10 B1B0
A1A0 00 01 11 10
A1A0
00 0 0 0 0 00 0 1 1 1
01 1 0 0 0 01 0 0 1 1
11 1 1 0 1 11 0 0 0 0
10 1 1 0 0 10 0 0 1 0
G=A1B1’+A0B1’B0’+A1A0B0’ L=A1’B1+A1’A0’B0+A0’B1B0

183
Magnitude Comparison
• Hardware chips
92
8-bit Comparator
A0
.
A3
7485
B0
.
In out
B3 A>B
A>B A<B
A<B
A=B
A=B
A>B
A<B
A>B
A=B
A<B
A4
A=B
.
A7 In out
B4
. 7485
B7

185
Seven Segment Displays

186
93
Seven Segment Displays
This presentation will demonstrate how

• A seven-segment display can be used to display the
decimal numbers 0-9 and some alpha characters.
• A common anode seven-segment display works.
• A common cathode seven-segment display works.
• To select the resistor value for a seven-segment
display.
Retro
LED Watch
(Circa 1970s)
Segment Identification
• A Seven-Segment Display (SSD) is simply a figure eight

grouping of LEDs {some include a decimal point (DP)}.
• Each Segment is labeled (a) thru (g).
• SSDs are available in two configurations
– Common Cathode (all LED cathodes are connected)
– Common Anode (all LED anodes are connected)
a
f b
g
e c

d dp
94
SSD Display Possibilities
Decimal Digits 0-
9
Select Alpha Characters
Simple Messages
Basic LED Operations
To understand how a seven-segment display works, we

must review how an LED works.
To Turn an LED ON . . .
• The ANODE must be at a
higher voltage potential (∼1.5v)
than the CATHODE.
• The amount of current flowing
through the LED will determine
CATHODE (‒) (+) ANODE
the brightness of the LED.
• The amount of current is
← Current Flow
controlled by a series resistor.
(not shown)
95
7-Segment Display (Common Anode display)
a
+5v
f b
g
e c a b c d e f g

191
7-Segment Display (Common Cathode display)
a b c d e f g
f b
g
e c

192
96
BCD 7-Segment Display
a
wxyz a b c d e f g
0 0000 1 1 1 1 1 1 0
f b 1 0001 0 1 1 0 0 0 0
2 0010 1 1 0 1 1 0 1
g
3 0011 1 1 1 1 0 0 1
4 0100 0 1 1 0 0 1 1
5 0101 1 0 1 1 0 1 1
e c 6 0110 1 0 1 1 1 1 1
7 0111 1 1 1 0 0 0 0
8 1000 1 1 1 1 1 1 1
d 9 1001 1 1 1 1 0 1 1
A 1010 x x x x x x x
b 1011 x x x x x x x
Using common
C 1100 .
cathode display d 1101 .
E 1110 .
F 1111 x x x x x x x

193
K-Map
yz
wx
00 01 11 10 a=y+w+xz+x’z’
00 1 0 1 1
01 0 1 1 1 b=w+x’+y’z’+yz
11 x x x x
10 1 1 x x c=y’+z+x
d=xy’z+w+x’z’+yz’+x’y
e=yz’+x’z’
f=w+y’z’+xy’+xz’
g=w+xy’+x’y+yz’
194
97
Flip Flops

195
Combinational vs. Sequential
• Combinational Logic Circuit

– output depends only on current inputs
• ex: adder always generates sum and carry,
regardless of previous inputs
• Sequential Logic Circuit
– Next output depends on present output as well as the present
inputs
– stores information (state) from past inputs using feedback
loops

196
98
Sequential logic elements
• Flip-flops: Building blocks of sequential logic circuits

• Useful for building “memory” elements
– can retain outputs even when inputs change

197
What exactly is memory?

• A memory should have at least three properties.
1. It should be able to hold a value.

2. You should be able to read the value that was saved.
3. You should be able to change the value that’s saved.
• We’ll start with the simplest case, a one-bit memory.
1. It should be able to hold a single bit, 0 or 1.

2. You should be able to read the bit that was saved.
3. You should be able to change the value. Since there’s only a single
bit, there are only two choices:
– Set the bit to 1
– Reset, or clear, the bit to 0.

198
99
SR Latch – NOR form
• Let’s use NOR gates . The SR latch below has two inputs S and R, which
will let us control the outputs Q and Q’.
• Here Q and Q’ feed back into the circuit. They’re not only outputs,
they’re also inputs!
• To figure out how Q and Q’ change, we have to look at not only the
inputs S and R, but also the current values of Q and Q’:
Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’
• Let’s see how different input values for S and R affect this thing.

199
SR Latch Representation
S R Q+
0 0 Q( no Reduced
change Characteristic Table
0 1 0 or
(reset)
Summarized state
1 0 1(set) transition table
Qnext = (R + Q’current)’
1 1 invalid
Q’next = (S + Qcurrent)’
S R Q Q+
0 0 0 0 Characteristic Table
or Timing Diagram
0 0 1 1
0 1 0 0 state transition table
S
0 1 1 0
R
1 0 0 1
1 0 1 1 Q
1 1 0 NV Equation of Q+ :
Q’
1 1 1 NV Q+=S+R’Q

200
100
SR latch using NAND Gates
• Latch made from cross-coupled NANDs

• Sometimes called S’-R’ latch
• Usually S=1 and R=1
• S=0 and R=0 generates unpredictable results
S’ R’ Q+
Timing Diagram 1 1 Q(No change)
1 0 0 (reset)
S 0 1 1 (set)
0 0 Avoid!
R
Q’

201
An SR latch with a control input

• Here is an SR latch with a control input C.
C S R S’ R’ Q
0 x x 1 1 No change
1 0 0 1 1 No change
1 0 1 1 0 0 (reset)
1 1 0 0 1 1 (set)
1 1 1 0 0 Avoid!
• Notice the hierarchical design!

– The dotted blue box is the S’R’ latch from the previous slide.
– The additional NAND gates are simply used to generate the correct
inputs for the S’R’ latch.
• The control input acts just like an enable.

202
101
Clocks and synchronization
• A clock is a special device that whose output continuously alternates
between 0 and 1.
clock period
• The time it takes the clock to change from 1 to 0 and back to 1 is called
the clock period, or clock cycle time.
• The clock frequency is the inverse of the clock period. The unit of
measurement for frequency is the hertz.
• Clocks are often used to synchronize circuits.
– They generate a repeating, predictable pattern of 0s and 1s that
can trigger certain events in a circuit, such as writing to a latch.
– If several circuits share a common clock signal, they can coordinate
their actions with respect to one another.
• This is similar to how humans use real clocks for synchronization.

203
Clock Edge
• Positive Edge or • Negative Edge or

• Rising edge • Falling edge
Lo-
Lo-Hi edge Hi
Hi--Lo edge

204
102
Positive Edge-triggered J-K Flip Flop
• Modified SR flip flop (both input could be on @ the same time)

• Two data inputs, J and K
• J -> set, K -> reset, if J=K=1 then toggle output
Characteristic Table

205
Negative Edge-triggered J-K Flip Flop
J
Q
CLK
Hi
Hi--Lo edge Q’
K

206
103
Asynchronous Inputs
• J, K are synchronous inputs

o Effects on the output are synchronized with the CLK input.
• Asynchronous inputs operate independently of the synchronous
inputs and clock
o Set the FF to 1/0 states at any time.

207
Positive edge-triggered D Flip-Flop
• Stores a value on the positive edge of C

• Input changes at other times have no effect on output

208
104
Positive and Negative Edge D Flip-Flop
• D flops can be triggered on positive or negative edge
• Bubble before Clock (C) input indicates negative edge trigger
Lo-
Lo-Hi edge Hi
Hi--Lo edge
209
Positive Edge-Triggered T Flip-Flop
T Q+
CLK
0 Q(no change)
T
1 Toggle
Q

210
105
Asynchronous Counters
Overvie
w
• Counters are important components in computers

– The increment or decrement by one in response to input
• Two main types of counters
– Ripple (asynchronous) counters
– Synchronous counters
• Ripple or Asynchronous counters
– Flip flop output serves as a source for triggering other flip flops
• Synchronous counters
– All flip flops triggered by a clock signal
• Synchronous counters are more widely used in industry.

212
106
Asynchronous Counters
• Counter: A register that goes through a prescribed series of states

• Binary counter
– Counter that follows a binary sequence
– N bit binary counter counts in binary from 0 to 2n -1
• Ripple counters triggered by initial Count signal
• Applications:
– Watches
– Clocks
– Alarms
– Web browser refresh

213
2-bit Asynchronous
Counter
J and K inputs
are always tied
together to form
the T Flip Flop
107
4-bit Asynchronous Ripple
Counter

215
Down
counters
• The counters we have seen so far are up-counters. The falling edge
Flip-Flops makes them count up.
• If we use rising edge Flip-Flops, the counter would be a down
counter.
• H.W.: Design a down counter that counts from 7(111) to 0(000)

216
108
Other Names for Ripple

Counters
• 2- bit counters counts 0-3 called:

– modulo-4 or
– divide-by-4
– modulo-8 or
– divide-by-8
– modulo-16 or
– divide-by-16

218
109
Timing Consideration
• Timing Diagram shows state transitions occurring exactly on
the falling edge of the clock. This is not true. It takes time
for the Flip-Flop to change state (say 40ns)
• Changing from state 00  01 would need to change 1 bit or
time delay=40ns.
• Changing from state 01  10 would need to change 2 bits or
time delay=80ns
• Since each Flip-Flop does not change state on a common
clock, and switching delay is incurred as the clock signal
ripples thru the string of Flip-Flops. This kind of counters is
called CAsynchronous ripple counter.
40ns Qa
Qb
80ns
219
Glitches & Decoding

Spikes
• For Ripple counters, switching from state to state causes
multiple states to exist for an increment of 40 ns each.
Those glitches or spikes states are called intermediate
states.
• Example for 4-bit counter going from 15 to 0 11110000:
C
1 0 0 0 0
Qa
Qb 1 1 0 0 0
Qc 1 1 1 0 0
Qd 1 1 1 1 0
15 14 12 8 0

220
110
Modifying the count
sequence
What if we need a divide-by-5 counter; A counter that counts

from 0 to 4 and reset at number 5.
000  001  010  011  100  reset(101)  000  …etc
Reset Delay:
•Change state
from 100101
takes 40ns
•Switch for
NAND takes
10ns
•Clear Flip-Flops
takes 40ns
•Total:40+10+40=
90ns Logic Circuits -Dr. Mohamad Alwan
221
111
Synchronous Counters
112
Synchronous Counters
• Unlike Asynchronous ripple counters, Synchronous counters are based

on a common clock. That means all Flip-Flops change state off a common
clock signal. Therefore all Flip-Flops change state at the same time and
thus eliminates delays and glitches.
• To aid in the design of a synchronous counters, two new tools of
sequential circuits behavior illustrations are introduced.
– State diagrams
– Transition or excitation tables

225
State Diagram
1
0
2
7
6 3
4
5

226
113
Excitation tables
Present Next
State state Inputs
Q(t) Q(t+1) D
0 0 0
0 1 1
1 0 0
1 1 1
Present Next
State state Inputs
Q(t) Q(t+1) J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0

227
3-bit Synchronous Counters using J-K flip-flops

• We can now use the JK excitation table to find the correct
values for each flip-flop’s inputs, based on its present and next
states.
Present State Next State Inputs
Qc Qb Qa Qc Qb Qa Jc Kc Jb Kb Ja Ka
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
114
3-bit counter - Continued
Qb Qa
Qb Qa
Qc 00 01 11 10
Qc 00 01 11 10
0 0 0 1 0 0 x x x x
1 x x x x 1 0 0 1 0
Jc=Qb Qa Kc=Qb Qa
Qb Qa
Qb Qa
Qc 00 01 11 10
Qc 00 01 11 10
0 0 1 x x
0 x x 1 0
1 0 1 x x
1 x x 1 0
Jb= Qa
Kb= Qa
3-bit counter - Continued
Qb Qa
Qb Qa
Qc 00 01 11 10
Qc 00 01 11 10
0 1 X x 1
0 x 1 1 X
1 1 x x 1
1 x 1 1 x
Ja= 1
Ka= 1
115
Logic Circuit
Qa
Qc Jc Qb Jb Qa Ja
C
Qc‘ Kc Qb‘ Kb Qa ‘ Ka

231
State Sequencer
Synchronous counters is simply a state sequencer with numerically

ascending state sequence.
Assume that the sequence shown in the following state diagram needs
to be generated:
1
0

232
116
Sequencer Continued…
states.
Qc Qb Qa Qc Qb Qa Jc Kc Jb Kb Ja Ka
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 1 0 0 1 X X 1 0 X
1 0 0 1 1 1 X 0 1 X 1 X
1 1 1 0 0 0 X 1 X 1 X 1
Sequencer - Continued
Qb Qa
Qb Qa
Qc 00 01 11 10
Qc 00 01 11 10
0 0 0 x 1 0 x x x x
1 x x x x 1 0 x 1 X
Jc=Qb Kc=Qb
Qb Qa
Qb Qa
Qc 00 01 11 10
Qc 00 01 11 10
0 0 1 x x
0 x x x 1
1 1 X x x
1 x x 1 X
Jb= Qa+Qc
Kb= 1
117
Sequencer - Continued
Qb Qa
Qb Qa
Qc 00 01 11 10
Qc 00 01 11 10
0 1 X x 0
0 x 1 X X
1 1 x x X
1 x X 1 x
Ja= Qb’
Ka= 1
Sequencer - Logic Circuit
Qc Jc Qb Jb Qa Ja
C
Qc‘ Kc Qb‘ Kb 1 Qa ‘ Ka
1

236
118
Unused states
• sometimes you may have unused, leftover states

• To get the safest possible circuit, you can explicitly fill in next states for the
unused states.
• This guarantees that even if the circuit somehow enters an unused state, it
will eventually end up in a valid state.
• This is called a self-starting counter
• Unused states :3, 5, and 6
0 1
2
7
4
Unused states
Present J inputs K inputs Q Next

state State
Qc 0 Jc=Qb=1 Kc=Qb=1 Toggle 1
Qb 1 Jb=Qa+Q Kb=1 Toggle 0
c=1
Qa 1 Ja=Qb’=0 Ka=1 Reset 0
3 4
0 1
2
7
4 3
119
Unused states - continued

state State
Qc 1 Jc=Qb=0 Kc=Qb=0 N/C 1
c=1
Qa 1 Ja=Qb’=1 Ka=1 toggle 0
5 6
0 1
5 2
6
7
4 3
Unused states - continued

state State
Qc 1 Jc=Qb=1 Kc=Qb=1 Toggle 0
c=1
Qa 0 Ja=Qb’=0 Ka=1 Reset 0
6 0
0 1
5 2
6
7
4 3
120
State Sequencer with External Control
1
0 3
0
x
x
0 1
2 5
1 4
x x

241
State Sequencer with external control - Continued

states.
y Qc Qb Qa Qc Qb Qa Jc Kc Jb Kb Ja Ka
0 0 0 0 0 0 1 0 X 0 X 1 X
X 0 0 1 0 1 0 0 X 1 X X 1
X 0 1 0 0 0 0 0 X X 1 0 X
1 0 0 0 0 1 1 0 X 1 X 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
X 1 0 0 1 0 1 X 0 0 X 1 X
X 1 0 1 0 1 1 X 1 1 X X 0
0 0 1 1 0 0 0 0 X X 1 X 1
121
Qb Qa
Qb Qa
Y Qc 00 01 11 10
Y Qc 00 01 11 10
00 0 0 0 0
00 x x x x
01 x x x x
01 0 1 x x
11 x x x x
11 0 1 x x
10 0 0 1 0
10 X X X X
Jc=Y Qb Qa
Kc= Qa
Qb Qa
Qb Qa
Y Qc 00 01 11 10
Y Qc 00 01 11 10
00 0 1 x x
00 x x 1 x
01 0 1 x x
01 x x x 1
11 0 1 x x
11 x x x X
10 1 1 X X
10 X X 1 1
Jb= Qa+Y Qc’

Kb= 1
122
Qb Qa
Qb Qa
Y Qc 00 01 11 10
Y Qc 00 01 11 10
00 1 x x 0
00 x 1 1 x
01 1 x x x
01 x 0 x x
11 1 x x x
11 x 0 x x
10 1 X 1 0
10 X 1 1 X
Ja= Qb’+ Qa
Ka= Qc’
Logic Circuit
Y
Qc Jc Qb Jb Qa Ja
C
Qc‘ Kc Qb‘ Kb Qa ‘ Ka
1

246
123

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Digital Computer Systems

• Digital systems consider discrete amounts of data.

Logic Circuits -Dr. Mohamad Alwan 1

Understanding Decimal Numbers

• Decimal numbers are made of decimal digits: (0,1,2,3,4,5,6,7,8,9)

Logic Circuits -Dr. Mohamad Alwan 2

• Binary numbers are made of binary digits (bits):

Logic Circuits -Dr. Mohamad Alwan 3

Conversion Between Number Bases

Decimal(base 10) Binary(base 2)

Logic Circuits -Dr. Mohamad Alwan 4

(1 x 102) + (6 x 101) + (2 x 100) + (3 x 10-1) + (7 x 10-2) + (5 x 10-3) = 162.375

Logic Circuits -Dr. Mohamad Alwan 5

Converting binary to decimal

– The decimal value is:

(1 x 23) + (1 x 22) + (0 x 21) + (1 x 20) + (0 x 2-1) + (1 x 2-2) =

Powers of 2: Useful abbreviations:

Logic Circuits -Dr. Mohamad Alwan 6

162 / 2 = 81 rem 0 0.375 x 2 = 0.750

• So, 162.37510 = 10100010.0112

Logic Circuits -Dr. Mohamad Alwan 7

Base 16 is useful too

Logic Circuits -Dr. Mohamad Alwan 8

10110100.0010112 = 1011 0100 . 0010 11002

Hex Binary Hex Binary Hex Binary Hex Binary

Logic Circuits -Dr. Mohamad Alwan 9

This time, the weights are powers of 16.

Integer Part: Divide by the base,

Logic Circuits -Dr. Mohamad Alwan 11

Logic Circuits -Dr. Mohamad Alwan 12

The decimal Value:

(1 x 27) + (0 x 26) + (0 x 25) + (1 x 24) + (0 x 23) + (1 x 22) + (0 x 21) + (1 x 20) =

Logic Circuits -Dr. Mohamad Alwan 13

Logic Circuits -Dr. Mohamad Alwan 14

Logic Circuits -Dr. Mohamad Alwan 15

Logic Circuits -Dr. Mohamad Alwan 16

Logic Circuits -Dr. Mohamad Alwan 18

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- To octal (from binary)

(17.76)10 =10001.11000010100011110101 1100

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(17.76)10 =10001.11000010100011110101 1100

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Find the decimal numerical values of:

1101.1 = (1 x 23) +(1x 22 )+(0x 21)+ (1x 20) . ( 1x 2-1 )= (13.5)10

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The decimal value :

Find the decimal numerical values of:

Find the decimal numerical values of:

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• Binary addition is very simple.

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The initial carry