electronics
Article
A New Design Technique for a High-Speed and High dV/dt
Immunity Floating-Voltage Level Shifter
Min Guo 1,2 , Lixin Wang 1,2, *, Shixin Wang 1,2 , Yuan Zhao 1 and Bowang Li 1,2
Citation: Guo, M.; Wang, L.; Wang,
S.; Zhao, Y.; Li, B. A New Design
Technique for a High-Speed and High
dV/dt Immunity Floating-Voltage
Level Shifter. Electronics 2023, 12,
4841. https://doi.org/10.3390/
electronics12234841
Academic Editor: Raffaele Giordano
Received: 1 November 2023
Revised: 17 November 2023
Accepted: 22 November 2023
Published: 30 November 2023
Copyright: © 2023 by the authors.
Licensee MDPI, Basel, Switzerland.
This article is an open access article
distributed under the terms and
conditions of the Creative Commons
Attribution (CC BY) license (https://
creativecommons.org/licenses/by/
4.0/).
Electronics 2023, 12, 4841. https://doi.org/10.3390/electronics12234841
1 Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China;
guomin@ime.ac.cn (M.G.); wangshixin2020@ime.ac.cn (S.W.); zhaoyuan@ime.ac.cn (Y.Z.);
libowang@ime.ac.cn (B.L.)
2 University of Chinese Academy of Sciences, Beijing 100049, China
* Correspondence: wanglixin@ime.ac.cn; Tel.: +86-010-82035581
Abstract: This paper presents a high-speed level shifter with about 500 V/ns power supply slew
immunity. In this designed structure, a narrow pulse-controlled current source is adapted to accelerate
the voltage conversion and reduce the power consumption. A Fast-Slewing Circuit speeds up the
operation of the level shifter based on the current comparison principle. Edge detection technology
is used to filter the generated voltage noise and achieve high dV/dt immunity. The proposed level
shifter simulated with the 0.18 µm BCD (bipolar-CMOS-DMOS) process shows fast responses with a
typical delay of 1.49 ns and 500 V/ns dV/dt immunity in the 200 V high-voltage application, which
only occupies a 0.022 mm2 active area with the 0.18 µm BCD process.
Keywords: level shifter; dV/dt immunity; high speed; high-voltage floating driver
1. Introduction
In recent years, the continuous growing markets in 5G communications, wireless
transmission, fast charging industries, etc., create a huge demand for advancing today’s
high-voltage (HV) power converters for cost and energy savings. Silicon-based power
semiconductor devices have reached their physical limits due to their restrictions on device
size and their physical characteristics. Although the switching losses in power devices can
be reduced by applying technologies like soft switching, the large gate parasitic capacitance
of silicon-based devices limits the optimization of energy loss, which affects the perfor-
mance of power converters under high-input-voltage and high-frequency conditions [1].
Wide-bandgap (WBG) semiconductor materials, such as silicon carbide (SiC) and gallium
nitride (GaN), have been demonstrated to offer excellent features compared to silicon. For
instance, wide-bandgap (WBG) semiconductor materials allow smaller, faster, more reliable
power electronic components than their silicon-based counterparts [2]. The wide-bandgap
power devices exhibit greater thermal conductivity and electric field strengths, and as a
result, SiC and GaN power devices have lower on-resistance to reduce conduction losses [3].
Therefore, the wide-bandgap GaN and SiC devices have gradually replaced the original
silicon-based power semiconductor devices for their excellent performance advantages,
producing a technological revolution in the fields of information communication, electric
vehicles, and consumer electronics [4–7].
Usually, SiC and GaN power devices are used in half-bridge drivers as power switches.
Level shifters are commonly employed as a transmission bridge between different voltage
domains to shift the potential of the control logic from the low-voltage domain to the
high-voltage domain or from the high-voltage domain to the low-voltage domain [8]. The
high-voltage domain mainly includes level shift, high-side drive, and bootstrap circuits.
Unlike the supply voltage of the low-voltage domain (usually a fixed voltage below 5 V),
the high-voltage domain is powered by floating power rails (VDDH and VSSH). When
the high-side power transistor is turned on, the low-voltage VSSH of the floating power
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Electronics 2023, 12, 4841 2 of 12

When the high-side power transistor is turned on, the low-voltage VSSH of the floating
power rail is approximately equal to the input voltage VHV of the half-bridge driver, and
therail is approximately
high-voltage VDDH equal of the to the input
floating power voltage
rail is V HV of
equal tothe half-bridge
VSSH + VCC. driver, and the
high-voltage
To turn onVDDHand offofthe thehigh-side
floating power
power rail is equalthe
transistor, to VSSH + VCC.
high-side driver needs to run
To turn on and off the high-side power transistor, the high-side
on a floating power rail. The logic control signal is from the low-voltage domain driver needs
and tomust
run on
be transformed to a high-voltage domain logic signal. As shown in Figure 1, the low-volt-be
a floating power rail. The logic control signal is from the low-voltage domain and must
agetransformed
control signalto aishigh-voltage
sent to the leveldomain logicafter
shifter signal. As via
going shownthe in Figure
Input 1, the low-voltage
Detection module,
which activates or deactivates the high-side power transistor. Therefore, as amodule,
control signal is sent to the level shifter after going via the Input Detection which
bridge con-
activates
necting the or deactivatesdomain
high-voltage the high-side
and thepower transistor.
low-voltage Therefore,
domain, as a bridge
the level shifter connecting
is one of
the high-voltage domain and the low-voltage domain, the level
the most critical circuits in the half-bridge driver. However, the GaN and SiC MOSFET shifter is one of the most
critical circuits in the half-bridge driver. However, the GaN
can generate larger dV/dt and di/dt noise in the fast switching. For GaN MOSFET,and SiC MOSFET can generate
the
dV/dt could be up to above 200 V/ns [9]. This fast slewing is particularly problematic onbe
larger dV/dt and di/dt noise in the fast switching. For GaN MOSFET, the dV/dt could
theup to above
high side of200
theV/ns [9]. This
half-bridge fast slewing
driver, as shown is particularly
in Figure 1. problematic on the high side of
the half-bridge driver, as shown in Figure 1.

VCC

VDDH
VHV
CB

Floating
Input Voltage
Driver GaN
Detection Level
Shifter VHV
200V/ns

VSSH
0
VIN VDDL

0 GaN
LS_G

Figure 1. The block diagram of the GaN high-voltage half-bridge driver.

Figure 1. The block diagram of the GaN high-voltage half-bridge driver.
Figure 2 shows the reliability issues with traditional GaN drivers. When the high-side
Figure
power 2 showsisthe
transistor reliability
activated, the issues
voltage with traditional
of VSSH will beGaN drivers.
quickly raisedWhen the, and
to VHV high-the
side power
rising transistor
speed is >200isV/ns.
activated, the voltage change
This dVSSH/dt of VSSH is will be quickly
coupled raisedshifter
to the level to VHVthrough
, and
thea rising
bootstrapspeedcapacitor.
is >200 V/ns. This
Since dVSSH/dt
the change
level shifter canisperform
coupled voltage
to the level shifter through
conversion between
a bootstrap
the low-voltagecapacitor. Sinceand
domain the level shifter can perform
the high-voltage domain,voltage
MH1 and conversion
MH2 arebetween the
high-voltage
low-voltage domain and the high-voltage domain, MH1 and MH2 are
transistors, whose parasitic capacitance is large. The parasitic capacitance will generate a high-voltage tran-
sistors,
charging whose parasitic capacitance
or discharging current when is large.
dV/dtThe parasitic
happens, whichcapacitance will with
will interfere generate a
the level
charging
shifter’sornormal
discharging current
operation and when
cause dV/dt happens,
errors in which
the driver’s willvoltage
logic interfere withhigh-voltage
of the the level
shifter’s
domain normal
[10–12].operation
In Figure and 2, cause
it can errors
be seen inthat
the driver’s
under the logic voltage
action of theofbootstrap
the high-voltage
capacitor
domain
CBOOT[10–12].
, VDDHIn Figure with
changes 2, it can be seen
VSSH, and that under the
dVDDH/dt is action of the bootstrap
approximately equal tocapacitor
dVSSH/dt.
CBOOT , VDDHsince
However, changes with MOS
the input VSSH, and dVDDH/dt
device MH1 of theislevelapproximately equal to dVSSH/dt.
shifter is a high-voltage transistor,
However,
there is asince
largethe input MOS
parasitic device Cpar
capacitance MH1at ofnode
the level shifter
A. The rapid is change
a high-voltage transistor,
of the VDDH acts on
Cpar
there is to generate
a large a large
parasitic current, which
capacitance Cparpulls down
at node the voltage
A. The of node
rapid change ofA.theWhen
VDDH theacts
noise
onamplitude
Cpar to generate(=R × Cpar a large× current,
dVSSH/dt) which generated
pulls downat node A is larger
the voltage thanA.
of node BOOT −
(VWhen VT ),
the
the recovery
noise amplitude circuit
(=R ×ofCpar
the subsequent
× dVSSH/dt) stage may transmit
generated at node theAnoise signal
is larger by mistake,
than (VBOOT − V where
T),

theVBOOT
recoveryis equal to VDDH
circuit − VSSH. Therefore,
of the subsequent stage may the transmit
dV/dt immunity
the noisecapability
signal byofmistake,
the driver
is limited by the parasitic capacitance of the HV transistor
where VBOOT is equal to VDDH − VSSH. Therefore, the dV/dt immunity capability of theof the level shifter.
driver is Existing
limitedhigh-voltage
by the parasitic level shifters have
capacitance employed
of the a number
HV transistor of theoflevel
design techniques
shifter.
to improve dV/dt immunity [13–15]. In [13], the author proposed a level shifter based
on high-bandwidth current and latch structure; the delay is 370 ps, but the dV/dt slew
immunity is only 30 V/ns. Yang et al. adopted a new technique to enhance the slew
rate of level shifters, achieving a novel level shifter with 120 V/ns immunity and 20 ns
propagation delay [14]. The level shifter (LS) proposed in [15] is designed with a current
mirror/latch structure, and a common-mode noise canceller is also applied to enhance the
dV/dt immunity. This level shifter achieves 200 V/ns noise immunity and sub-nanosecond
delay in the SOI process, but this good performance is limited by the process. As the supply
voltage increases, level shifters made with traditional processes suffer more from dV/dt
noise. Then the ensuing problem is that the level shifter needs to consume more energy to
 Electronics 2023, 12, 4841 3 of 12

Electronics 2023, 12, x FOR PEER REVIEW 3 of 13

enhance the dV/dt immunity of the circuit. As a result, several conventional structures
designed to enhance the dV/dt noise immunity of the level shifters become inappropriate
as the power supply voltage rises.

Allowable Noise Unallowable Noise VDDH

VHV
CBOOT

R
>V BOOT-VT
>VBOOT−VT LATCH Buffer GaN
A
Cpar VSSH
dVSSH
dt

MH1 MH2
VIN
VIN

Figure 2. Reliability problem of the traditional level shifter.

Figure 2. Reliability problem of the traditional level shifter.
This paper presents a high-speed and high dV/dt immunity floating-voltage level
shifter in the
Existing 0.18 µm BCD
high-voltage process.
level shiftersThe proposed
have employed design can achieve
a number a small
of design propagation
techniques to
delay and an ultra-high dV/dt noise shielding function.
improve dV/dt immunity [13–15]. In [13], the author proposed a level shifter based on
The rest ofcurrent
high-bandwidth this paper is organized
and latch structure; as the
follows:
delayIn is Section
370 ps, 2,buttwo
theconventional
dV/dt slew im- level
shifteris designs
munity only 30 are
V/ns.reviewed.
Yang et al.Inadopted
Section a3,new a novel enhanced
technique level shifter
to enhance is proposed,
the slew rate of
andshifters,
level its propagation
achievingdelay andlevel
a novel dV/dt immunity
shifter with 120 areV/ns
analyzed
immunityin detail.
and 20 Sections 4 and 5,
ns propaga-
respectively,
tion delay [14].display
The levelthe shifter
simulation
(LS) results
proposed andin conclusion.
[15] is designed with a current mir-
ror/latch structure, and a common-mode noise canceller is also applied to enhance the
2. Previous Level Shifter
dV/dt immunity. This level shifter achieves 200 V/ns noise immunity and sub-nanosecond
delay inAtheconventional
SOI process, level
butshifter is shown
this good in Figureis3 limited
performance [16]. The byMOS transistors
the process. As M1–M4
the sup-are
plyhigh-voltage transistors.
voltage increases, levelLDNMOS
shifters made(laterally
withdiffused N type
traditional metal oxide
processes suffersemiconductor)
more from
transistors M1 and M2 connect their gates to VDDL to protect
dV/dt noise. Then the ensuing problem is that the level shifter needs to consume and clamp the low-voltage
more
(LV) transistors ML1 and ML2. In addition, the circuit connects
energy to enhance the dV/dt immunity of the circuit. As a result, several conventional the gates of the LDPMOS
(laterallydesigned
structures diffusedto P enhance
type metal theoxide
dV/dtsemiconductor)
noise immunitytransistors M3
of the level and M4
shifters to VSSH
become in- to
protect the low-voltage transistors
appropriate as the power supply voltage rises. ML5 and ML6 from being damaged by breakdown. This
circuit can convert the low-voltage power rail signal from GND-VDDL
This paper presents a high-speed and high dV/dt immunity floating-voltage level to the high-voltage
floating
shifter in thepower railBCD
0.18 µm signal VSSH-VDDH.
process. The proposedHowever, designLDNMOS
can achieveanda LDPMOS transistors
small propagation
increase
delay and an theultra-high
parasitic capacitance
dV/dt noiseand cause large
shielding propagation delays. More seriously, this
function.
structure suffers from mismatch delay and low dV/dt noise immunity. This level shifter has
Electronics 2023, 12, x FOR PEER REVIEWThe rest of this paper is organized as follows: In Section 2, two conventional 4level of 13
inconsistent low-to-high and high-to-low conduction delays due to the current asymmetry
shifter designs are reviewed. In Section 3, a novel enhanced level shifter is proposed, and
between the rising and falling edges of the output node.
its propagation delay and dV/dt immunity are analyzed in detail. Sections 4 and 5, respec-
tively, display the simulation
VDDH
results and conclusion.

LV PMOS
2. Previous Level Shifter
ML5 ML6
A conventional level shifter is shown in Figure VOUT
3 [16].LVThe
NMOS
MOS transistors M1–M4
are high-voltage transistors. LDNMOS (laterally diffused N type metal oxide semiconduc-
tor) transistors M1 and M2 connect their gates to VDDL toLDPMOS protect and clamp the low-
VSSH M3 M4
voltage (LV) transistors ML1 and ML2. In addition, the circuit connects the gates of the
LDPMOS (laterally diffused P type metal oxide semiconductor) LDNMOStransistors M3 and M4 to

VSSHVDDL
to protect the
M1 low-voltage M2transistors ML5 and ML6 from being damaged by break-

down. This
VDDL
circuit can convert the low-voltage power rail signal from GND-VDDL to the
VDDL
high-voltage
VIN 0 floating
ML1 power rail
ML2
signal VSSH-VDDH. However, LDNMOS and LDPMOS
transistors increase the parasitic capacitance and cause large propagation delays. More
seriously, this structure suffers from mismatch delay and low dV/dt noise immunity. This
level shifter has inconsistent low-to-high and high-to-low conduction delays due to the
Figure
Figure3.
current 3.Traditional
asymmetry level
Traditional levelshifter
between thebased
shifter basedon
risingonhigh-voltage
high-voltage
and PMOS
PMOS
falling edges ofclamping.
clamping.
the output node.

Figure 4 shows another type of conventional level shifter [17]. This topology clamps
the voltage at nodes N1 and N2 to VDDH − VGS by using the diode-connected low-volt-
age PMOS transistors M1 and M4, where VGS is the gate-source voltage of the PMOS
transistors. When the input signal VIN switches from low to high, the high-voltage tube
 VDDL M1

VDDL VDDL
VIN 0
ML1 ML2

Electronics 2023, 12, 4841 4 of 12

Figure 3. Traditional level shifter based on high-voltage PMOS clamping.

Figure
Figure44shows
showsanother
anothertypetypeofofconventional
conventionallevel levelshifter
shifter[17].
[17].This
Thistopology
topologyclamps
clamps
the voltage at nodes N1 and N2 to VDDH − VGS by using the diode-connected
the voltage at nodes N1 and N2 to VDDH − VGS by using the diode-connected low-voltage low-volt-
age PMOS
PMOS transistors
transistors M1 M4,
M1 and andwhere
M4, where
VGS isVGS is the gate-source
the gate-source voltage ofvoltage
the PMOSof the PMOS
transistors.
transistors. When the input signal VIN switches from low to high,
When the input signal VIN switches from low to high, the high-voltage tube LDNMOS1 the high-voltage tubeis
LDNMOS1
turned on;isthen
turned
the on; then the
potential potential
of the N1 pointof the N1 point
is pulled is pulled
down, down,
and the and the
potential ofpoten-
the N2
tial of the
point N2However,
rises. point rises. However,
the potentialthe potential
at point at point N1
N1 decreases decreases
more slowlymore
than slowly than
the potential
the potential at point N2 rises due to the current asymmetry. In the
at point N2 rises due to the current asymmetry. In the same way, when the VIN switchessame way, when the
VIN switches from high to low, the high-voltage tube LDNMOS2 is
from high to low, the high-voltage tube LDNMOS2 is turned on; then the potential of theturned on; then the
potential
N2 pointofisthe N2 point
pulled is pulled
down, and thedown, and the
potential ofpotential of therises.
the N1 point N1 point
Therises. Thespeed
falling fallingof
speed of the potential
the potential at point at
N2point N2 isthan
is slower slower
the than
risingthe rising
speed at speed at point
point N1. For N1. For the
the structure
structure
in Figurein4,Figure
only a4,pair
only
of ahigh-voltage
pair of high-voltage transistors,
transistors, LDNMOS1 LDNMOS1 and LDNMOS2,
and LDNMOS2, are used,
are used,
which which
has has parasitic
a lower a lower parasitic capacitance
capacitance than the than the structure
structure in Figurein3.Figure 3. However,
However, this level
this levelfaces
shifter shifter
thefaces
samethe same difficulties
difficulties as the structure
as the structure shown in shown
Figurein3,Figure
namely,3, namely,
that there that
is a
there is a severe mismatch delay and low
severe mismatch delay and low dV/dt noise immunity.dV/dt noise immunity.

VDDH

LV PMOS

M1 M2 M3 M4
LDNMOS

N1 N2
Fast rising

VDDL Slow falling VOUT

LATCH

VIN Narrow Narrow

Pulse LDNMOS1 Pulse LDNMOS2

Figure
Figure4.4.Traditional
Traditionallevel
levelshifter
shifterbased
basedon
ondiode-connected
diode-connectedPMOS
PMOSclamping.
clamping.

3.3.Proposed
ProposedEnhanced
EnhancedLevelLevelShifter
Shifter
AsAsshown
shownFigure
Figure5,5,this
thispaper
paperpresents
presentsaahigh-speed
high-speedandandhigh
highdV/dt
dV/dtimmunity
immunitylevel
level
shifter which consists of three parts: the Power Supply Rail Conversion Circuit,
shifter which consists of three parts: the Power Supply Rail Conversion Circuit, the Fast- the Fast-
SlewingCircuit
Slewing Circuit (FSC),
(FSC), and andthethe dV/dt
dV/dt Noise
Noise Shielding
Shielding Circuit.
Circuit. The Power
The Power SupplySupply Rail
Rail Con-
Conversion Circuit converts the signal from the low-voltage domain to
version Circuit converts the signal from the low-voltage domain to the high-voltage do- the high-voltage
domain.
main. TheThe Fast-Slewing
Fast-Slewing Circuit
Circuit speeds
speeds upupthethe level
level shifter’s
shifter’s signalconversion.
signal conversion.And
Andthenthen
the dV/dt Noise Shielding Circuit can shield the dV/dt noise to make
the dV/dt Noise Shielding Circuit can shield the dV/dt noise to make the output of the the output of the
level shifter remain constant.
level shifter remain constant.
In Figure 5, the input transistors M1 and M2 are low-voltage MOS devices. The
diode-connected transistors M7 and M8 are used to clamp the voltages of node A and
node B. The gate of the high-voltage transistors MNLD3 and MNLD4 are connected to the
low-voltage rail power supply VDDL to bear high voltage, preventing the breakdown of
the low-voltage transistors M1 and M2. The M5 and M6 transistors are used in the form
of diodes, with their sources connected to the floating power supply ground VSSH to
ensure that the voltages of node A and node B can be higher than VSSH − VTH (VTH is the
threshold voltage of the MOSFET). This prevents the drain-source voltage of the M7 and
M8 devices from exceeding the safe voltage range. A narrow pulse generation circuit is
adopted to generate the instantaneous driving signal and speed up the operation of the
level shifter [18]. Additionally, the Fast-Slewing Circuit that was added to the circuit can
speed up the voltage conversion rate of the level shifter even more, eliminating the issue of
various mismatch delays.
Electronics 2023, 12, x FOR PEER REVIEW 5 of 13

Electronics 2023, 12, 4841 5 of 12

VDDH
M7 M8
dV/dt Noise VOUT
B Fast-Slewing
Shielding
A Circuit
Circuit

M5 M6
VSSH
MNLD3 MNLD4
VDDL

VIN
Narrow Narrow
Pulse M1 Pulse M2

VSSL

Power Supply Rail Conversion Circuit

Figure 5. Top structure and strategy of the proposed level shifter.

Figure 5. Top structure and strategy of the proposed level shifter.
The problem of dV/dt immunity is the most important concern of the level shifter,
In Figure
which 5, the
can be input from
analyzed transistors
the two M1situations
and M2 are low-voltage
of positive swing MOSanddevices.
negative The di- of
swing
ode-connected transistors
the power supply. AsM7shown and M8 are used
in Figure 6, to clamp
when thethe
VIN voltages
is high,of the
node A and states
normal node of
B. The
VA gate
− VSSHof the
andhigh-voltage
VB − VSSHtransistors MNLD3 and M
are low voltage high are connected
NLD4voltage, to the low-volt-
respectively. When VSSH
ageand
rail power
VDDHsupply
quicklyVDDL to bear
transition high
from voltage,
high preventing
voltage the breakdown
to low voltage, both VAof−the low-and
VSSH
VB −transistors
voltage VSSH riseM1 and M2.
to high The M5
voltage. When andVSSH
M6 transistors
and VDDH are transition
used in thefrom
formlowof diodes,
voltage to
with theirvoltage,
high sourcesboth VA − to
connected the floating
VSSH − VSSH
and VB power supply ground
can drop VSSH
to low to ensure
voltage. that the the
Therefore,
Electronics 2023, 12, x FOR PEER REVIEW 6 of 13
voltages
dV/dtofNoise
nodeShielding
A and node B can
Circuit is be higher
meant than VSSH
to maintain the−level
VTH (V TH is the
shifter’s threshold
output voltage
in order to avoid
theMOSFET).
of the succeedingThis stageprevents
circuit fromthe receiving
drain-sourcethe erroneous
voltage ofsignal
the M7 output
and M8of the level shifter.
devices from
exceeding the safe voltage range. A narrow pulse generation circuit is adopted to generate
the instantaneous drivingPower Supply Slew
signal and speed up the operation of the level shifter [18]. Ad-
VIN
ditionally, the Fast-Slewing Circuit that was added to the circuit can speed up the voltage
dv/dt sensing
conversion rate of the level shifter even more, eliminating the issue of various mismatch
delays.
VDDH/VSSH
The problem of dV/dt immunity is the most important concern of the level shifter,
which can ΔVA from the two situations of positive swing and negative swing of
be analyzed
VAV −A-VSSH
VSSH
VF
the power supply. As shown in Figure 6, when the VIN is high, the normal states of VA −
VSSHV and VB − VSSH VF are low voltage and high voltage, respectively. When VSSH and
BV−B-VSSH
VSSH
VDDH quickly transition from highΔVvoltage B to low voltage, both VA − VSSH and VB −
VSSH rise to high voltage. When VSSH and VDDH transition from low voltage to high
Maintain Original State
voltage, both
VOUT-VSSH
VOUT
VA − VSSH and VB − VSSH can drop to low voltage. Therefore, the dV/dt
− VSSH
Noise Shielding Circuit is meant to maintain the level shifter’s output in order to avoid
the Figure
succeeding stage
6. Noise circuitfeature
shielding from receiving
for dV/dt thewhenerroneous
the VIN issignal
high. output of the level shifter.
Figure 6. Noise shielding feature for dV/dt when the VIN is high.
3.1. Strategy for the Enhanced Level Shifter
3.1. Strategy for the Enhanced Level Shifter
The level shifter proposed in this article is shown in Figure 7. The signal conversion
The
of the level
level shifter
shifter canproposed in this
be sped up articlethe
by using is shown in Figure
Fast-Slewing 7. The
Circuit andsignal conversion
the double-pulse
ofgeneration
the level shifter can be sped up by using the Fast-Slewing Circuit and the
circuit. The double-pulse generation circuit can generate a voltage pulse on the double-pulse
generation
rising andcircuit.
fallingTheedgesdouble-pulse
of an inputgeneration circuit can
signal, consisting of generate
a NANDagate, voltage pulse on the
a capacitor, and
rising
severaland falling edges
inverters. In theof an inputlevel
proposed signal, consisting
shifter, the inputof aofNAND gate, a capacitor,
this double-pulse and
generation
several inverters.
circuit is the signalInofthe
theproposed
VIN, andlevel shifter,ofthe
the output theinput
circuitofisthis
used double-pulse
to control thegeneration
on and off
circuit is the signal of the VIN, and the output of the circuit is used
of M1 and M2. Therefore, whenever there is a conversion of high voltage to low voltage to control the on andor
off of M1 and M2. Therefore, whenever there is a conversion of high voltage
low voltage to high voltage, a large current will appear in the voltage conversion branch, to low voltage
or low voltage
improving to highconversion
the voltage voltage, a speed.
large current
At the samewill time,
appear theintransistors
the voltageM1conversion
and M2 are
branch,
turned improving
off during the the voltage
voltageconversion speed.
holding stage, so At thethe
that same
leveltime, the transistors
shifter has very low M1static
and
M2 are turned
power off during the voltage holding stage, so that the level shifter has very low
consumption.
static power consumption.

Power Supply Rail Conversion Fast-Slewing Circuit

VDDH
M7 M8
M9 M13 M12 M16 the Edge Detection Circuit SR Latch
B
A NAND1
 circuit is the signal of the VIN, and the output of the circuit is used to control the on and
off of M1 and M2. Therefore, whenever there is a conversion of high voltage to low voltage
or low voltage to high voltage, a large current will appear in the voltage conversion
branch, improving the voltage conversion speed. At the same time, the transistors M1 and
Electronics 2023, 12, 4841 M2 are turned off during the voltage holding stage, so that the level shifter has very low 6 of 12
static power consumption.

Power Supply Rail Conversion Fast-Slewing Circuit

VDDH
M7 M8
M9 M13 M12 M16 the Edge Detection Circuit SR Latch
B
A INV1 INV2 INV3
NAND1
VOUT
C Buffer1
NAND4

D NAND3
NAND2
INV1 INV2 INV3
M10 M11 M14 M15
M5 M6 Buffer2
VSSH
MNLD3 MNLD4
VDDL

VIN M1 M2

Double Pulse Double Pulse

Generation Circuit Generation Circuit

Power Supply Rail Conversion Fast-Slewing Circuit dV/dt Noise Shielding Circuit

Figure 7. Schematic of the proposed level shifter circuit.

Figure 7. Schematic of the proposed level shifter circuit.
The Fast-Slewing Circuit is a current mirror that makes use of the principle of current
The Fast-Slewing
comparison to achieveCircuit is voltage
rapid a currentconversion
mirror thatspeed
makes[19].
use ofAsthe
canprinciple
be seen ofincurrent
Figure 7,
comparison
when the VIN signal transitions from low voltage to high voltage, the voltageFigure
to achieve rapid voltage conversion speed [19]. As can be seen in 7, A
of node
when the VIN
can drop signal
rapidly transitions
with from
the help of the low
hugevoltage to high
pull-down voltage,
capability ofthe
the voltage of M1,
transistor nodewhile
A
can drop rapidly with the help of the huge pull-down capability of the transistor M1,
the asymmetric current of the circuit causes the voltage of node B to rise slowly. Therefore, while
thethe
asymmetric
proposed current of theadopts
level shifter circuitthe
causes the voltage
Fast-Slewing of node
Circuit to B to rise slowly.
improve Therefore,
the response speed.
theThe
proposed level shifter adopts the Fast-Slewing Circuit to improve
voltages at nodes A and B are mirrored to nodes D and C through a current the response speed.
mirror,
The voltages atafter
respectively, nodes A and through
passing B are mirrored to nodes DCircuit,
the Fast-Slewing and C through
preventing a current mirror,
the circuit from
various mismatch delays. Then, the rising edge of node C or D can be captured by the edge
detection circuit and locked by the SR latch, which finally changes the output of the level
shifter and keeps it constant until the VIN changes.

3.2. The Propagation Delay of the Proposed Level Shifter

The proposed level shifter’s operation for switching from low to high is shown in
Figure 8a. Before the VIN becomes high, VA is equal to VDDH, and VB is equal to VSSH.
The signal transmission process of the level shifter is as follows:
(1) When the VIN changes from low voltage to high voltage, the generation circuit, which
consists of a NAND gate, a capacitor, and several inverters, generates a voltage pulse
on the rising edges of the VIN signal. The delay in this process is called Tr0 , which is
determined by the delay of the NAND gate.
(2) When the voltage pulse generates, the input transistor M1 is turned on, and the
voltage VA at node A begins to drop rapidly. The delay in this process is called Tr1 .
The strong pull-down capability of M1 will briefly provide a large current to the
branch where node A is located to increase the response speed of node A.
(3) The current M7 is mirrored by the M9. Due to the small current of M10, the current of
M9 is much greater than that of M10, so the potential at node C is rapidly raised to
VDDH. The Tr2 is the transmission delay from node A to node C, which is determined
by the delay of the current comparator.
(4) The edge detection circuit can identify the rising edge signal of node C. When VC
becomes high, a short pulse signal is generated at node S under the action of the
delay chain composed of INV1-INV3 and NAND1. Tr3 is the delay of the edge
detection circuit.
(5) The generation of a short pulse signal VS triggers the flipping voltage of NAND4. At
this point, the VOUT transitions from low to high and remains at VDDH until a short
pulse occurs at node R. The delay between VS and VOUT is described by Tr4 , which
is the delay of NAND4.

Electronics 2023, 12, 4841
The current of M7 can also be mirrored to M15 through M13 and M14. Due to the
small current of M16, the voltage at node D is quickly pulled down. Although the descent
speed of VD is slower than the ascent speed of VA, the drop of VD is not detected by the
edge detection circuit and is just prepared for the next reset. Therefore, when the input
signal VIN changes from low to high, the speed at which the voltage at node D12changes
7 of
has no effect on the circuit.

VDDH
M7 M8 Tr3
M13 M12 M16 Tr4
B M9
A NAND1
S
INV1 INV2 INV3 NAND4 VOUT
Tr2 C Buffer1

D NAND3
NAND2

M11 M14 M15 INV1 INV2 INV3 R

M10
M5 M6 Buffer2
VIN

Tr1 VSSH VOUT

MNLD3 MNLD4
VDDL

INV0
Tr=Tr0+Tr1+Tr2+Tr3+Tr4
Tr0
VIN M2
Electronics 2023, 12, x FOR PEER REVIEW M1 8 of 13

(a)
VDDH
M7 M8
M9 M13 M12 M16 Tf6
B
A NAND1
S
INV1 INV2 INV3 NAND4 VOUT
C Buffer1
Tf3
D NAND3
NAND2
INV1 INV2 INV3 R
M10 M11 M14 M15
M5 M6 Tf2 Buffer2
VIN
Tf5
VSSH Tf4 VOUT
MNLD3 MNLD4
VDDL
Tf0

INV0
Tf1
VIN M1 M2

Tf=Tf0+Tf1+Tf2+Tf3+Tf4+Tf5+Tf6

(b)

Figure 8.Figure 8. The suggested

The suggested level shifter’s
level shifter’s switching
switching operation:
operation: (a) low-to-high
(a) low-to-high switching
switching operation; (b)
operation;
high-to-low switching operation.
(b) high-to-low switching operation.

The currentAs shown

of M7 incan Figure
also be 8b,mirrored
when thetoinput voltage of
M15 through M13theandlevelM14.
shifter
Due transitions
to the from
high to
small current of low,
M16,thethepropagation
voltage at node delay Td_f
D is of the pulled
quickly signal down.
consistsAlthough
ofTf0, Tf1,the
Tf2,descent
Tf3, Tf4, Tf5, and
speed ofTV f6.DDue to the than
is slower goodthe symmetry of theof
ascent speed proposed level shifter,
VA , the drop of VD isTnot r0 is detected
equal to T byf1, the
Tr1 is equal
to Tf2, Tcircuit
edge detection r2 is equal
andtoisTjustf3, Tr3 is equal for
prepared to Tthe
f4, and
nextTreset.
r4 is equal to Tf5. Therefore,
Therefore, when the input it can be seen
signal VINthatchanges
Td_f has from
two morelow to high,items,
delay the speed
Tf0 and at which
Tf6, than theTd_r
voltage
, which atare
nodetheDdelays
changes of the two
has no effect
NAND on gates.
the circuit.
Therefore, Td_r is smaller than Td_f.
As shown in Figure 8b, when the input voltage of the level shifter transitions from
high to low, the propagation
3.3. The dV/dt Immunity delay Td_fProposed
of the of the signal
Level consists
Shifter ofTf0 , Tf1 , Tf2 , Tf3 , Tf4 , Tf5 , and
Tf6 . Due to the good symmetry of the proposed
The edge generation circuit of the proposed level shifter,level
Tr0 isshifter
equal hasto Tf1 , Tr1functions.
two is equal One is
to Tf2 , Tthat
r2 is equal to T ,
the edge generation
f3 T r3 is equal to T
circuit can , and T is equal to T . Therefore,
f4 outputr4a pulse signalf5at the rising edge it canand be falling
seen thatedge
Td_f of
has two more delay items,
the input signal; on the other Tf0 and T
hand, , than
f6 the edge T , which are the delays of
d_r generation circuit generates a large the
two NAND gates. Therefore, T d_r is smaller than T d_f .
current during the narrow pulse signal to help the signal transfer quickly, and reduces the
overall power consumption of the circuit by turning off the input transistors M1 and M2
3.3. The dV/dt Immunity of the Proposed Level Shifter
during the VIN signal hold.
The edgeThe
generation
transientcircuit of theof
operation proposed level shifter
the proposed level has twoisfunctions.
shifter One iswith
demonstrated that low-to-
the edge generation circuit can output a pulse signal at the rising edge and falling edge of
high and high-to-low operations. When the VIN shifts from low to high, M1 is activated
the input signal; on the other hand, the edge generation circuit generates a large current
and M2 is turned off. The voltage at node A starts declining, the dropping edge of node A
during the narrow pulse signal to help the signal transfer quickly, and reduces the overall
is sampled, and the rise of node C is accelerated by the current comparison circuit. The
power consumption of the circuit by turning off the input transistors M1 and M2 during
rising edge of node C is delayed by the delay circuit composed of the inverters INV1–
the VIN signal hold.
INV3, and then the delayed signal is input to NAND1 together with the signal of node C.
The transient operation of the proposed level shifter is demonstrated with low-to-high
Next, a low-voltage pulse signal S is generated, and then the voltage of the VOUT changes
and high-to-low operations. When the VIN shifts from low to high, M1 is activated and
from low to high. When the input signal VIN changes from high to low, M2 is turned on,
M2 is turned off. The voltage at node A starts declining, the dropping edge of node A
and M1 is turned off. The voltage at node B begins to drop, and then the falling edge of
node B is sampled, which speeds up the rising speed of node D. The rising edge of node
D can be delayed by the inverters INV4–INV6 and this delayed waveform is input into
NAND2 with node D. At this time, a low-level pulse is generated in R to make the VOUT
change from high to low. Figure 9 shows the waveform of the level shifter during the VIN
 Electronics 2023, 12, 4841 8 of 12

is sampled, and the rise of node C is accelerated by the current comparison circuit. The
rising edge of node C is delayed by the delay circuit composed of the inverters INV1–INV3,
and then the delayed signal is input to NAND1 together with the signal of node C. Next,
a low-voltage pulse signal S is generated, and then the voltage of the VOUT changes
from low to high. When the input signal VIN changes from high to low, M2 is turned on,
and M1 is turned off. The voltage at node B begins to drop, and then the falling edge of
node B is sampled, which speeds up the rising speed of node D. The rising edge of node
D can be delayed by the inverters INV4–INV6 and this delayed waveform is input into
Electronics 2023, 12, x FOR PEER REVIEWNAND2 with node D. At this time, a low-level pulse is generated in R to make the 9 ofVOUT
13
change from high to low. Figure 9 shows the waveform of the level shifter during the VIN
transient changes.

VIN

VA

VB

VC

VC_delay

VD

VD_delay

VOUT

Figure 9. The waveform of the level shifter during VIN transient changes.
Figure 9. The waveform of the level shifter during VIN transient changes.
The proposed level shifter can shield dV/dt noise by using the dV/dt Noise Shielding
The proposed
Circuit, level shifter
which consists can shieldand
of INV1–INV6 dV/dt noise by
NAND1, using the
NAND2. dV/dt
The Noise
voltages at Shielding
nodes C and
Circuit,
D willwhich
rise orconsists of INV1–INV6
fall synchronously anddV/dt
when NAND1, noiseNAND2. The voltages
is generated at nodes
due to rapid C and
changes in the
D will
VSSH riseand
or VDDH.
fall synchronously
If the dV/dtwhen noise dV/dt
is high,noise is generated
voltage changes atduenodesto rapid
C and changes in
D may trigger
the the
VSSHlogicand VDDH.
gates of theIf edge
the dV/dt noisecircuit.
detection is high,Positive
voltagedV/dt
changes at nodes
noise C andundershoot
will cause D may
trigger the at
voltage logic gates
nodes of the
C and D,edge detectiondV/dt
and negative circuit. Positive
noise dV/dtovershoot
will cause noise willatcause
nodes under-
C and D.
However,
shoot voltage these
at nodesgenerated
C and D, voltage noises will
and negative be filtered
dV/dt after
noise will passing
cause through
overshoot the edge
at nodes
detection
C and circuit, so
D. However, thatgenerated
these no error signals
voltage will be generated
noises at the Safter
will be filtered and R terminals,
passing and the
through
the state
edgeof the RS latch
detection willsonot
circuit, beno
that changed. Therefore,
error signals will bethe proposedatlevel
generated the Sshifter
and Rcan shield
termi-
the
nals, dV/dt
and noiseoffrom
the state the RSdisturbing
latch willthe
notoutput VOUT,Therefore,
be changed. so that thetheVOUT can remain
proposed constant.
level shifter
can shield the dV/dt noise from disturbing the output VOUT, so that the VOUT can remain
4. Simulation Results
constant.
The proposed level shifter is simulated at the 0.18 µm BCD process using the Cadence
Virtuoso
4. Simulation tool. Figure 10 shows the simulated propagation performance of the proposed
Results
level
Theshifter
proposed withlevel
205 V VDDH
shifter and 200 V at
is simulated VSSH under
the 0.18 µmthe typical
BCD process
process using corner. All power
the Cadence
rails are supplied with fixed voltage sources during simulation
Virtuoso tool. Figure 10 shows the simulated propagation performance of the proposed (VDDH − VSSH = 5 V,
level shifter with 205 V VDDH and 200 V VSSH under the typical process corner. Allthe
VDDL = 5 V). The VIN is operated under 5 V supply voltage, and the low voltage of
VOUT is 200 V and the high voltage is 205 V. It can be seen from Figure 10 that when
power rails are supplied with fixed voltage sources during simulation (VDDH − VSSH =
the rising edge of the VIN is generated, the voltage at node A drops and triggers the
5 V, VDDL = 5 V). The VIN is operated under 5 V supply voltage, and the low voltage of
low-voltage pulse signal of the S terminal of the RS flip-flop, and then the VOUT starts to
the VOUT is 200 V and the high voltage is 205 V. It can be seen from Figure 10 that when
flip from low to high. The voltage at node B decreases when the falling edge of the VIN
the rising edge of the VIN is generated, the voltage at node A drops and triggers the low-
arrives; then the R terminal of the RS flip-flop generates a low-voltage pulse signal, and the
voltage pulse signal of the S terminal of the RS flip-flop, and then the VOUT starts to flip
VOUT starts to change from high to low. The simulation results show that the propagation
from low to high. The voltage at node B decreases when the falling edge of the VIN arrives;
then the R terminal of the RS flip-flop generates a low-voltage pulse signal, and the VOUT
starts to change from high to low. The simulation results show that the propagation delay
of the rising edge is about 1.23 ns, and the propagation delay of the falling edge is about
1.75 ns.
Electronics 2023, 12, 4841 9 of 12

Electronics 2023, 12, x FOR PEER REVIEW 10 of 13

delay
Electronics 2023, 12, x FOR PEER REVIEW of the rising edge is about 1.23 ns, and the propagation delay of the falling10edge
of 13is
about 1.75 ns.

Figure 10. Propagation delay

Figure 10. delay of the
the proposed
proposed level
level shifter.
shifter.
Figure 10. Propagation delay of the proposed level shifter.
Figure 11a,bshow
Figure 11a,b showthe therising
rising and
and falling
falling delays
delays of the
of the proposed
proposed levellevel shifter
shifter underunder
three
Figure
three 11a,b
process show ss
corners, the(Worst
rising Case),
and falling
tt delaysCase),
(Typical of the and
proposed
ff level
(Best shifter
Case), at under three
temperatures
process corners,
◦ Ccorners,
ss (Worst Case), tt (Typical Case), and ff (Best Case), at temperatures −55 °C
process
− 55 150
and and 150ss◦simulation
°C. The
(Worst
C. Case), tt (Typical
The simulation results
results show
Case),
show
that
and ffthe
the that
(Best
minimum
Case), at rising
minimum temperaturesis−55
rising delay is delay
479 ps and479°C
ps
the
and
and150
the°C. The simulation
maximum is 2.64 ns;results show thatfalling
the minimum the minimum
delay is rising delay
842.1 ps andisthe
479maximum
ps and theis
maximum is 2.64 ns; the minimum falling delay is 842.1 ps and the maximum is 3.4 ns.
maximum
3.4 ns. is 2.64 ns; the minimum falling delay is 842.1 ps and the maximum is 3.4 ns.

(a)
(a)

(b)
(b)
Figure 11. Simulation results of the proposed level shifter’s delay: (a) rising delay; (b) falling delay.
Figure
Figure11.
11.Simulation
Simulationresults
resultsofofthe
theproposed
proposedlevel
levelshifter’s
shifter’sdelay:
delay:(a)
(a)rising
risingdelay;
delay;(b)
(b)falling
fallingdelay.
delay.
Figure 12 simulates the dV/dt noise shielding function of the proposed level shifter
Figure 12 simulates the dV/dt noise shielding function of the proposed level shifter
at ±500 V/ns dV/dt noise. The simulation results show that when dV/dt noise is generated,
at ±500 V/ns dV/dt noise. The simulation results show that when dV/dt noise is generated,
Electronics 2023, 12, 4841 10 of 12

Electronics2023,
Electronics 2023,12,
12,xxFOR
FORPEER
PEERREVIEW
REVIEW 11 of
11 of 13
13

Figure 12 simulates the dV/dt noise shielding function of the proposed level shifter at
±500 V/ns dV/dt noise. The simulation results show that when dV/dt noise is generated,
thevoltages
the
the voltagesVVSSSand
voltages andV
and VRRRhave
V have
haveno no erroneous
noerroneous logicsignals
erroneouslogic
logic signalsduring
signals duringthe
during theperiod
the periodwhen
period whenthe
when theinput
the input
input
signalVIN
signal
signal VINisishigh,
high,the
theoutput
outputsignal
signalVOUT
VOUTisisnot
notdisturbed
disturbedby bydV/dt
dV/dtnoise,
dV/dt noise,and
noise, andthe
and thestate
the state
state
remainsunchanged.
remains
remains unchanged.Therefore,
Therefore,this
Therefore, thiscan
candemonstrate
demonstratethat
demonstrate thatthethelevel
levelshifter
level shifterproposed
shifter proposedin
proposed inthis
in this
this
papercan
paper
paper achieve
canachieve ±500
±500
achieve±500 V/ns
V/ns
V/ns dV/dt
dV/dt immunity,
immunity,
dV/dt immunity,which
which isisalso
which also suitable
suitable
is also forother
for
suitable other supply
supply
for other volt-
volt-
supply
agesand
ages andand
voltages processes. Figure
processes.
processes. Figure 13shows
Figure
13 shows
13 showsthelayout
the layout ofthe
the layout
of the proposed
ofproposed
the proposed levellevel
level shifter. Thechip
shifter.
shifter. The chip area
The area
chip
is
area
is only 127
is only
only µm ×
127×µm
127 µm 178 µm
178×µm at
178atµmthe
theat 0.18 µm
theµm
0.18 BCD
0.18BCD process.
BCD process.
µm process.

Figure
Figure 12.
Figure12. Simulation
12.Simulation results
Simulationresults of
resultsof the
ofthe dV/dt
thedV/dt noiseshielding
dV/dtnoise shieldingfunction
functionof
ofthe
theproposed
proposedlevel
levelshifter.
shifter.

Figure13.
Figure
Figure 13.The
13. Thelayout
The layoutof
layout ofthe
of theproposed
the proposedlevel
proposed levelshifter.
level shifter.
shifter.

Table 11 shows
Table shows the
the performance
performance comparison
comparison between
between the
the proposed
proposed level
level shifter
shifter and
and
previous reported
previous reported level
level shifters.
shifters. FOM
FOM isis used
used to
to evaluate
evaluate the
the performance
performance of of the
the level
level
shifterby
shifter bycombining
combiningdelay,
delay,supply
supplyvoltage,
voltage,and
andprocess
processnode.
node.ItItcan
canbe
beseen
seenfrom
fromTable
Table11
Electronics 2023, 12, 4841 11 of 12

Table 1 shows the performance comparison between the proposed level shifter and
previous reported level shifters. FOM is used to evaluate the performance of the level
shifter by combining delay, supply voltage, and process node. It can be seen from Table 1
that the high-voltage level shifter proposed in this paper has the highest dV/dt immunity
and the smallest FOM. Therefore, the proposed level shifter can still achieve sufficient
response speed and high reliability under a 200 V power supply.

Table 1. Comparison with previous work.

Latch Name [13] [14] [19] [20] This Work

Year 2016 2015 2019 2021 2023
0.18 µm 0.5 µm 0.18 µm 0.5 µm 0.18 µm
Process
CMOS UHV CMOS BCD BCD
Voltage (V) 20 700 50 30 200
Delay (ns) 0.37 20 0.53 0.66 1.49
dV/dt immunity 30 120 200 250 500
FoM 0.1 0.06 0.058 0.044 0.041
Note: dV/dt is simulated. FOM from [21]: Delay/(Process node × Voltage). Unit: ns/(µm × V).

5. Conclusions
This paper presents a high-voltage level shifter for a GaN half-bridge driver that offers
high-speed operation and high dV/dt immunity. A narrow pulse-controlled current source
and the Fast-Slewing Circuit speed up the transmission of the level shifter and reduce the
power consumption. Edge detection technology is utilized to filter the generated voltage
noise and then achieve the ultra-high dV/dt immunity of the level shifter without using
complex auxiliary circuits. In the 0.18 µm BCD process, the proposed level shifter can
achieve a propagation delay of 1.49 ns and a 500 V/ns dV/dt immunity under a 200 V
power supply, which only occupies a 0.022 mm2 active area. The FOM is very small, which
is only 0.041. The suggested level shifter can be utilized in multi-MHz converters because of
its low propagation delay and its ability to provide 500 V/ns of slewing immunity, making
it suitable for drivers of wide-bandgap power device applications.

Author Contributions: Conceptualization, M.G. and L.W.; methodology, M.G.; software, S.W.; data
curation, Y.Z.; writing—original draft preparation, M.G.; writing—review and editing, B.L. All
authors have read and agreed to the published version of the manuscript.
Funding: This research received no external funding.
Data Availability Statement: Data are contained within the article.
Acknowledgments: The authors would like to thank all members of the Institute of Microelectronics
of the Chinese Academy of Sciences (IMECAS) for their suggestions on the circuit structure of
this paper.
Conflicts of Interest: The authors declare no conflict of interest.

References
1. Yaakub, M.F.; Amran, M.; Hanim, F. Silicon carbide power device characteristics, applications and challenges: An overview. Int. J.
Power Electron. Drive Syst. 2020, 11, 2194–2202. [CrossRef]
2. Sun, C.; Xu, X.; Gui, C. High-Quality Epitaxial N Doped Graphene on SiC with Tunable Interfacial Interactions via Electron/Ion
Bridges for Stable Lithium-Ion Storage. Nano-Micro Lett. 2023, 15, 202. [CrossRef] [PubMed]
3. Rajendran, G.; Vaithilingam, C.A.; Naidu, K. Hard Switching Characteristics of SiC and GaN Devices for Future Electric Vehicle
Charging Stations. MATEC Web Conf. 2021, 335, 02007. [CrossRef]
4. Neudeck, P.G.; Okojie, R.S.; Chen, L.Y. High-temperature electronics—A role for wide bandgap semiconductors. Proc. IEEE 2002,
90, 1065–1076. [CrossRef]
5. Ahmed, M.R.; Todd, R.; Forsyth, A.J. Predicting SiC MOSFET Behavior Under Hard-Switching, Soft-Switching, and False Turn-On
Conditions. IEEE Trans. Ind. Electron. 2017, 64, 9001–9011. [CrossRef]
6. Li, K.; Evans, P.; Johnson, M. SiC/GaN power semiconductor devices: A theoretical comparison and experimental evaluation
under different switching conditions. IET Electr. Syst. Transp. 2018, 8, 3–11. [CrossRef]
Electronics 2023, 12, 4841 12 of 12

7. Sheng, K.; Guo, Q. Recent Advances in Wide Bandgap Power Switching Devices. ECS Trans. 2013, 50, 179–188. [CrossRef]
8. Cao, J.; Zhou, Z.; Wang, Z.; Tang, H.; Zhang, B. A Sub-Nanosecond Level Shifter with Ultra-High dV/dt Immunity Suitable for
WideBandgap Applications. In Proceedings of the 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville,
Spain, 12–14 October 2020; pp. 1–5.
9. Yu, S.Y.; Zhou, Q.; Shi, G.; Wu, T.Y.; Zhu, J.; Zhang, L.; Sun, W.; Zhang, S.; He, N.; Li, Y. A 400-V Half Bridge Gate Driver for
Normally-Off GaN HEMTs With Effective Dv/Dt Control and High Dv/Dt Immunity. IEEE Trans. Ind. Electron. 2023, 70, 741–751.
[CrossRef]
10. Zhang, Y.; Zhu, J.; Sun, W.; Lu, Y.; Gu, L.; Zhang, S.; Su, W. A capacitive-loaded level shift circuit for improving the noise
immunity of high voltage gate drive IC. In Proceedings of the IEEE International Symposium on Power Semiconductor Devices &
IC’s, Hong Kong, China, 10–14 May 2015; pp. 173–176.
11. Hua, Q.; Li, Z.; Qu, X.; Zhang, B.; Feng, Y. High voltage driver IC with improved immunity to di/dt induced substrate noise.
IEICE Electron. Express 2015, 12, 20150189. [CrossRef]
12. Akahane, M.; Jonishi, A.; Yamaji, M.; Kanno, H.; Sumida, H. A new level up shifter for HVICs with high noise tolerance. In
Proceedings of the 2014 International Power Electronics Conference (IPEC-Hiroshima 2014–ECCE ASIA), Hiroshima, Japan,
18–21 May 2014; pp. 2302–2309.
13. Liu, D.; Hollis, S.J.; Dymond, H.C.P.; Mcneill, N.; Stark, B.H. Design of 370-ps delay floating-voltage level shifters with 30-v/ns
power supply slew tolerance. IEEE Trans. Circuits Syst. II Express Briefs 2016, 63, 688–692. [CrossRef]
14. Yang, H.A.; Chiu, C.C.; Lai, S.C.; Chen, J.L.; Luo, H.Y. 120 V/ns output slew rate enhancement technique and high voltage
clamping circuit in high integrated gate driver for power GaN FETs. In Proceedings of the ESSCIRC Conference 2015—41st
European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 14–18 September 2015; pp. 291–294.
15. Nguyen, V.H.; Ly, N.; Alameh, A.H.; Blaquiere, Y.; Cowan, G. A versatile 200-v capacitor coupled level shifter for fully floating
multi mhz gate drivers. IEEE Trans. Circuits Syst. II Express Briefs 2021, 68, 625–1629. [CrossRef]
16. Choi, B.D. Enhancement of current driving capability in data driver ics for plasma display panels. IEEE Trans. Consum. Electron.
2009, 55, 992–997. [CrossRef]
17. Khorasani, M.; Berg, L.V.D.; Marshall, P.; Zargham, M.; Martel, S. Low-power static and dynamic high-voltage CMOS level-shifter
circuits. In Proceedings of the 2008 IEEE International Symposium on Circuits and Systems, Seattle, WA, USA, 18–21 May 2008;
pp. 1946–1949.
18. Chang, Y.K.; Fang, Y.; Kou, Y.X.; Zhang, X. A GaN-Si hybrid integrated driver for narrow-pulse and high-current LiDAR
applications. Front. Phys. 2022, 10, 1063730. [CrossRef]
19. Liu, D.; Hollis, S.J.; Stark, B.H. A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant
Floating Voltage Level Shifters for GaN SMPS. IEEE Trans. Circuits Syst. I Regul. Pap. 2018, 66, 1280–1290. [CrossRef]
20. Cao, J.; Zhou, Z.K.; Wang, Z.; Tang, H.; Zhang, B. Design Techniques of Sub-ns Level Shifters with Ultrahigh dV/dt Immunity for
Various Wide-Bandgap Applications. IEEE Trans. Power Electron. 2021, 36, 10447–10460. [CrossRef]
21. Moghe, Y.; Lehmann, T.; Piessens, T. Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 m HV-CMOS Technology.
IEEE J. Solid-State Circuits 2011, 46, 485–497. [CrossRef]

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