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CH2 Coders Decoders
CH2 Coders Decoders
The next set of combinational circuits are responsible for the transcoding operations such as the
encoders, decoders.
2.4.7. Encoders
An encoder is a combinational circuit with 2n inputs and n outputs. Only one input can be active
(logic high) at a time and the binary code equivalent to the position of this input is produced by the
outputs. It is important to keep in mind that only one input is allowed at a time and other inputs are
0. In other words, we can say that encoder encodes 2n input line with n bits.
2n inputs
N outputs
Example:
In order to understand the functionality of an encoder let us design a 4 x 2 encoder (4 inputs and
2 outputs) as illustrated in the following figure:
I0
2 outputs
22 inputs
I1 O0
I2 O1
I3 The binary code of
the input
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I1 I0 00 01 11 10 I1 I0 00 01 11 10
I3 I2 I3 I2
00 x 0 x 0 00 x 0 x 1
01 1 x x x 01 0 x x x
11 x x x x 11 x x x x
10 1 x x x 10 1 x x x
O1 = 𝐼2 + 𝐼3 O0 = 𝐼1 + 𝐼3
The logic expressions for this system are:
O0 is 1 if I2 = 1 OR I3 = 1
O1 is 1 if I0 = 1 OR I1 = 1
The logic circuit is
Similarly, a decimal to BCD encoder can be achieved by using a 16 to 4 encoder, but only
considering 10 inputs out of the 16 available inputs (because in decimal we have numbers from 0
to 9). Then each input when activated will give an output the correspond to the BCD code.
Here is the truth table:
2
I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 O3 O2 O1 O0
0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 0 0 0 0 1 0 0 0 0 1 0
0 0 0 0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 0 1 0 0 0 0 0 1 0 0
0 0 0 0 1 0 0 0 0 0 0 1 0 1
0 0 0 1 0 0 0 0 0 0 0 1 1 0
0 0 1 0 0 0 0 0 0 0 0 1 1 1
0 1 0 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 0 0 0 1 0 0 1
I3 I2 I1 I0 O1 O0
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 1 1
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1 0 0 1 1 1
1 0 1 0 1 1
1 0 1 1 1 1
1 1 0 0 1 1
1 1 0 1 1 1
1 1 1 0 1 1
1 1 1 1 1 1
In order to get the logic expression let us use the k-maps for both outputs:
I1 I0 00 01 11 10 I1 I0 00 01 11 10
I3 I2 I3 I2
00 0 0 1 1 00 0 0 0 0
01 0 0 0 0 01 1 1 1 1
11 1 1 1 1 11 1 1 1 1
10 1 1 1 1 10 1 1 1 1
O0 = 𝐼3 + 𝐼̅2 𝐼1 O1 = 𝐼3 + 𝐼2
And the logic circuit for a 4x2 priority encoder is:
Also, to solve the problem of when no input is activated the output gives zero which is incorrect,
the priority encoder sometime include an additional output that is always activated for all valid
inputs and is 0 if all inputs are zero to confirm the situation.
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The modified truth table for this priority encoder is:
I3 I2 I1 I0 O1 O0 V
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1
And the modified logic circuit is:
2.4.9. Decoders
A decoder is a combinational circuit that has N inputs and maximum of 2N outputs such that
outputs are ≤ 2N. It takes an input code and produces an output based on that code. It converts
coded information into a more understandable format. It is usually used in digital machines to
convert from binary codes and activate a specific output that corresponds to the decimal value of
the input combinations. 2n
outputs
N
inputs
The binary
code of the
E
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In order to understand the functionality of a decoder, let us take
the example of a decoder with 2 inputs and 4 outputs. E stands
for enable which when set to 0, the decoder gives all zeros no
matter what the input is (it is disabled), and when set to 1, the
decoder functions (it is enabled).
E I1 I0 O3 O2 O1 O0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
From the truth table we can find the logic expressions of the outputs as follows:
O0 = 𝐸𝐼̅1 𝐼̅0 O1 = 𝐸𝐼̅1 𝐼0 O2 = 𝐸𝐼1 𝐼̅0 O3 = 𝐸𝐼1 𝐼0
And the logic circuit for this decoder is:
As an additional example, let us take the 3x8 decoder (active high), with 3 inputs and 23 = 8
outputs.
E I2 I1 I0 O0 O1 O2 O3 O4 O5 O6 O7 The
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 1 0
truth table is: 1 1 1 1 0 0 0 0 0 0 0 1
The logic expressions are:
𝑂0 = 𝐸𝐼̅2 𝐼̅1 𝐼̅0
𝑂1 = 𝐸𝐼̅2 𝐼̅1 𝐼0
𝑂2 = 𝐸𝐼̅2 𝐼1 𝐼̅0
𝑂3 = 𝐸𝐼̅2 𝐼1 𝐼0
𝑂4 = 𝐸𝐼2 𝐼̅1 𝐼̅0
𝑂5 = 𝐸𝐼2 𝐼̅1 𝐼0
𝑂6 = 𝐸𝐼2 𝐼1 𝐼̅0
𝑂7 = 𝐸𝐼2 𝐼1 𝐼0
Decoders can be used as code converters where an input code corresponds to an output code
(binary-octal, binary decimal…etc.) or as an output selector where only one output among all
outputs can be activated at a time.
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They are also used in automatic washing machines in which the operation during the washing
cycle is selected using a decoder as follows:
One last example is the arithmetic logic unit (ALU) in the computer. A decoder is used to choose
among the different arithmetic and logic operation will executed.
Example:
Implement a 3 to 8 decoder using 2 to 4 decoders.
Solution:
We know that a 2 to 4 decoder has 2 inputs and 4 outputs and a 3 to 8 has 3 inputs and 8 outputs.
The number of lower order decoders required to implement higher order decoders is found
according to the following expression:
𝑅𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑙𝑜𝑤𝑒𝑟 𝑜𝑓 𝑙𝑜𝑤𝑒𝑟 𝑑𝑒𝑐𝑜𝑑𝑒𝑟𝑠
𝑡ℎ𝑒 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑜𝑢𝑡𝑝𝑢𝑡𝑠 𝑓𝑜𝑟 𝑡ℎ𝑒 ℎ𝑖𝑔ℎ𝑒𝑟 𝑜𝑟𝑑𝑒𝑟 𝑑𝑒𝑐𝑜𝑑𝑒𝑟
=
𝑡ℎ𝑒 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑜𝑢𝑡𝑝𝑢𝑡𝑠 𝑓𝑜𝑟 𝑡ℎ𝑒 𝑙𝑜𝑤𝑒𝑟 𝑜𝑟𝑑𝑒𝑟 𝑑𝑒𝑐𝑜𝑑𝑒𝑟
In our case it is: 8/4 = 2 (2 to 4 decoders at the output side)
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As for the inputs, we have two inputs only per decoder, so we need to benefit from the enable pin
as well and use as an input. (LSB inputs used as decoder inputs and MSB input used with the
enable to select the active decoder)
So here is the arrangement:
Inputs A0 and A1 are applied to both decoders and input A2 is used as an enable to choose which
decoder to activate and get the right output from.
A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
2 to 4 0 0 1 0 1 0 0 0 0 0 0
decoder 0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
2 to 4 1 0 1 0 0 0 0 0 1 0 0
decoder 1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
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Example:
Implement a 4 to 16 decoder using 2 to 4 decoders
Solution:
for a start we need 16/4 = 4 (2 to 4 decoders) to get all 16 outputs, but also we need an extra 2 to 4
decoder to control which decoder gives the required output and its output will be connected to the
enable of the four 2 to 4 decoders.
So A and B will be 0 for the first input combinations so decoder
D5 will have the first output set 1 and hence decoder D activated
for four inputs cases where C and D will change states to get
outputs Y0 to Y3 one after one. Same goes for the remaining
states.
The truth table for a 4 to 16 decoder is:
2 to 4
Decoder
D1
2 to 4
Decoder
D2
2 to 4
Decoder
D3
2 to 4
Decoder
D4
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