Lecture 4. Multi - Stage Transistor Amplifers - For Uploading

Lecture #4.
Multi-stage
Transistor Amplifiers
Mai Linh, PhD
Faculty of Electronics and Telecommunications,
VNU-University of Engineering and Technology
Email: linhmai@vnu.edu.vn ; mlinh2009@gmail.com
1
Outline
1. Single transistor amplification review
2. Introduction multistage amplifier
3. RC-coupled multi-stage amplifier
4. DC-coupled multi-stage amplifier
5. Compound configurations
6. Differential amplifier
7. RF selective amplifier
8. Wideband amplifier
9. Power amplifiers
2
CLASSIFICATION OF AMPLIFIERS
Amplifiers are classified in many ways based on different criteria as given below
I. In terms of frequency range: IV. In terms of parameter:

1. DC amplifiers. (0 Hz to 20 Hz) 1. Voltage amplifiers.
2. Audio amplifiers (20 Hz to 20 KHz) 2. Current amplifiers.
3. Radio frequency amplifiers (Few KHz to hundreds of KHz) 3. Power amplifiers.
4. Microwave amplifiers (In the range of GHz)
5. Video amplifiers (Hundreds of GHz) V. In terms of biasing condition:
1. Class A amplifier
II. In terms of signal strength: 2. Class B amplifier
1. Small signal amplifiers. 3. Class AB amplifier
2. Large signal amplifiers. 4. Class C amplifier.
III. In terms of coupling: VI. In terms of tuning:

1. Direct coupling. 1. Single tuned amplifier
2. Resistance – capacitance (RC) coupling. 2. Double tuned amplifier
3. Transformer coupling. 3. Stagger tuned amplifier.
3
4.1 Transistor Amplifier Configurations (review)
Common Emitter & Common Source
+VDD
Rin +VCC Rout
Rin Rout
Amplifier input & output R1 R1 RD
RC Cc2 Cc2
resistances (small signal Rsig Cc1 Rsig Cc1
parameters) RL RL
vsig CE vsig CS
R2 RE R2 RS
Portion Portion
due to Portion Portion due to Sometimes, we neglected ro for simplicity in
bias due to due to bias
circuitry BJT BJT circuitry calculation (because ro >> RC)
➢ Rin = R2||R1||rp for the BJT or Rin = R2||R1
Rin rp
+ gmvp
ro
Rout for the MOSFET
R1||R2 vp or RC ➢ Rout = ro||RC for the BJT or MOSFET
_ gmvgs
rp is replaced with an open circuit for the MOSFET

4
Summary of Common Emitter and Common Source Characteristics
✓ Very large voltage gain

This ones make the CE/CS
✓ Inverting voltage gain (-gmro) configuration very good for high
✓ High input impedance gain stage of amplifiers!
✓ High output impedance
5
Common Collector and Common Drain
Rin +VCC +VDD
RC Rin ✓ Unity voltage gain
RD
R1 C2 R1 CD
✓ Non-Inverting voltage gain
Cc1 Cc1
Rsig
Rout
Rsig
Rout ✓ Very high input impedance
Cc2 Cc2
vsig
R2 RE RL
vsig
R2 RS RL
✓ Low output impedance
➢ This ones make the CC/CD

▪ Collector (or Drain) is neither an input or configuration very good for
impedance transformation, ie.
output
“buffering” high impedances to low
▪ Input is Base (or Gate)
impedances!
▪ Output is Emitter ( or Source) ➢ CC/CD topologies are good for
output stages of amplifiers due to
their very low output impedance
6
Common Base and Common Gate
+VCC +VDD
Rout Rout ✓ High voltage gain
RC Cc2 RD Cc2
R1 R1 ✓ Non-Inverting voltage gain
Rin
RL
Rin
RL
✓ Very low input impedance
Rsig Rsig
C2
R2 R Cc1
C2
R2 R Cc1
✓ Very high output impedance
E vsig S vsig
➢ Input & output impedances are the

➢ Base (or Gate) is neither an input or output opposite of what is typically needed for
➢ Input is Emitter (or Source) a voltage amp. Thus, CE/CS amp. are
normally used instead of CB/CG.
➢ Output is Collector ( or Drain)
➢ The input & output impedances are
useful for current amp. but the current
gain is at best unity. Thus a current
buffer is one useful application for the
CB/CG.
7
Single-Stage Amplifiers “Terminal Gain and I/O Resistances of BJT Amplifiers”
Rsig vin vo Rsig vin Rsig vin
+
vo
vs RL vs + vs RC
RB RE RC RB Ri RL RB
vo _
_ Ri
Ri Ro Ro
Ro Ro
(a) CE (b) CC (c) CB
−  RC − g m RC RL RL Av = g m RL
Avo = Av = =
rp + (  + 1) R E 1 + g m RE 1 re + RL
+ RL  1
 R  gm Rin = re = ;
(1 +  ) RE  C + ro  gm gm
Ri = rp +  (1 +  )  rp + (  + 1) R E
Ri = rp + (  + 1) RL
ro + RC + RE rp + Rth 1 Rth Ro = RC
Ro =  +
Ro = RC || Ro = RC || 1 + g m ( rp || RE )  ro + ( rp || RE ) 1+  gm  AI 1
Ro 1 + g m RE  ro AIo =  + 1
AIo = 
Without degeneration RE: For the gain, Ri, Ro of the whole amplifier, you need to include
Simply set RE = 0 voltage/current dividers at input and output stages
8
Single-Stage Amplifiers “Terminal Gain and I/O Resistances of BJT Amplifiers”
(C-C) (C-B)
(C-E)
9
Single-Stage Amplifiers “Terminal Gain and I/O Resistances of FET Amplifiers”
C-S C-G
C-D
g m RL g m RL AV ,t = g m RL
Av ,t = − AV ,t =
1 + g m RS 1 + g m RL Ri 1
gm
Ri =  Ri = 
Ro =  ro (1 + g m RS ) 
Ro =  ro (1 + g m RE )  Ro = 1
gm AI ,t 1
AI ,t = 
RI ,t = 
Without degeneration RS:
Simply set RS = 0
For the gain, Ri, Ro of the whole amplifier, you need to include voltage/current
dividers at input and output stages 10
Inverting Amplifiers: C-E and C-S Amplifier Review
11
Follower Circuits - CC & CD
amplifiers Summary
(C-C) (C-D)
12
C-B and C-G Amplifiers
Summary
(C-B) (C-G)
13
4.2 Introduction Multistage Amplifiers
Need for Multistage Amplifiers
All the sorts of transistor amp. topologies studied (e.g., CE, CB, CC; CS, CG,
CD, source follower, etc.), each had at least one advantage character (e.g.
high open-circuit voltage gain, low output resistance, high input resistance,
etc.). And each one also owned at least one additional property (like low-
open-circuit voltage gain, low input resistance, high output resistance, etc.).
Như vậy, không thể nào

thiết kế 1 bộ khuếch đại Đúng vậy! Nhưng ta có
“hoàn hảo”? thể tạo ra những bộ
khuếch đại rất, rất tốt!
14
❖ Typical spec. for a general purpose operational amplifier Cascading

– Input resistance ~ 1MΩ multiple stages
– Output resistance ~ 100Ω
– Voltage gain ~ 100,000
of amplifiers to
❖ No single transistor amplifier can satisfy the spec. meet the spec.
❑ Usually
– An input stage to provide required input resistance
– A gain stage/middle stage(s) to provide gain
– An output stage to provide required output resistance
❑ It is important to note that the input resistance of the follow on stage
becomes the load of the previous stage
15
A multi-stage amplifier is a combination circuit

constructed using several of the basic designs
(e.g., CS, CC,…) that we have studied. Typically,
a multi-stage amplifier consists of 3 sections
+
Input Gain Output
Stage Stage Stage
-
multi-stage amplifier
16
Cascade & Cascode Amplifiers
A multistage amplifier in a cascade: the first stage's output is
connected to the second stage's input, and the second stage's output is
connected to the third stage's input, and so on. A cascade amplifier is
a two-port network with amplifiers connected in series, with each
amplifier transmitting its output to the second amplifier's input.
Fig. 1: example of cascade amplifier,
Fig. 2: example of cascode amplifier: which consists of 2 CE amplifiers
a CE stage followed by a CB stage
This cascode is a two-stage amplifier that consists of a CE stage feeding into a
common-base stage.
In modern circuits, the cascode is often constructed from two transistors (BJTs or
FETs), with one operating as a CE or CS and the other as a CB or CG. The
cascode improves input–output isolation (reduces reverse transmission), as there
is no direct coupling from the output to input. This eliminates the Miller effect
and thus contributes to a much higher bandwidth.
17
• Figure shows a three-stage amplifier connected in cascade.
The basic functions of coupling blocks:

1.To move AC voltage from one stage output to the next stage input.
2.To block DC voltage and pass AC voltage from one stage to another.
Input & output

resistances 18
Practical amplifiers usually consist of a number of stages connected in
cascade.
❖ The first (input) stage is usually required to provide
– a high input resistance
– a high common-mode rejection for a differential amplifier
❖ Middle stages are to provide
– majority of voltage gain
– conversion of the signal from differential mode to single-end mode
– shifting of the dc level of the signal
❖ The last (output) stage is to provide
– a low output resistance in order to
✓ deliver the output signal to the load without loss of gain and
✓ provide the current required by the load (power amplifiers)
19
Example 1: A two-Stage Bipolar Op-Amp
Current ❑ 1st stage or input stage (Q1, Q2) is
source Current mirrors differential-pair with single-ended
output
✓ Q3 & Q4 is current mirror (active loads):
they act as the two drain resistors RD
Differential pair, ✓ biased by current mirror Q5
single-ended
output
❑ 2nd stage (Q6 & Q7) is a CS-stage
(high gain) where the 2nd stage “load”
is the current course Q7
❑ Q8 is a current source, with Q5 & Q7
parts of current mirror
❑ A capacitor CC is included in the negative-
feedback path of the second stage.
Active loads 2nd stage
(CS)
20
Open Circuit Overall Voltage Gain
Fig.: Three-stage amplifier cascade
In the cascade amplifier,
the overall voltage gain
is the product of the
open-circuit voltage
gains of the individual
stages.
Inverting amplifier using an operational amplifier Closed-loop feedback amplifier two-port model 21
Open Circuit Overall Voltage Gain
Fig.: Two-port representation for three-stage cascaded amplifier
 RinB   RinC 
vo = AvAvi   AvB   AvC Output resistances are small (zero in the ideal case)
 RoutA + RinB   RoutB + RinC 
𝑣0
The open circuit overall gain expression: 𝐴𝑣 = = 𝐴𝑣𝐴 ⋅ 𝐴𝑣𝐵 ⋅ 𝐴𝑣𝐶
𝑣𝑖 22
Closed Circuit Overall Voltage Gain
vo
Atotal = = A1  A2  ...  An
vin
Rin
Overall voltage gain: Av = Atotal (in dB) = 20log10|Av|
Rs + Rin
Pout
Power gain in decibels = 10 log10 Ap = 10 log10
Pin
23
The bel (B) & decibel (dB) scale
❑bel scale
In the early 1920's in order to quantify the degree of signal loss
occurring in 1 mile of standard telephone cables, Bell Laboratories
came up with the bel (B) scale, named after A. G. Bell - this scale was
simply a logarithmic comparison of two signal powers (one at the start Alexander Graham Bell, Scottish-
of a cable and one at the end). American scientist and inventor,
1847–1922
 P1 
A = log10   [B]
 P2 
A denotes the relative difference between the two powers P1 and P2 on a logarithmic scale.
 P1  1
or A=10 log10    bel
 P2  10
 P1 
If we write 1/10 bel as decibel (dB), then A = 10 log10   [dB]
 P2 
Where A, again denotes the relative difference between the two powers P1 and P2 on a
logarithmic scale
24
The bel (B) & decibel (dB) scale
❑ Thus: the decibel (or dB) represents the ratio between two levels of power, or power gain.
❑ As defined, the dB is a dimensionless parameter (given that it is the ratio of two quantities
having the same unit of measure).
✓ 0 dB corresponds to a ratio of 1:1
✓ 10 dB corresponds to a ratio of 10:1
✓ -10 dB corresponds to a ratio of 1:10
❑ dB are used to measure
➢ Electric power, filter magnitude
➜ If P2 = P1 ⇒ AdB = 0 dB
➜ If P2 =2P1 ⇒ AdB = 3 dB
➜ If P2 = (1/2)P1 ⇒ AdB = −3 dB
➜ If P2 = 1,000,000P1 ⇒ AdB = 60 dB
25
Logarithmic Measure for Power
• To express a power in terms of decibels, one starts by choosing
a reference power, Preference, and writing
Power P in decibels = 10log10(P/Preference)
• Example 2:
Express a power of 50 mW in decibels relative to 1 watt.
50 × 10−3
𝑃 𝑑𝐵 = 10𝑙𝑜𝑔10 = −13 (𝑑𝐵)
1
dBm to express absolute values of power relative to a milliwatt.

dBm = 10log10(power in milliwatts / 1 milliwatt).
Ex.: 100 mW = 10log10(100/1) = 20 dBm

10 mW = 10log10(10/1) = 10 dBm
26
4.3 RC-coupled transistor amplifier
Coupling network
✓ 2-stage amplifier circuit, in CE,
common VCC.
✓ R1, R2 and RE form the biasing &
stabilization network.
✓ CE (bypass capacitor) which passes
only ac while restricting DC.
✓ RC : load impedance
✓ Cin couples ac signal to the base of
the transistor.
✓ CC (coupling capacitor) connects 2
stages and prevents DC
interference between the stages
and the shifting of operating point.
27
Operation of RC Coupled Amplifier
❑ AC input signal @ B terminal of

Q1 gets amplified and appears at
RC, then passes CC to the 2nd stage.
Then amplified AC signal again
appears across RC of Q2.
❑ 2-stage amplifier: the output phase
is same as input. Because the
phase reversal is done two times
by the two stage CE.
❑ The total gain is less than the
product of the gains of individual
stages.
28
Xc = 1/2πfc
Frequency response
For audio amplifier circuit, the voltage
gain drops off at low (< 50 Hz) and high
(> 20 kHz) frequencies whereas it is
uniform over mid-frequency range (50
Hz to 20 kHz)
Less than 50 Hz: the reactance of
coupling capacitor CC is quite high →
very small part of signal will pass from
one stage to the next stage. Fig.: frequency response of a typical RC coupled amplifier
Higher than 20 kHz: the reactance of CC is very small and it behaves as a short circuit. This increases the
loading effect of next stage and serves to reduce the voltage gain. And capacitive reactance of base-emitter
junction is low which increases the base current. This reduces the current amplification factor β.
@ 50 Hz to 20 kHz: the voltage gain of the amplifier is constant.
29
Advantages:
(i) Excellent frequency response. The gain is constant over the audio frequency range (for speech,
music etc.)
(ii) It has lower cost since it employs resistors and capacitors which are cheap.
(iii)The circuit is very compact as the modern resistors and capacitors are small and extremely light.
Disadvantages:
(i) The RC coupled amplifiers have low voltage and power gain because the low resistance
presented by the input of each stage to the preceding stage decreases the effective load
resistance (RAC) and hence the gain.
(ii) Tendency to become noisy with age, particularly in moist climates.
(iii)Impedance matching is poor. It is because the output impedance of RC coupled amplifier is
several hundred ohms whereas the input impedance of a speaker is only a few ohms. Hence,
little power will be transferred to the speaker.
30
• Example 3: RC-Coupled Transistor Amplifier with 3 stages
Find voltage
gain, input
& output
resistance?
Chapter 14
31
• Example 3: RC-Coupled Transistor Amplifier with 3 stages
❖ Input and output of overall amplifier is ac-coupled through capacitors C1 and C6.
❖ Bypass capacitors C2 and C4 are used to get maximum voltage gain from the two inverting amplifiers.
❖ Interstage coupling capacitors C3 and C5 transfer ac signals between amplifiers but provide isolation at
dc and prevent Q-points of the transistors from being affected.
❖ In the ac equivalent circuit, bias resistors are replaced by RB2 = R1||R2 and RB3 = R3||R4
32
• Example 3: RC-Coupled Transistor Amplifier with three stages
Find voltage
gain, input
& output
resistance?
The transistor M1 Kn = 10 mA/V2, VTN = -2 V,  = 0.02 V-1

parameters are given: Q2 F = 150, VA = 80 V, VBE = 0.7 V
Q3 F = 80, VA = 60 V, VBE = 0.7 V
33
Example 3: RC-Coupled Transistor Amplifier with three stages
(The capacitors have all been removed) At DC, the capacitors isolate
each individual transistor stage
from the others. So to find the
bias point of each transistor, Let
use the single transistor analysis
methods already mention.
Detailed DC calculations are

left for you to do @ home!
Fig.: dc equivalent circuit Q-POINT VALUES SMALL-SIGNAL PARAMETERS

for the three-stage M1 (5.00 mA, 10.9 V) gm1 = 10.0 mS, ro1  12.2 k
Q2 (1.5 mA, 5.53 V) gm2 = 62.0 mS, rp2 = 2.5 k, ro2  53.3 k
Q3 (1.96 mA, 8.45 V) gm3 = 78.4 mS, rp3  1.0 k, ro3  34.9 k
34
➢AC Analysis The AC solution reduces to three circuits, each of which has a
load dependent on the input resistance of the next stage!
Fig.: ac equivalent circuit for ac analysis of the three-stage
All capacitors have been replaced by short circuits. For Q2 & Q3, the base bias resistors
have been replaced by 𝑅𝐵2 = 𝑅1 ∥ 𝑅2 & 𝑅𝐵3 = 𝑅3 ∥ 𝑅4
35
➢AC Analysis
Simplified ac circuit of the three-stage
amplifier with 3 sets of parallel resistors:
RI1 = 620 Ω || 17.2 kΩ  598 Ω
RI2 = 4.7 kΩ || 51.8 Ω  4.31 kΩ
RL3 = 3.3 kΩ || 250 Ω  232 Ω , and
RL1 = RI1 || Rin2 = 598Ω || rπ2 =598Ω || 2500Ω  482Ω
Rin = RG = 1 MΩ
Rin2
RL1
Fig.: Small-signal equivalent (hybrid-p equivalent) circuit for the three-stage amplifier.
To simplify calculations, let skip all ro1, ro2, and ro3 36
Overall Voltage gain calculation:
𝑣2
The gain of the 1st stage: 𝐴𝑣1 = = −𝑔𝑚1 𝑅𝐿1
𝑣1
𝑅𝐿1 = 482 Ω , 𝑔𝑚1 = 0.01 S
→ 𝐴𝑣1 = −0.01 𝑆 × 482 Ω = −4.82
𝑣3
The terminal gain of the 2nd stage (common-emitter amplifier): 𝐴𝑣2 = = −𝑔𝑚2 𝑅𝐿2
𝑣2
RL2: total load resistance connected to the collector of Q2 → 𝑅𝐿2 = 𝑅𝐼2 ∥ 𝑅𝑖𝑛3 , 𝑅𝑖𝑛3 = 𝑟𝜋3 + (𝛽03 + 1)𝑅𝐿3
𝑅𝐿2 = 4310 ∥ 1000 + 81 × 232  3.54 (𝑘), 𝑔𝑚2 = 62.0 mS → 𝐴𝑣2 = −62.0𝑚𝑠 × 3.54𝑘Ω = −219.48
The terminal gain of the emitter follower stage:

𝑣𝑜 𝑔𝑚3 𝑅𝐿3 78.4 mS (232 Ω)
Av3 = = 𝐴𝑣3 =
1 + 78.4 mS (232 Ω)
 0.95
𝑣3 1+𝑔𝑚3 𝑅𝐿3
37
Voltage gain for the overall amplifier (signal source voltage gain) - Overall Voltage gain:
𝑣𝑜 𝑣 𝑣 𝑣 𝑣 Rin 𝑣 𝑅𝑖𝑛 𝑅𝐺 1𝑀Ω
𝐺𝑣 = = ( 𝑜 )( 3 )( 2 )( 1 ) = Av3.Av2.Av1. ( ) Where 1 = = =
𝑣𝑖 𝑣3 𝑣2 𝑣1 𝑣𝑖 RI+Rin 𝑣𝑖 𝑅𝑖𝑛 +𝑅𝐼 𝑅𝐺 +𝑅𝐼 10𝑘Ω+1𝑀Ω
1 𝑀Ω
Gv = 0.95(-219.48)(-4.82)  +995 (  Voltage gain of ~ 60 dB)
10𝑘Ω+1 𝑀Ω
Calculations of Current gain and Power gain:

vi vi −7
✓ The input current delivered to the amplifier from source vi : ii = = 4 = 9.90  10 vi
RI + Rin 10 + 10 6
v A v 995vi
✓ The current delivered to the load from the amplifier is io = o = v i = = 3.98vi
250 250 250
i 3.98vi
✓ The current gain Ai = o = 4.02  10 6
( 132 dB)
ii 9.90 10 −7 vi
P v i
The power gain of the amplifier: AP = o = o o = Av Ai = 995  4.02  10 = 3.99 10
6 9
✓ ( 96 dB)
Ps vi ii
38
v3
Calculations of Current gain & Power gain: Q2
Q3
❖ Input Resistance: Rin = RG = 1 M ie ix
4.31 k
53.3 k
RI2 ir
ro2
❖ To find the overall output resistance of the whole amplifier Rout, vx
3.3 k
RE3
use Test voltage vx by applying it to the C-C amplifier output.
vx vx
ix = ir + ie = + (1) RTh3
3300 RiE 3
Fig.: Output resistance of the 3-stage amplifier
vx rp + RTh 1 RTh
RiE = = + (2) (RiE : The resistance looking into the emitter terminal)
ix o + 1 gm o
𝑅𝑇ℎ3 (Thevenin equiv. source Res. of 3rd stage) is equal to the parallel combination of inter stage resistance
𝑅I2 & the output resistance of Q2 (𝑟02 ): RTh3 = RL2||ro2 = 4310 Ω||53300 Ω  3987.6 Ω
Case of Q3: put equ. (2) into (1)
vx 1 1
Rout = = = 61.4 ()
ix 1 1 1 1
+ +
3300 1 RTh 3 3300 1 3987.6
+ +
g m3 3 78.4 mS 80
39
4.4 DC-coupled transistor amplifier
• The coupling capacitors in the multistage amplifier limit the low-frequency
response of the amplifier and prevent its application as a dc amplifier.
• For the amplifier to provide gain at DC or very low frequency, capacitors in series
with the signal path must be eliminated. Such as amplifier is called DC-coupled, or
direct-couple amplifier.
Disadvantage: small changes in the

dc bias voltages from temperature
effects or power-supply variation
are amplified by the succeeding
stages → a significant drift in the dc
levels throughout the circuit
40
Example 4: 𝑉𝐵𝐸 𝑜𝑛 = 0.7 𝑉 and 𝛽 = 100 for both transistors. Determine Q-point?
DC analysis
Thevenin equivalent circuit

41
Example 4: Cascade small signal amplifier circuit
Vo  Ri 
Av = = g m1 g m 2 ( RC1 || rp 2 )( RC 2 || RL )  
Vs  i
R + Rs 
Ri = R1 || R2 || rp 1
Rout = RC 2
All the remain works (DC & AC analysis) must be

derived in detail at home by your own!
Fig.: Small-signal equivalent circuit 42

Drift effect in DC amplifier
The problem need be resolved in a dc coupling amplifier is suppressing of drift effects due to e.g.
temperature change. How is a temperature drift?
• Give initial conditions:

𝐼𝑐 = 2.5 𝑚𝐴, 𝑉𝐸1 = 1 𝑉; 𝑉𝐵𝐸2 = 0.7 𝑉; 𝑉𝑐𝑐 = 9 𝑉.
=> 𝑉𝑐 = 4 𝑉; 𝑉𝐸2 = 3.3 𝑉; 𝐼𝐸2 = 3.3 𝑚𝐴.
• If the temperature changes by ∆𝑻 = 𝟏𝟎𝟎 𝑪, situation?

✓ 𝑉𝐵𝐸1 changes by 2 mV/𝑑𝑒𝑔𝑟𝑒𝑒
✓ 𝐼𝑐 = 2.5 𝑚𝐴 → 𝑔𝑚1 = 100 𝑚𝐴/𝑉
✓ ∆𝐼𝑐 = 2 𝑚𝐴 → ∆𝑉𝑐 = 4 𝑉 and 𝑉𝑐 = 0 𝑉.
=> Q1 is in saturation and Q2 is cut-off
43
4.5 Compound configuration
• Darlington pair
If the input impedance of the amplifier circuit is to be only 500 KΩ or less,
then CC Configuration can be used. But if still higher input impedance is
required, a special circuit has to be used. This circuit is known as the
Darlington configuration or Darlington Pair configuration.
❖ DC analysis:
𝑉𝐶𝐶
Voltage across R2 and RE: 𝑉2 = × 𝑅2 & VE = V2 − 2VBE
𝑅1 + 𝑅2
𝑉2 − 2𝑉𝐵𝐸
Current through RE, 𝐼𝐸2 = and IE1 = IB2
𝑅𝐸 IE2 = (β1+1)(β2+1)IB1
Q1: IE1 = (β1+1)IB1 and Q2: IE2 = (β2+1)IB2
Consider β1 & β2 >> 1 → IE2  β1β2IB1

𝐼𝐸2 𝛽1 𝛽2 𝐼𝐵1
Therefore, Current Gain can be given as: 𝜷  = = 𝜷𝟏 𝜷𝟐
𝐼𝐵1 𝐼𝐵1
44
4.5 Compound configuration Sidney Darlington
(July 18, 1906 – October 31, 1997)
• Darlington pair EE American & inventor of a

transistor configuration in 1953,
the Darlington pair. He advanced
the state of network theory,
developing the insertion-loss
synthesis approach, and invented
chirp radar, bombsights, and gun
and rocket guidance.
Characteristics
The following are the important characteristics of
Darlington amplifier.
3-terminals device can be called ✓ Extremely high input impedance (MΩ).
as Darlington transistor ✓ Extremely high current gain (several thousands).
✓ Extremely low output impedance (a few Ω).
45
4.5 Compound configuration
• Darlington pair ❖ ac analysis: small signal
Vπ1 = Iirπ1 → gm1Vπ1 = gm1rπ1Ii = β1Ii and Vπ2 = (Ii + β1Ii)rπ2
The output current: Io = gm1Vπ1 + gm2Vπ2 = β1Ii + β2(1 + β1)Ii where gm2rπ2 = β2.
The overall current gain is then
𝐼
𝐴𝑖 = 𝐼𝑜 = 𝛽1 + 𝛽2 (1 + 𝛽1 ) ≅ 𝛽1 𝛽2 , note: 𝛽1 𝛽2 >> 𝛽1 + 𝛽2
𝑖
Input resistance is Ri = Vi/Ii . Vi = Vπ1 + Vπ2 = Iirπ1 + Ii(1 + β1)rπ2  Ii[rπ1 + (1 + β1)rπ2]
So that Ri = rπ1 + (1 + β1)rπ2
𝛽1 𝑉𝑇 𝐼𝐶𝑄2 𝛽2 𝑉𝑇
𝑟𝜋1 = 𝑎𝑛𝑑 𝐼𝐶𝑄1 ≅ → 𝑟𝜋1 = 𝛽1 = 𝛽1 𝑟𝜋2
𝐼𝐶𝑄1 𝛽2 𝐼𝐶𝑄2
Thus, input resistance Ri  2β1rπ2
(𝛽1 +1)𝑟𝜋2 𝑣𝑖
𝑣𝐸1 = 𝑣𝑖 𝑟 ≅ and 𝑔𝑚2 ≅ 𝛽2 𝑔𝑚1
𝜋1 +(𝛽1 +1)𝑟𝜋2 2
𝑣𝑖 𝑣𝑖 𝑔𝑚1 𝑔𝑚2 𝑔𝑚2 𝑔𝑚2 𝑔𝑚2
𝑔𝑚 𝑣𝑖 = 𝑔𝑚1 2 + 𝑔𝑚2 2 → 𝑔𝑚 = 2
+ 2
= 2𝛽2
+ 2
≅ 2
𝑅𝑜1 ≅ 𝛽𝑜1 𝑅𝑜2

Output resistance Ro 𝑅𝑜 = 𝑅𝑜2 ∥ 𝑅01
# 46 =>𝑅𝑜 ≅ 𝑅𝑜2 Fig.: small-signal equivalent circuit
4.6 Differential Amplifier
❑ A differential amplifier is an amplifier that produces outputs that are a function
of the difference between two input voltages. The differential amplifier has two
basic modes of operation: differential (in which the two inputs are different) and
common mode (in which the two inputs are the same).
❑ The differential amplifier has two inputs and two outputs.
❑ The differential-pair or differential-amplifier configuration is the most widely
used building block in analog IC design.
Vo = Ad(V1 – V2)
47
Advantages
➢ There are 2 reasons for using differential in preference to
single-ended amplifiers.
(1) Differential circuits are much less sensitive to noise and
interference than single-ended circuits.
(2) It enables us to bias the amplifier and to couple amplifier stage
without the need of bypass and coupling capacitors which are
impossible to fabricate economically by IC technology.
48
• Basic Characteristics
– Two matched transistors (Q1 & Q2) with
emitters shorted together and connected to a
current source.
– Devices must always be in active mode. Current source
– Amplifies the difference between the two
The basic BJT differential-pair configuration
input voltages, but there is also a common
mode amplification in the non-ideal case.
49
4.6 Differential Amplifier Any Two Signals have a Differential Form
Differential-mode input signal: 𝑣𝑖𝑑 = 𝑣2 − 𝑣1

𝑣 +𝑣
Common-mode input signal: 𝑣𝑖𝑐𝑚 = 1 2
2
Differential-mode gain: 𝐴𝑑
Common-mode gain: 𝐴𝑐𝑚
Output voltage: vo = AdvId + AcmvIcm
Common-mode rejection ratio (CMRR): Fig.: Representing the input signals to a

Ad differential amplifier in terms of their
CMRR = 20 log differential and common-mode components
Acm
50
V v1(t)
4.6 Differential Amplifier v2(t)

Any Two Signals have a Differential Form
▪ There are 2 signals:
t
v1(t) & v2(t)
(a)
▪ Invert the diff. representation

▪ Differential Representation: vCM(t)
Equations:
1 v1 ( t ) + v2 ( t )
v1 ( t ) = vCM ( t ) + vDM ( t ) vCM ( t ) =
2 2 t
1
v2 ( t ) = vCM ( t ) − vDM ( t )
vDM ( t ) = v1 ( t ) − v2 ( t )
2
(b)
▪ Both differential signals have vCM(t) = VDC

51
Ví dụ: có 2 tín hiệu dưới đây. Hãy vẽ dạng sóng của các tín hiệu vi sai (differential
signals vCM & vDM)?
v1(t) 1.9V vCM

1.0V 1.0V
0.1V 0.1V 1 tín hiệu đi
t t lên & 1 tín
v2(t) vDM
hiệu đi
1.9V
1.8V xuống!
0.1V
t t
-1.8V
52
BJT differential amplifiers MOS differential amplifiers
Ideal, the differential amplifier is symmetric. The differential amplifier behaves as

either an inverting or noninverting amplifier for differential input signals but tends to
reject signals common to both inputs.
53
The BJT Differential Pair: Basic Operation-1: Common-mode input
• Assume the inputs are shorted together to a common voltage, vCM,
called the common mode voltage
➢ equal currents flow through Q1 and Q2
➢ emitter voltages equal and at vCM - 0.7 in order for the devices to
be in active mode,
➢ collector currents are equal and so collector voltages are also
equal for equal load resistors,
➢ difference between collector voltages = 0
• What happens when we vary vCM?
➢ As long as devices in active mode, equal currents flow through Q1
and Q2
➢ Note: current through Q1 and Q2 always add up to I, current
through the current source
➢ So, collector voltages do not change and difference is still zero….
➢ Differential pair circuits thus reject common mode signals.
54
The BJT Differential Pair : Basic Operation-2
➢The differential pair with a large differential input

signal.
• Assume: Q2 base grounded and Q1 base at +1 V

▪ All current flows through Q1
▪ No current flows through Q2
▪ Emitter voltage at 0.3V and Q2’s EBJ not
forward biased
▪ vC1 = VCC – IRC
▪ vC2 = VCC
55
The BJT Differential Pair: Basic Operation-3
➢The differential pair with a large differential input

signal of polarity opposite to that in basic operation-2
(previous slide).
• Let Q2 base grounded and Q1 base is –1 V
▪ All current flows through Q2
▪ No current flows through Q1
▪ Emitter voltage at – 0.7V and Q1’s EBJ not
forward biased
▪ vC2 = VCC – IRC
▪ vC1 = VCC
56
The BJT Differential Pair: Basic Operation-4: Difference-mode or Difference signals
➢Assuming the bias current source I to be ideal and thus I

remains constant.
• Apply a small signal vi

– Causes a small positive I to flow in Q1
– Requires small negative I in Q2
• since IE1 + IE2 = I
– Can be used as a linear amplifier for small signals (I is a
function of vi)
• Differential pair responds to differences in the input voltage
– Can entirely steer current from one side of the diff. pair
to the other with a relatively small voltage.
57
4.6 Differential Amplifier The BJT Differential Pair
Example 5
Find vE, vC1, and vC2 in the circuit of Fig.
Assume that |vBE| of a conducting transistor
is approximately 0.7 V and that α  1.
58
Example 5 – Sol.
5-0.7
= 4.3mA
1
= +0.7V
= -5 V
= -0.7 V
= -5 + 4.3x1
= 4.3 mA
59
DC analysis
To find the Q-points, setting both input signal voltages to zero.
VBE1 = VBE2 = VBE
Assume Q1 & Q2 are matched, then
IC1 = IC2 = IC, IE1 = IE2 = IE , and IB1 = IB2 = IB,
Due to symmetry of the circuit: VC1 = VC2 = VC
The loop equation starting @ the base of Q1
𝑉𝐸𝐸 − 𝑉𝐵𝐸 loop 2IE
VBE + 2IEREE − VEE = 0 and 𝐼𝐶 = 𝛼𝐹 𝐼𝐸 = 𝛼𝐹
2𝑅𝐸𝐸
with IB = IC/βF , and VC1 = VC2 = VCC − ICRC

Also VCE1 = VCE2 = VCC + VBE − ICRC.
Thus, for the symmetrical amplifier: VOD = VC1 − VC2 = 0 V The dc output voltage is zero 60
ac analysis
With the Q-point data, we can proceed to use small-signal
analysis to characterize the voltage gain, input & output
resistances of the differential amplifier.
The ac analysis of the differential amplifier can be
simplified by breaking input sources v1 & v2 into their
equivalent differential-mode input (vid) and common-
mode input (vic) signal components.
𝑣1 + 𝑣2
vid = v1 − v2 and 𝑣𝑖𝑐 =
2
Total input voltages: v1 = vic + vid /2 and v2 = vic − vid /2

Circuit analysis is performed using superposition of the differential-mode & common-mode input
signal components.
61
ac analysis
The differential-mode & common-mode output voltages, vod & voc,
𝑣 +𝑣
vod = vc1 − vc2 and 𝑣𝑜𝑐 = 𝑐1 𝑐2
2
For the general amplifier case, voltages vod & voc are functions of both vid & vic and can be written as
𝑣𝑜𝑑 𝐴𝑑𝑑 𝐴𝑐𝑑 𝑣𝑖𝑑

𝑣𝑜𝑐 =
𝐴𝑑𝑐 𝐴𝑐𝑐 𝑣𝑖𝑐
Where 4 gains are defined:
Add = differential-mode gain
Acd = common-mode (to differential-mode) conversion gain
Acc = common-mode gain
Adc = differential-mode (to common-mode) conversion gain
For ideal symmetrical amplifier with match transistors, Acd & Adc are zero, thus
vod = Addvid  Advid and voc = Accvic  Acvic
Here, Ad & Ac are the differential mode gain & the common mode gain, respectively.
62
ac analysis
Differential-mode gain & I/O-put resistances finding
Fig.: Differential amplifier with a differential Fig.: Small-signal model for differential-mode inputs. The (ro) output
mode input signal. resistances are neglected in the calculations
63
ac analysis
• Summing currents at the emitter node:
Resistances rp & REE have their equivalent conductances virtual

gp & GEE. The base-emitter voltages are: ground
vid vid
v3 = − ve & v4 = − − ve → v3 + v4 = −2ve
2 2
Hence 𝑣𝑒 (𝐺𝐸𝐸 + 2𝑔𝜋 + 2𝑔𝑚 ) = 0 which requires 𝒗𝒆 = 𝟎 → v3 = vid /2 & v4 = – vid /2
• For a purely DM input voltage, the voltage at the emitter node is identically zero ➔ emitter node (ve)
represents a virtual ground for DM input signal. So this node causes the differential amplifier to
behave as a common-emitter (or common-source) amplifier.
64
ac analysis
vid vid
The output signal voltages are vc1 = − g m RC vc 2 = + g m RC vod = − g m RC vid
2 2
vod
The differential-mode gain Ad for a balanced output, vod = vc1 − vc2, is Ad = = − g m RC
vid vic = 0
❖ If vc1 or vc2 is used as the output, referred to as a single-ended (or ground-referenced) output,
then:
v g R A v g R A
Ad1 = c1 = − m C = d or Ad2 = c 2 =+ m C =− d
vid v =0 2 2 vid v =0 2 2
ic ic
The virtual ground @ the emitter node causes the amplifier to behave as a single-stage C-E
amplifier. (The same as for C-S amplifier in case of CMOS).
common-mode output voltages voc = 0 since vc2 = −vc1, and therefore Adc is indeed zero.
65
ac analysis
Differential-Mode Input Resistance
❖ The differential-mode input resistance Rid represents the small-signal
resistance presented to the full differential-mode input voltage appearing
between the two bases of the transistors.
vid
Rid = = 2rp
ib1
❖ The differential-mode output resistance Rod (if vid is set to zero, then
gmv3 and gmv4 are zero):
Rod = 2(RC||ro)  2RC
Thus, single-ended outputs Rout  RC
66
The BJT Differential Pair
ac analysis
Common-mode gain & Input resistances finding
To find the CM characteristics and discover that it
tends to reject CM input signals, a very useful
property!
Purely CM input signals are applied to the

differential amplifier. For this case, both
sides of the amplifier are completely
symmetrical.
Thus, the two base currents, the emitter
currents, the collector currents, and the two
collector voltages must be equal.
67
ac analysis
For small signal model:
vic = ib rp + ve = ib  rp + 2 (  o + 1) REE 
vic
 ib =
rp + 2 (  o + 1) REE
The output voltage at collectors:

−  o RC
vc1 = vc 2 = −  oib RC = vic
rp + 2 (  o + 1) REE
2 (  o + 1) REE
The voltage at the emitter: ve = 2 (  o + 1) ib REE = vic  vic
rp + 2 (  o + 1) REE
68
ac analysis Common-mode gain & Input resistances finding
voc  o RC R
So with the CM output voltage 𝑣𝑜𝑐 , the gain: Ac = =−  − C (for β𝑜 >> 1)
vic vid = 0
rp + 2 (  o + 1) REE 2 REE
I C RC V /2 VCC V
Ac = −  CC   CC where it is assumed that F = 0
2 I C REE 2 I E REE 2 (VEE − VBE ) 2VEE and ICRC = VCC / 2.
❑ The differential output voltage vod is identically zero because the

voltages are equal at two collectors: vod = vc1 – vc2 = 0.
So, the CM conversion gain for a differential output is also zero:
vod
Acd = =0
vic vid = 0
 1 1 
✓ If ro is included Ac RC  − 

 oor 2 REE 
69
ac analysis
Common-mode input resistance
vic rp + 2 (  o + 1) REE rp
Ric = = = + (  o + 1) REE
2ib 2 2
Common-mode rejection ratio (CMRR), characterizes the ability of an amplifier to
amplify the desired differential-mode input signal and reject the undesired common
mode input signal.
𝐴𝑑𝑚 𝐴 𝑑 Τ2 1 1
CMRR = = = 𝑔 𝑅 × = 𝑔𝑚 𝑅𝐸𝐸
𝐴𝑐𝑚 𝐴𝐶 2 𝑚 𝐶 𝑅𝐶 Τ2𝑅𝐸𝐸
By writing gm in terms of the collector current IC

CMRR = 40ICREE = 20(2IEREE) = 20(VEE − VBE)  20VEE
70
4.6 Differential Amplifier Differential Amplifier with MOSFET
MOSFETs provide very high-input resistance and are often used in differential
amplifiers implemented in CMOS technologies.
For DC analysis, using half-circuits,
the amplifier is redrawn in
symmetrical form
Each of the transistors are in
saturation, then drain current:
I k
I D = SS = n (VGS − Vtn )
2
2 2
VD1 = VD 2 = VDD − I D RD , VG = 0
VDS = VDD − I D RD + VGS
vGS 1 = v1 − vS & vGS 2 = v2 − vS
The differential input voltage as: vGS 1 − vGS 2 = v1 − v2  vD

71
Now, doing some algebra I KI K 2
iD1 = + vD 1− vD
with all of the above 2 2 2I
equations to find the drain (*)
I KI K 2
current for each transistor: iD 2 = − vD 1− vD
2 2 2I
Note this result shows that the drain

current of each transistor is dependent
only on the differential signal --the
drain currents are independent of the
common-mode! Fig.: The MOSFET differential pair for the
purpose of deriving the transfer characteristics
2I 2I
❖ If vD = 0, then ❖ If vD  − ❖ If vD  +
K K
I
iD 1 = iD 2 = Q1 is cutoff Q2 is cutoff
2
Q2 is saturation: iD2 = I Q2 is saturation: iD1 = I
72
2I 2I
❖ If −  vD  +
K K
2 transistors are in saturation, and the drain current
through each transistor is described using equ (*) in
previous slide. Plotting these equations, we find:
Fig. Normalized plots of the currents in a MOSFET

differential pair. Here, VOV is the overdrive voltage at
which Q1 & Q2 operate when conducting drain currents
equal to I/2,
73
❑Read at home the following sections (book: Microelectronic Circuit

Design, 5th Ed., by C. JAEGER • TRAVIS N. BLALOCK):
In the chapter 15
➢ 15.1.12 DIFFERENTIAL-MODE INPUT SIGNALS
➢ 15.1.13 SMALL-SIGNAL TRANSFER CHARACTERISTIC FOR THE MOS DIFFERENTIAL AMPLIFIER
➢ 15.1.14 COMMON-MODE INPUT SIGNALS
74
CS with a Current source
+VDD The small-signal
Nguồn
circuit must be… vO = ?
I tín hiệu RS
Q1
Nguồn vO(t) vs +
-
tín hiệu RS
Q1
vs +
-
VDC All real current source (similar as with voltage source)
has a source resistance roc.
A more accurate current source model is: I roc
Ideally, roc = . In fact, good current source has roc is
about 100 k → we consider it is very large (ignore it).
But…
75
CS with a Current source +VDD
I roc
But there are some circuits where this resistance Nguồn
tín hiệu RS vO(t)
makes quite a difference. Q1
Thus, a more accurate amplifier circuit schematic is: vs +
-
VDC
Therefore, with the hybrid-pi model: Small-signal circuit

(deactivated DC)
roc
G1 id
D1 vO(t)
vO(t)
+ +
vS vgs1 ro1 roc +
Q1
_ _ gmvgs1 v s-
S1
76
I
But, we implement a current source using a current mirror. vO(t)
Nguồn
What is the output resistance ro of current mirror? tín hiệu RS
Q1
Let design a PMOS current mirror as below: vs +
-
current mirror (acts VDC
likes current source)
VSS _ VSS What is the source
_
resistance ro of this
VGS3 VGS2
Q3 + + current source?
Q2
Iref vO(t)
Transistors Q2, Q3, and Q4 form the current
Q1
Q4 + mirror that acts as the current source.
vs(t) - Note: Q4 is an enhancement load—it acts as the
resistor in the current mirror Ckt.
VDC
77
VSS _ _ VSS
Let’s analyze the small-signal circuit that _
amplifier and find out! Q3 + + VDS2 +vds2
Q2 +
➢ For Q1 there will be small-
signal voltages vgs1(t) & vds1(t), Iref +0
+ vO(t)
along with id1(t). Q4
VDS4 +0 Q1 +
➢ Same as Q2: a small-signal + _ VDS1+vds1
+ + _
voltage vds1(t) and current id2(t) _
vs(t) -
_
will appear.
➢ For the rest of the voltages & VDC
currents in this circuit, the
small-signal component is zero!
We must consider the MOSFET
output resistance of Q2!
78
CS with a Current source S2
_ _
The small-signal drain current for a PMOS device: vgs2 vds2 ro2
vds 2 gmvgs2
id 2 gm2 v gs 2 + +
ro2 G2 D2 id
vds 2
Since vgs2 = 0, → id 2
ro2
S2
S2 _ _
_
vgs2=0 vds2 ro2
vds2 ro2 or, simplifying further + +
+ vds2
id = r G2 D2 id
o2
D2
79
Finally, the small-signal model of the entire current mirror is simply the
output resistance of the MOSFET Q2 !
Điện trở đầu

ro2 roc ra của mạch
gương dòng
vO(t) vO(t) bằng điện trở
Q1 Q1 đầu ra của
+ +
v s- v s- riêng
MOSFET Q2 !
Fig. in slide #77
80
Transistor
Q2 Iref ro2 = 1
VSS _
_
VSS ||Iref
VGS3 VGS2 vO(t)
Q3 + + Q2 Q1
vs +
-
Iref vO(t)
VDC
Q1
Q4 +
vs(t) -
Avo gm1 ro1 ro2 2Kn1 Iref ro1 ro2
VDC
W 
The open-circuit voltage gain is:
Avo = − 2  n Cox   I ref ( ro1 ro 2 )
 L 1
81
Depletion and Enhancement loads
Resistors occupy huge space on IC substrates. How come?
→ Engineers came up with a brilliant idea to
replace the resistor with a transistor. D-MOSFET
E-MOSFET
We can make a two terminal device from a +

+
MOSFET by v v
-
➢ connecting the gate & the drain (for -
i
Enhancement MOSFET) i
➢ or connecting the gate & the source (for
Depletion MOSFET)
+
Again, how v
_
come? i
Active resistor
82
Depletion loads: using Depletion MOSFETs
Remember: a D-MOSFET has conducting channel implanted, so we do not need to
induce a channel)
+ VGS = 0 > Vt Therefore, a common source amplifier can be
v → D-MOSFET can never be constructed using either a resistor or, in the context of
- in cutoff—the channel is an integrated circuit, a depletion load.
i always conducting!
VDD VDD I i=id

1 G1 D1
ro = +
RD Q2 I vgs_=0 ro
+
vds= v
vO vO gmvgs
_
vI vI S1
Q1
We have ignored body effects!
83
Depletion and Enhancement loads +
i v
Enhancement loads: using Enhancement MOSFETs -
Remind: we do need to induce a channel for E-MOSFETs Resistor i
Resistors & enhancement loads are far from exactly the same, but:
Enhancement
1) They both have i = 0 when v = 0
load
2) They both have increasing current i with increasing voltage v
v
For the enhancement
load amplifier, the
load line is replaced
with a load curve
v = VDD - vDS
The transfer function of this circuit
84
Enhancement loads: using Enhancement MOSFETs
1 W 
*) DC Analysis Q2: If VDS2 > VGS2 - Vt → I = nCox   (VGS 2 − Vtn )
2
VDD VDD 2  L 2
Q2 W  1
RD *) Determine gm2 & ro2: g m =  n Cox   (VGS − Vtn ) ; ro 2 =
vO vO  L 2 I
vI vI
Q1 *) ac analysis Q2 (the small-signal circuit of Q2):
G2 D2 i=id
+
+
v vgs2
_
ro2
- gmvgs2
i S2
Small-signal equivalent ckt. for an enhancement load
85
Enhancement loads – using Enhancement MOSFETs
Finally, the Small signal behavior
of an enhancement load is
Quan trọng là mạch bên trái của tôi là
mạch tương đương tín hiệu nhỏ cho tải E-
MOSFET.
i
Do vậy, khi phân tích mạch tín hiệu nhỏ +
của bất kỳ bộ khuếch đại MOSFET nào, gmv v ro
anh/chị chỉ cần thay thế tất cả các tải E
MOSFET bằng mô hình tín hiệu nhỏ này. _
Enhancement Load
Small-Signal Model
86
CS Amplifier Enhancement loads VDD
Q2
How to get the small-signal open-ckt. voltage
gain, input & output resistance of this amp.? vO(t)
vI
+ Q1
vs(t) -
Chuyện nhỏ! Làm đúng theo các bước đã học:
VG
DC analysis; compute small-signal parameters; ac
analysis; …
VDD
Q2 ID Step 1 – DC Analysis VGS1 = VG – 0 = VG; VDS2 = VGS2, and VDS1 = VDD – VDS2
1 W  1
Q1 & Q2 are in saturation, so I D = Cox   (VGS 1 − Vt1 ) = k1 (VG − Vt1 )
2 2
Q1
VO 2  L 1 2
1
and Q2 also has current: I D = k2 (VGS 2 − Vt 2 )
2
VG 2
ID
87
VDD
CS Amplifier Enhancement loads Q2 ID
Step 1 – DC Analysis (cont.)
k k
VO
VGS 2 = 1 (VG − Vt1 ) + Vt 2 ; VDS 2 = 1 (VG − Vt1 ) + Vt 2
Q1
k2 k2
VG
k ID
VDS 1 = VDD − Vt 2 − 1 (VG − Vt1 ) ;
k2
Note: Q1 & Q2 are in saturation if VDS1 > VGS1 – Vt1 and VGS1 > Vt1
Step 2 – Compute small-signal parameters: Each transistor has its own small signal parameters
W  1
g m1 =  nCox   (VG − Vt1 ) ; ro1 =
 L 1 1 I
W  1
gm2 =  n Cox   (VG − Vt 2 ) ; ro 2 =
 L 2 2I
88
VDD
CS Amplifier Enhancement loads Q2
Step 3 – ac analysis for the small-signal circuit vO(t)
➢ DC sources were turned off + Q1
➢ Q1 & Q2 were replaced with their equivalent small-signal models, vs(t) -
respectively.
Then, redraw the small-signal ckt. like this…

G2
G1 D1 id S2 vO(t)
+
+ + _ gm2vgs2 ro2
vS(t) vgs1 ro1 vgs2
_ _ vgs2 ro2 _
gm1vgs1 gm2vgs2 + S2
S1 G2
G1 id vO(t)
D1
+ +
And then, simplify it as much as possible… vS(t) vgs1
_
ro1
_ gm1vgs1
S1
89
CS Amplifier Enhancement loads
Step 3 – ac analysis for the small-signal circuit G1 vO(t)
❖ As a result, the simplified small-signal ckt.: + + (gm1vgs1 - gm2vgs2)
_
vS(t) vgs1 ro1||ro2
_ _ vgs2
+
❖ This is a familiar ckt., so we have: S1
vS(t) = vgs1; vgs2 = - vO(t)
vO(t) = -(gm1vgs1 – gm2vgs2)(ro1||ro2)
Avo =
vO
=
− ( ro1 ro 2 ) g m1 −g −g
 m1 ; Now, let take: Avo = m1 = −
2k1 I D k
=− 1 =−
(W L ) 1
(I)
vS 1 + ( ro1 ro 2 ) g m 2 gm2 gm2 2k 2 I D k2
(W L ) 2
Equ. (I) means that we can adjust the MOSFET channel geometry to set the small-signal
gain of this amplifier!
❖ Small-signal input resistance: Rin = 
❖ Small-signal output resistance: Rout = ro1||ro2

90
4.7 RF selective amplifier (further reading)
• In radio communication, waves have frequencies of the order of hundreds of kHz or higher. Amplifiers
operating in this frequency range is called high-frequency or RF ones (Radio Frequency Amplifier).
• Information in this waveband is usually set in a narrow frequency range around a certain frequency
called the carrier. In this case, the amplifier should only is required to amplify the received signals
about the carrier’s frequency or the neighboring, and then remove the other ones which are far from
that narrow range. Such amplifier is called the selective amplifier.
• The resonant frame LC has the selective character about the critical frequency w = 1 /LC is the
good selection using it as a resonant load for a transistor-based amplifiers.
91
RF selective amplifier
Scheme of an input stages of the RF receiver
92
4.8 Wide-Band Amplifier (further reading)
• Such a video amplifier requires a wideband to 6.5 MHz. Meanwhile the frequency response of a
typical RC-coupled amplifier is limited at some tens of kHz. It is only uniform over mid-frequency
range (e.g.50 Hz to 20 kHz) but is dropped off at two ends of bandwidth:
✓ Lower the low-range, signal is attenuated due to the high-impedance of coupled capacitors.
✓ Over the high-range, signal is shunt-dropped due to parallel parasitic capacitors in circuit.
93
4.9 Power Amplifiers
What is a Power Amplifier?
A power amplifier is an electronic amplifier designed to increase the
magnitude of power of a given input signal. The power of the input
signal is increased to a level high enough to drive loads of output devices like speakers,
headphones, RF transmitters etc. Unlike voltage/current amplifiers, a power amplifier is
designed to drive loads directly and is used as a final block in an amplifier chain.
Fig.: Chain of an arbitrary audio amplifier

Types of Power Amplifiers
Depending on the type of output device that is connected, power amplifiers are divided into the
following three types:
➢ Audio Power Amplifiers (few milliwatts to thousands of watts)
➢ RF Power Amplifiers
➢ DC Power Amplifiers 94
4.9 Power Amplifiers
95
4.9 Power Amplifiers (PAs)
➢ PAs are large-signal amplifiers.
➢ PAs are based on the percentage of the input cycle for which the amplifier operates in its linear
region. Each class has a unique circuit configuration because of the way it must be operated. The
emphasis is on power amplification.
➢ PAs are normally used as the final stage of a communications receiver or transmitter to provide
signal power to speakers or to a transmitting antenna. BJTs are used to illustrate power amplifier
principles.
PAs designed to amplify analog signals come under A, B, AB or C category

• Class A power amplifiers
• Class B power amplifiers
• Class AB push-pull amplifiers
• Class C power amplifiers
(Textbook 2: Thomas L. Floyd, Electronic devices, 9th edition, Prentice Hall, Chap. 7)
96
4.9 Power Amplifiers Classification of Output Stages
Class A
❖ Class A: the transistor conducts
Class B
for the entire cycle of the input
signal
❖ Class B: the transistor conducts
for only half the cycle
❖ Class AB: conduction cycle is
greater than 180º and less than
360º
Class AB Class C – Used for opamp output stage and
audio power amplifiers
❖ Class C: conduction cycle is less
than 180º
– Used for radio-frequency (RF) power
amplifications (mobile phones, radio
Collector or Drain current waveforms and TV)
of different output stages 97
AC & DC Load lines in BJT transistor amplifiers
DC Load Line
When the transistor is given the bias and no AC
signal is applied at its input, the DC load line
drawn under such conditions, can be
understood as DC condition.
VCE = VCC − ICRC
98
AC & DC Load lines in BJT transistor amplifiers
ac Load Line
Whereas the ac load line gives the peak-to-peak voltage, or the
maximum possible output swing for a given amplifier.
VCE = (RC||RL)×IC , let rC = RC||RL RB
BJT work as an amplifier: The Q point is so chosen that the

maximum input signal excursion is symmetrical on both negative
and positive half cycles.
→ Vmax = VCEQ and Vmin = -VEQ
VCEQ is the emitter-collector voltage @ Q point.
Current IC @ the saturation point (A): IC(sat) = ICQ + (VCEQ/rC)
Voltage VCE @ the cutoff point (B): VCE(off) = VCEQ+ ICQrC
99
AC and DC Load Line
When ac and DC Load lines are represented
in a graph, it can be understood that they are
not identical.
DC Load Line: For C-E transistors, it is
straight line. It is on output characteristic
curve (RC is the resistor in collector circuit)
ac Load Line: It is straight line through the
quiescent operating point having slope
corresponding to AC load resistance
rC = RC || RL.
100
4.9 Power Amplifiers Class A power amplifiers
• Operating in linear region.
• Q-Point is centered on the AC load line
Transistor driven into cutoff by a further increase in input amplitude

Amplitude of Vce and Ic limited by cutoff
101
Class A power amplifiers
2
𝑃𝐿 𝑉𝐿2 𝑉𝑖𝑛
• Power Gain: 𝐴𝑝 = where 𝑃𝐿 = and 𝑃𝑖𝑛 = Biasing resistors
𝑃𝑖𝑛 𝑅𝐿 𝑅𝑖𝑛 for BJT Amp.
𝑉𝐿2 𝑅𝑖𝑛 𝑅𝑖𝑛

𝐴𝑝 = 2 𝐴𝑝 = 𝐴2𝑣 Where 𝑅𝑖𝑛 = 𝑅1 ∥ 𝑅2 ∥ 𝑟𝜋
𝑉𝑖𝑛 𝑅𝐿 𝑅𝐿
• Example 6: Common – Collector Amplifier has an input resistance 10k

and a load resistance of 100 ohm. Since a CC amplifier has a voltage
gain (Av) of approximately 1, what is the power gain?
𝑅𝑖𝑛 10𝑘
𝐴𝑝 = 𝐴2𝑣 =1 2 = 100
𝑅𝐿 100
102
Class A power amplifiers
• DC Quiescent Power: Power dissipation of transistor with no signal input (by Q-Point)
𝑃𝐷𝑄 = 𝐼𝐶𝑄 𝑉𝐶𝐸𝑄
PDQ is the maximum power that a class A amplifier must handle.
• Output Power: C-E Amplifiers with a centered Q-Point
2
✓ maximum peak voltage swing 𝑉𝑐 𝑚𝑎𝑥 = 𝐼𝐶𝑄 𝑅𝑐 → rms value: 𝑉
2 𝑐 𝑚𝑎𝑥
𝑉𝐶𝐸𝑄 2
✓ maximum peak current swing 𝐼𝑐 𝑚𝑎𝑥 = → rms value: 𝐼
𝑅𝐶 2 𝑐 𝑚𝑎𝑥
2 2
✓ 𝑷𝒐𝒖𝒕 𝒎𝒂𝒙 = 𝑉 × 𝐼 = 𝟎. 𝟓 𝑰𝑪𝑸 𝑽𝑪𝑬𝑸
2 𝑐 𝑚𝑎𝑥 2 𝑐 𝑚𝑎𝑥
• DC power: 𝑃𝐷𝐶 = 𝐼𝐶𝐶 𝑉𝐶𝐶 = 2𝐼𝐶𝑄 𝑉𝐶𝐸𝑄 (Supply voltage is at least 2VCEQ)
• Power efficiency:
Power Delivered to Load 𝑃 0.5𝐼 𝑉
In practice, max is
max ≡ Power Drawn from Supply = 𝑃𝑜𝑢𝑡 = 2𝐼 𝐶𝑄𝑉 𝐶𝐸𝑄 = 0.25 (=25%) less about 10%
𝐷𝐶 𝐶𝑄 𝐶𝐸𝑄
Maximum efficiency
103
of class A
Reference: Electronic Devices, 9th Ed.
Class A power amplifiers by Thomas Floyd. Chapter 7.
Example 7
• Determine the voltage gain and the power gain of the class A power amplifier in
below figure. Assume 𝛽1 = 𝛽2 = 𝛽3 = 200.
104
Example 7: Sol.
1st stage (Q1) is a voltage-divider biased common-emitter with a resistor (RE1). The 2nd stage (Q2 & Q3)
is a Darlington voltage follower configuration. The speaker is the load.
1st stage: The ac collector resistance Rc1  RC || (R3 || R4) = 4.7 k || 5.6 k || 22 k = 2.29 k
 R2   10 
VB    CC    12 = 1.82 (V)
V =
 R1 + R2   66 
V − 0.7 1.82 − 0.7
IE = B = = 1.78 (mA)
RE1 + RE 2 628
25 mV 25 mV
re( Q1) = = = 14 
IE 1.78 mA
Rc1 2.29 103
Voltage gain of the first stage with the loading of the 2nd stage Av1 = − =− −27.93

RE1 + re (Q1) 68 + 14
Total input resistance of the 1st stage Rin (tot)1 = R1 || R2 ||  ac (Q1) ( RE1 + re(Q1) )
= 56 k  ||10 k  || 200(68  + 14 ) = 8.4 k 
105
Example 7
2nd stage: The voltage gain of the Darlington emitter-follower: Av2  1
Overall amplifier: The overall voltage gain is the product of the first and second
stage voltage gains.
Av(tot) = Av1Av2  (– 27.9)(1) = – 27.9
Power gain:
 Rin (tot)1  2  8.4 k  
Ap = A2
  = (−27.9)    817330
 8 
v (tot)
 RL 
106
Example 8
• Determine the efficiency of the power amplifier in Example 7?
107
Example 8 – Sol.: by Thomas Floyd. Chapter 7.
The efficiency is the ratio of the signal power in the load to the power supplied by
the dc source. The input voltage is 50 mV peak-to-peak which is 35.4 mV rms.
→ The input power: v 2 (35.4 mV )
Pin = in
= 149 nW
Rin 8.4 k 
The output power Pout = Pin Ap = (149 nW )  817330 = 122 mW
Most of the power from the dc source is supplied to the output stage. The current in the output stage
can be computed from the dc emitter voltage of Q3.
 22 k  
VE ( Q 3)     (12 V ) − 1.4 V = 8.2 V
 27.6 k  
VE ( Q 3) 8.2
I E ( Q 3) = = 0.25 ( A)
RE 33
Neglecting the other transistor and bias currents, which are very small, the total dc supply current is about
0.25 A. The power from the DC source PDC = ICCVCC = (0.25 A)(12 V) = 3 W
Pout 122 mW
➔ Efficiency of the amplifier  = = 0.04 Only 4% !
PDC 3W
108
Class B & Class AB Push-Pull Amplifiers
• Class B Amplifiers is in cutoff for 180𝑜 .
• Q-Point is at cutoff: amplifier is biased at the cutoff point:
𝐼𝐶𝑄 = 0; 𝑉𝐶𝐸𝑄 = 𝑉𝐶𝐸(𝑐𝑢𝑡𝑜𝑓𝑓) .
• Only conduct for positive half of cycle.
Emitter-Follower circuit
109
Class B & Class AB Push-Pull Amplifiers
• Class B push-full operation
❶ Transformer coupled push-pull amplifiers:
Q1 conduct during the
positive half-cycle; Q2
conducts during the negative
half-cycle. The two halves
are combined by the output
transformer.
The positive power supply
VCC is connected to the
center tap of the output
transformer.
110
Class B and Class AB Push-Pull Amplifiers
❷ Complementary Symmetry Transistors (matching pair of npn/pnp BJTs):
Notice: this case, there is no

dc base bias voltage (VB = 0).
111
Trouble:
Crossover distortion: Q1 & Q2 are off
due to the input signal voltage < VBE.
➔there is a time interval between
the positive and negative
alternations of the input when
neither transistor is conducting.
➔Make distortion in the output
waveform is called crossover
distortion (méo xuyên tâm)
112
• Biasing Push-Pull Amplifier (Class AB Operation)
To eliminate crossover distortion, the biasing is adjusted to just overcome
the VBE of the transistors → leads to class AB.
D1 & D2 are closely matched to the characteristics of Q1 & Q2, → the current
in the diodes and the current in the transistors (ICQ) are the same; named as
current mirror.
Biasing the push-pull amplifier 0.7 V is applied to the input transformer’s secondary
113
• ac Operation
✓ Q-Point is slightly above cutoff
✓AC saturation current for two-supply operation with
push-pull amplifier:
𝑉𝐶𝐶
𝐼𝑐(𝑠𝑎𝑡) =
𝑅𝐿
Load lines (of Q1) for a complementary

symmetry push-pull amplifier. AC load line for Q1
114
Example 9
• Determine the ideal maximum peak output voltage and current for
the circuit shown in below figure.
115
Example 9 – Sol.
The ideal maximum peak output voltage is
Vout ( peak )  VCEQ VCC = 20 V
The ideal maximum peak current is

VCC 20 V
I out ( peak ) I c ( sat ) = 133 mA
RL 150 
The actual maximum values of voltage and

current are slightly smaller!
116
• Single-Supply Push-Pull Amplifier
Push-pull amplifiers using complementary symmetry
transistors can be operated from a single voltage source
The bias is set to force the output emitter voltage to be VCC / 2
C1 , C2 & C3 capacitors for the input and output is necessary to
block the DC bias voltage from the
source and the load resistor.
Since Q1 & Q2 are slightly conducting at zero

input, no information in the input signal is
lost at the output during the zero-crossing of
the input signal → cross-over distortion is
eliminated at a cost of slightly reduced
efficiency.
117
• Single-Supply Push-Pull Amplifier
❑ Advantages of Class AB power amplifier
✓ No cross over distortion.
✓ No need for the bulky coupling transformers.
✓ No hum in the output.
❑ Disadvantages of Class AB power amplifier
✓ Efficiency is slightly less when compared to Class B configuration.
✓ There will be some DC components in the output as the load is
directly coupled.
✓ Capacitive coupling can eliminate DC components but it is not
practical in case of heavy loads.
118
Example 10
• Determine the maximum ideal peak values for the output voltage and
current in below figure:
119
Example 10 – Sol.
The maximum peak output voltage
VCC 20
Vout ( peak ) VCEQ = = = 10 (V )
2 2
The maximum peak output current

VCEQ 10
I out ( peak )  I c ( sat ) = = = 200 ( mA)
RL 50
120
Class B and Class AB push-pull Amplifiers
• Class B/AB Power
✓ Maximum Output Power maximum average output power:
Pout = Iout(rms)Vout(rms) = 0.707Ic(sat)×0.707VCEQ = 0.5Ic(sat)VCEQ
VCEQ = VCC/2 => Pout = 0.25Ic(sat)Vcc
✓ DC Input Power (comes from the VCC supply):
PDC = ICCVCC and ICC=Ic(sat)/𝜋 (because each transistor operates a half-cycle of signal)
𝐼𝑐(𝑠𝑎𝑡)𝑉𝐶𝐶
=> 𝑃𝐷𝐶 =
𝜋
𝑃𝑜𝑢𝑡 0.25𝐼𝑐(𝑠𝑎𝑡) 𝑉𝐶𝐶 much higher efficiency
✓ Efficiency: 𝜂𝑚𝑎𝑥 = = = 0.25𝜋 ≈ 79% when compare to class A!
𝑃𝐷𝐶 𝐼𝑐(𝑠𝑎𝑡)𝑉𝐶𝐶 Τ𝜋
• Input Resistance
input resistance for the emitter-follower Rin =  ac ( re + RE ) || R1 || R2
Since RE = RL, Rin =  ac ( re + RL ) || R1 || R2
121
Example 11
• Find the maximum ac output power and
the dc input power of the amplifier in
figure.
122
Example 11 – Sol.
The ideal maximum peak output voltage
VCC 20
Vout ( peak ) VCEQ = = = 10 (V )
2 2
The maximum peak output current
VCEQ 10
I out ( peak ) I c ( sat ) = = = 1.25 ( A)
RL 8
The ac output power and the dc input power
Pout = 0.25 I c ( sat )VCC = 0.25 1.25  20 = 6.25 (W )
I c ( sat )VCC 1.25  20
PDC = = 7.96 (W )
p p
123
Class C Amplifiers
• Be biased so that conduction
occurs for much less than 180o.
• More efficient than either class A
or push-pull class B and class AB.
• Not used for linear amplification,
but used in radio frequency (RF)
applications.
Class C is biased below cutoff with

the negative VBB supply → ac
source voltage has a peak value
slightly > |VBB| + VBE → short
interval, the transistor is turned on.
124
Class C Amplifiers
The power dissipation of the transistor in a
class C amplifier is low!
• Power dissipation during the on time

PD(on) = Ic(sat)Vce(sat)
• Power dissipation averaged over the
entire cycle (transistor is on for a short
time, ton, and off for the rest of the input
cycle):
 ton   ton 
PD ( avg ) =   PD ( on ) =   I c ( sat )Vce ( sat )
T  T 
125
Class C Amplifiers
• Tuned Operation
Because the Vout is not a replica of the input Vin, the
resistively loaded class C amplifier alone is of no
value in linear applications. It is therefore necessary
to use a class C amplifier with a parallel resonant
circuit (tank).
Resonant frequency of the tank circuit
1
𝑓𝑟 =
2𝜋 𝐿𝐶
The short pulse of collector current on each
cycle of the input initiates and sustains the
oscillation of the tank circuit so that an
output sinusoidal voltage is produced
126
Class C Amplifiers
• Maximum output power:
Vrms ( 0.707VCC )
2 2 2
0.5VCC
Pout = = 
RC RC RC
• Total power of the circuit: PT = Pout + PD(avg)
Pout
• Efficiency: =
Pout + PD ( avg )
When Pout >> PD(avg), the class C efficiency closely approaches 1 (100%)
127
Example 12
• A class C amplifier is driven by a 200 kHz signal. The transistor is on
for 1us and the amplifier is operating over 100% of its load line. If
Ic(sat) = 100 mA and Vce(sat) = 0.2 V, what is the average power
dissipation of the transistor?
128
Example 12 – Sol.
1
The period is T= = 5 s
200 kHz
Therefore,
 ton 
PD ( avg ) =  I c ( sat )Vce ( sat ) = 0.2  100 mA  0.2 V = 4 mW
T 
129
Example 13
• Suppose the class C amplifier described in example 12 has a
VCC = 24 V and RC = 100 ohm. Determine the efficiency.
130
Example 13 – Sol.:
From Example 12, PD(avg) = 4 mW.

2
0.5VCC 0.5  24
Pout = = = 2.88 (W )
RC 100
Therefore,
Pout 2.88
= = 0.999
Pout + PD ( avg ) 2.88 + 4  10 −3
or, as a percentage, 99.9%.
131
Prob. #1: What are the voltage gain, input resistance, and output resistance of the
amplifier (in slide #35) if bypass capacitors C2 and C4 are removed from the
circuit?

Q3 F = 80, VA = 60 V, VBE = 0.7 V 132
Prob. #2: Find the gain and input signal range for this amplifier.

Q3 F = 80, VA = 60 V, VBE = 0.7 V
133
Some note abt MOSFET
SMALL-SIGNAL MODEL FOR THE MOSFET
Here, we consider the behavior of the
common-source amplifier stage that is the
FET version of the common-emitter
amplifier (in small-signal model). Small-signal model for the 3-
Kn terminal MOSFET
The drain current is: iD = ( vGS − VTN ) (1 +  vDS )
2
2
for vDS ≥ vGS − VTN, and iG = 0, where Kn = μnCox(W/L).
id iDS id iDS
gm = = go = =
vgs vGS Q − po int
vds vgs = 0
vDS Q − po int
vds = 0
iDS 2I D
gm = = K n (VGS − VTN )(1 + VDS ) =
vGS Q − po int
VGS − VTN
iDS Kn ID ID
go = = (VGS − VTN ) = =
2
vDS Q − po int
2 1 + VDS 1 + V
DS

134
Some note abt. MOSFET
SMALL-SIGNAL MODEL FOR THE MOSFET
ID ➔ giải thích tại sao giá trị điện trở ro1 của M1
Transconductace : g m =
VGS − VTN trong example 3 (slide #38) bằng 12.2 k!
2 1
+ VDS
1 + VDS
ro1 = 
1
+ VDS =
1  1
Output resistance : ro = =  ID ID
go ID ID
1 + 0.02  10.9
If VDS << 1/λ → ro  1/ID ro1 = = 12.18 ( k )  12.2 k 
0.02  5mA
Rewriting the expression for gm from previous equations

g m = kn (VGS − Vtn )(1 + VDS ) = 2kn I D (1 + VDS )
 kn (VGS − Vtn ) or g m  2k n I D
where the simplifications require λVDS << 1
135

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Lecture #4.

I. In terms of frequency range: IV. In terms of parameter:

III. In terms of coupling: VI. In terms of tuning:

rp is replaced with an open circuit for the MOSFET

✓ Very large voltage gain

➢ This ones make the CC/CD

➢ Input & output impedances are the

Như vậy, không thể nào

❖ Typical spec. for a general purpose operational amplifier Cascading

A multi-stage amplifier is a combination circuit

The basic functions of coupling blocks:

Input & output

Fig.: Two-port representation for three-stage cascaded amplifier

dBm to express absolute values of power relative to a milliwatt.

Ex.: 100 mW = 10log10(100/1) = 20 dBm

❑ AC input signal @ B terminal of

The transistor M1 Kn = 10 mA/V2, VTN = -2 V,  = 0.02 V-1

Detailed DC calculations are

Fig.: dc equivalent circuit Q-POINT VALUES SMALL-SIGNAL PARAMETERS

Fig.: ac equivalent circuit for ac analysis of the three-stage

The terminal gain of the emitter follower stage:

Calculations of Current gain and Power gain:

❖ Input Resistance: Rin = RG = 1 M ie ix

Disadvantage: small changes in the

Thevenin equivalent circuit

All the remain works (DC & AC analysis) must be

Fig.: Small-signal equivalent circuit 42

• Give initial conditions:

• If the temperature changes by ∆𝑻 = 𝟏𝟎𝟎 𝑪, situation?

Consider β1 & β2 >> 1 → IE2  β1β2IB1

• Darlington pair EE American & inventor of a

𝑅𝑜1 ≅ 𝛽𝑜1 𝑅𝑜2

Differential-mode input signal: 𝑣𝑖𝑑 = 𝑣2 − 𝑣1

Output voltage: vo = AdvId + AcmvIcm

Common-mode rejection ratio (CMRR): Fig.: Representing the input signals to a

4.6 Differential Amplifier v2(t)

▪ Invert the diff. representation

▪ Both differential signals have vCM(t) = VDC

v1(t) 1.9V vCM

BJT differential amplifiers MOS differential amplifiers

Ideal, the differential amplifier is symmetric. The differential amplifier behaves as

➢The differential pair with a large differential input

• Assume: Q2 base grounded and Q1 base at +1 V

➢The differential pair with a large differential input

➢Assuming the bias current source I to be ideal and thus I

• Apply a small signal vi

with IB = IC/βF , and VC1 = VC2 = VCC − ICRC

Total input voltages: v1 = vic + vid /2 and v2 = vic − vid /2

𝑣𝑜𝑑 𝐴𝑑𝑑 𝐴𝑐𝑑 𝑣𝑖𝑑

Resistances rp & REE have their equivalent conductances virtual

Purely CM input signals are applied to the

The output voltage at collectors:

❑ The differential output voltage vod is identically zero because the

By writing gm in terms of the collector current IC

The differential input voltage as: vGS 1 − vGS 2 = v1 − v2  vD

Note this result shows that the drain

Fig. Normalized plots of the currents in a MOSFET

❑Read at home the following sections (book: Microelectronic Circuit