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Experiment No: 21 Experiment Name: Examination of J-K Type Flip Flop
Experiment No: 21 Experiment Name: Examination of J-K Type Flip Flop
Figure 21.4
Table 21.2
Experimental Procedure:
2- Observe the Q output by using the SET, RESET, J-K, Clk' values in Table 21.2 and write it to the
relevant digit. (X) Places seen are indifferent values. It can be "1" or "0".
NOTE: The Clk pulse should be given last in each sequence.
3- According to the results in Table 21.2;
a.) When both J-K inputs are “0”, when Clk arrives, does FF keep its old state?
EXPERIMENT NO: 5
EXPERIMENT NAME: EXAMINATION OF UP SYNCHRONOUS COUNTER
CONSISTING OF JK FLIP FLOPS
Figure 5.2
Experimental Procedure:
1- By setting up the circuit in Figure 5.2, combine the GNDs of both sets and apply the power.
2- Make the SET lead (key A) "0" and make it passive. Set the RESET lead (D switch) to the "1"
position temporarily, then set it to "0". Is "0" seen on the display? Why?
3- Apply the first Clk pulse to the FFs with the PULSE button. Explain the change in outputs.
5- What type of counting does the counter perform according to the results in Table 5.1? Why?
6- Is the principle of the synchronous counter given in the preliminary information appropriate, with
the changes up to LED-3...LED-0 connected to the outputs when each pulse is applied?
Table 5.1
Figure 29.3
Experimental Procedure:
2- Prepare the circuit as a right shift register by making S0=1(K switch), S1=0 (J switch). The
information is prepared to move from Q0 to Q3.
3- Set all outputs to "0" by making MR "0" (key G) (delete:0). Then disable deletion by making MR
"1".
5- With pulse pulse (40194 positive edge will be triggered.) Send pulse 4 times. Has the information
been recorded in the recorder? (Observe the result on the LEDs.)
Table 29.2
INPUTS OUTPUTS
MR MOD CLK SERIES PARALLEL Q0 Q1 Q2 Q3
S0 S1 LEFT RIGHT A B C D
0 X X X X X X X X X
1 X X 0 X X X X X X
1 1 1 1 X X A B C D
1 0 1 1 1 X X X X X
1 1 0 1 X 1 X X X X