SOI

Silicon on Insulator
Technology
SOI Technology
Silicon on insulator (SOI) technology refers to the use
of a layered silicon–insulator–silicon substrate in place
of conventional silicon in semiconductor Manufacturing.
SOI Technology

• Why?

• As MOSFET’s are scaled down to near-

and sub-micrometer dimensions, small-
geometry effects alter their device
characteristics.

• Parasitic Effects are pronounced

Conventional CMOS Technology & Its Limitations

Short Channel Effects (Leff ≈ xj ) Narrow Channel Effects (W ≈ xdm)

Latch-up Problem in CMOS

Refer Bulk CMOS Limitations PPT

Need for SOI Technology

Improves bulk technology

Allow continuous by
miniaturization of MOSFET
Low parasitic capacitance and
device.
Resistance to Latch-up

Compatible with existing

Capable of higher current
fabrication process
densities
without
than
any special equipment or
obtained in equivalent bulk
retooling of an existing
devices.
factory

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SOI Technology
• SOI-based devices differ from conventional silicon-
built devices in that the silicon junction is above an
electrical insulator, typically silicon dioxide or
sapphire
SOI Technology

• In a Silicon On Insulator (SOI) Fabrication

technology , Transistors are encapsulated in SiO2 on
all sides.
SOI Technology

• The choice of insulator depends largely

on intended application
• Sapphire is used for high-
performance radio frequency (RF)
and radiation-sensitive applications,
and
• Silicon dioxide is used for diminished
short channel effects in
microelectronics devices.
SOI Technology

• BOX: Buried Oxide

SOI MOSFET Structure
Bulk silicon and Silicon on Insulator (SOI) MOSFET

Bulk MOSFET Silicon on Insulator MOSFET

 SOI Technologies

SOS (Silicon on Sapphire)

SIMOX (Separation by IMplanted OXygen)

BESOI (Bond and Etch-back SOI)

ELTRAN (Epitaxial Layer TRANsfer)

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 SOI Technologies

SOS (Silicon on Sapphire)

• The topmost Si layer is

grown directly on the
insulator.
• Homoepitaxy- Requires an
appropriately oriented
crystalline insulator
• Low channel electron
mobility is observed in SOS
MOSFETs (≈ 230-250
cm2/V-sec)
 SOI Technologies
SIMOX (Separation by IMplanted OXygen)
• Ion Implantation of Oxygen is
carried out at:
-Energy 120-200 keV
-Dose ~0.3-1.8e18 cm-2
• The wafer is then Annealed in
inert atmosphere above 1300°C
for 3-6 hours
• Usually Multiple implants are
carried out to overcome defect
density
• Typical BOX layer of thickness
100, 200, 400 nm is obtained
• The SOI film thickness varies
from ~50 - 240 nm

Ref: https://www.google.com/patents/US5888297
 SOI Technologies
SIMOX (Separation by IMplanted OXygen)
 SOI Technologies

SIMOX (Separation by IMplanted OXygen)

There are two essential stages of the
process: ion implantation and annealing.
In the implantation stage, oxygen ions
are implanted in the silicon wafer and
react with the silicon to form silicon
dioxide precipitates. However, the
implantation causes considerable damage
to the wafer and the layer of silicon
dioxide precipitates is not continuous.
Thus high-temperature annealing helps
repair the damage and form the oxide
precipitates into a continuous layer. Now
the silicon's quality is restored and the
buried oxide (BOX) layer can act as a
highly effective insulator.
 SOI Technologies

BESOI (Bond and Etch-back SOI)

1. Thermally Oxidize 2. Bond wafer-B on the 3. Etch back the top

Wafer A oxide by SFB wafer-B to the required
SOI Thickness

1 2 3
 SOI Technologies
BESOI (Bond and Etch-back SOI)
 SOI Technologies

BESOI (Bond and Etch-back SOI)

By using bonding chemistry between silicon (Si) and silicon dioxide(SiO2)

or between SiO2 and SiO2 effectively, two Si wafers are tightly bonded
with a SiO2 layer as an insulator inside the bonded pair. After one side of
the Si bulk is thinned down properly with a desired active Si layer
thickness, bonded SOI wafers are obtained.

The fabrication process is accomplished by three basic steps. The first

step is to mate a thermally oxidized wafer on a non-oxidized wafer at
room temperature. The second step is to anneal the bonded pair to
increase bonding strength. The third step is to thin down one side of the
bonded pair to an appropriate thickness by grinding, etching and
polishing.
 SOI Technologies

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 SOI Technologies

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• Hydrogen doses >5´X1016 cm-2 are typically used for

splitting of silicon.
• For manufacturing SOI structures, the implanted
surface is bonded to another wafer.
• As a function of temperature, depending on material
and implant conditions, the pressure of hydrogen that
accumulates in the microcavities and microcracks
induced by the initial implantation eases splitting
along the implanted zone.
• SOI film thickness set by H2 implant energy and BOX
thickness
• The net result is that a thin layer of Si, defined
precisely by the implant depth, is transferred from a
seed wafer to a handle wafer.
 SOI Technologies

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 SOI Technologies
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 SOI Technologies

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 SOI Technologies
ELTRAN (Epitaxial Layer TRANsfer)

It is a technology developed by Canon

CMOS Fabrication by SOI Technology

The subsequent steps for fabrication of CMOS are similar to Bulk Technology
Bulk vs SOI
CMOS in Bulk vs SOI technology
CMOS in Bulk vs SOI technology
Types of SOI Devices
 Fully Depleted SOI
• In an NMOS transistor, applying a positive
voltage to the gate depletes the body of P-type
carriers and induces an N-type inversion
channel on the surface of the body.

• If the insulated layer of silicon is made very

thin, the depletion layer fills the full depth of
the body. A technology designed to operate this
way is called a “fully depleted” SOI technology.

• The thin body avoids a floating voltage

Fully Depleted SOI
 Partially Depleted SOI
• On the other hand, if the insulated layer
of silicon is made thicker, the inversion
region does not extend the full depth of
the body.

• A technology designed to operate this way

is called a “partially depleted” SOI
technology.

• The undepleted portion of the body is not

connected to anything. => Floating Body
Partially Depleted SOI
FDSOI vs PDSOI
 FDSOI vs PDSOI

PDSOI FDSOI

Insulating BOX thickness is 100 to 200nm Insulating BOX thickness is 5 to 50nm

Top silicon layer 50 to 90nm Top silicon 5 to 20nm

Used in analog circuit Low power applications

Easy to manufacture Leakage and power consumption reduced

drastically

Drawback: packaging scalability Drawback: complex fabrication process

FDSOI vs PDSOI
 FDSOI vs PDSOI

Conventional MOSFET Partially depleted SOI Fully depleted SOI

MOSFET MOSFET
SOI is the technology of the future

Highlights
• Reduced junction capacitance
• Absence of latchup
• Ease in scaling (buried oxide need
not be scaled)
• Compatible with conventional
Silicon processing
• Reduced leakage

Drawbacks
• History Effect
• Kink effect
• Self-Heating Effect
 Advantages of SOI technology
• Technology
– Simpler technology with no wells or trenches
• Device Parameters
– Better dielectric isolation in both vertical and
horizontal directions
– No latch up
– Better radiation tolerance
– Low drain / source junction Capacitances and
leakage currents
• Device performance
– Better sub-threshold swing

Why??
 Advantages of SOI technology

P+N+ N+ P+ P+

P-well

No walls and Trenches: N-Substrate

Ease of Fabrication A: Cross-section of bulk CMOS inverter

N+ P+ N+ P+ P P+

Buried oxide

Si-substrate
B: Cross-section of a SOI CMOS inverter
Advantages of SOI technology

Better isolation lets denser

fabrication:

It is recognized by IBM that 30%

more electronic devices than those of
bulk can be fabricated in SOI.
 Advantages of SOI technology

No Latch-Up Problem

SOI has no wells into the substrate and therefore no latch up or leakage path.
 Advantages of SOI technology
Better Radiation
Tolerance

Soft-errors in SOI Soft-errors in Bulk

 Advantages of SOI technology

Low drain / source

junction Capacitances

Bulk

SOI
Reduced Capacitance would imply
Lower Power Dissipation
 Advantages of SOI technology

Better Sub-Threshold
Swing

Sub-Threshold swing is steeper and ON current improved

 Limitations of SOI technology

Floating Body Effect

• In Silicon-On-Insulator process technology, the

source, body, and drain regions of transistors are
insulated from the substrate.

• The body of each transistor is typically left

unconnected and that results in floating body.
• The floating body can get freely charged /
discharged due to the transients and this condition
affects threshold voltage (Vt) and many other device
characteristics.
Limitations of SOI technology

Kink Effect

The transistor's body forms a

capacitor against the insulated
substrate.
The charge accumulates on this
capacitor and may cause adverse
effects, for example, off-state
leakages.
The current flowing through the
device is affected, based on
charges accumulated on Floating
body.
This itself is called Floating Body
Effect (or) KINK effect.
 Limitations of SOI technology

History Effect
• In PDSOI, Floating body can be charged/discharged => Changes in the MOS
Transistor Threshold voltage due to differences in the (Floating) Body voltages.
• This could cause variation in the circuit delay and mismatch between two
identical devices. Two transistors may have Floating body at different voltages
based on their previous steady-state condition. They may Switch at different
times, based on charges accumulated.
• This is called the History Effect.
• A SOI logic circuit will have shorter delay if switching regularly verses a circuit
that has been inactive for a long time and then switches.
Limitations of SOI technology

Self-Heating Effect

50
Energy Band Diagram for Bulk, PDSOI and FDSOI
Technology MOSFETs

Shaded Regions are depleted regions