ELL 100 - Introduction to Electrical Engineering

LECTURE 19: DIODE BASED CIRCUITS

Diode Types

2
 Diode Types

Symbol for various types of Diodes 3

 Numerical 1
A full-wave center-tapped rectifier circuit is shown below.
Assume each diode has a cut-in voltage V = 0.6V and a
forward resistance rf = 15. The load resistor, R = 95 .
(a) Determine peak output voltage vo across the load, R
(b) Sketch the output voltage vo and label its peak value.
SOLUTION:
vs (peak) = 125 / 25 = 5V

V + IDrf + IDR - vs(peak) = 0

0.6 + 15ID+ 95ID - 5 = 0
ID = (5 – 0.6) / 110 = 0.04 A

Vo

vo (peak) = 95 x 0.04 = 3.8 V

3.8V

t
 Numerical 2
Consider the battery charging circuit shown below.
Assume VB = 6 V, R = 120 Ω, VS = 18.6 V and vγ = 0.6 V. .

Determine the peak diode current, maximum reverse-bias diode voltage,

and the fraction of the wave cycle over which the diode is conducting.
 Numerical 2
Solution:
vs ( peak )  v  vB 18.6  0.6  6
Peak diode current I D ( peak )    100mA
R 120
Maximum reverse-bias diode voltage
VRB = VB + VS = 6 + 18.6 = 24.6 V
- VRB +
-

+
The diode conduction is started with phase angle of the wave
v1  18.6sin t1  V  VB  0.6  6.0  6.6V

1  t1  sin (6.6
1
18.6
)  20.783

2  t2  180  20.783  159.217

So the % of conduction of diode with respect to

full cycle of the wave is
2  1 159.217  20.783
*100  *100  38.453%
360 360
 Numerical 3
(a) Sketch the output voltage vo(t) and determine its average dc level
assuming the diode to be ideal.
(b) Repeat part (a) for a real silicon diode with vγ = 0.7 V.
Solution: (a)

For half-wave rectifier, the avg dc level is

Vdc = -Vm/π = -0.318(20 V) = -6.36 V
The negative sign indicates that the polarity of the output is opposite to
the defined polarity of figure below
(b) For a silicon diode, the output has the appearance below

Vdc = -0.318(Vm - 0.7) V = -0.318(19.3 V) = -6.14 V

The resulting drop in dc level is 0.22 V, or about 3.5%.

 Numerical 4
Determine the output waveform vo(t) for the network below. Calculate the
average dc level and the required PIV for each diode.
Solution:

vo  1 vi
2
PIV = Vo(max) = 5 V
Vo max  1 Vi max  1 (10V )  5V
2 2
For the negative part of the input, the roles of the diodes are interchanged
but vo remains the same => circuit acts as full-wave rectifier

Vdc = 2vo,max/π = 0.636(5 V) = 3.18 V

 Numerical 5
Determine vo(t) for the network below.
Solution:
Determining the transition level

For vi ≥ 4 V, vo = vi
For vi ≤ 4 V, vo = 4 V
 Numerical 6
Determine vo(t) for the network below.
Solution: Note that the frequency is 1000 Hz, resulting in a period of 1 ms
and an interval of 0.5 ms between transitions. Consider the negative input
half-cycle first,

The result is vo = 5 V for this interval.

Applying Kirchhoff’s voltage law around the input loop results in

-20 + VC − 5 = 0 => VC = 25 V
The capacitor will therefore charge up to 25 V. Now consider the positive input
half-cycle,

Applying Kirchhoff’s Voltage Law around the outside loop results in,
10 + 25 − vo = 0 => vo = 35 V
The time constant of the discharging network is determined as
τ = RC = (100 kΩ)(0.1 μF) = 0.01 s = 10 ms >> 0.5 ms

Thus, it is certainly a good approximation that the capacitor will hold its
voltage during the positive period of the input signal.
Clamping Network with a Sinusoidal Input
 Numerical 7
Determine vo for the network below.
 Voltage Ripple in Rectifier circuits
In any case of rectification, the amount of AC voltage mixed with
rectifier's pure DC output is called ripple voltage.
If power levels are not too high, filtering networks may be
employed to reduce amount of ripple in output voltage.
 OUTPUT FILTER CAPACITOR DESIGN TO
LIMIT THE OUTPUT VOLTAGE RIPPLE

Full wave rectifier with Equivalent Circuit model with

centre tapped added capacitive filter
transformer
25
 Vo(max) = Vm
α

Ripple voltage Vr(pp) = Vo(max) - Vo(min)

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α

 Vo (min) 
Vo (min)  Vm sin( ) or   sin 
1

 m 
V

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 α

𝑡
−
𝑣𝑜 𝑡 = 𝑉𝑚 𝑒 𝑅𝐿 𝐶𝑒

 td  Vm 
vo (t  td )  Vo (min)  Vm e RLCe
...(2)
=> td  RL Ce ln   .....(3)
V
 o (min)  28
 td     2   ......(1)
Substituting the expressions for td and α into above equation,
 Vm  1  o (min) 
V
 RL Ce ln     2     2  sin  
V   Vm 
 o (min) 
Therefore, the filter capacitor Ce can be found from
 Vo (min) 
 2  sin  1

Ce   Vm 
..............(4)
 Vm 
 RL ln  
 Vo (min)  29
 α

   t  
Vm
  e d (t )   cos (t ) d (t ) 
RLCe
Redefining the time origin Vo ( av )
(ωt = 0) at π/2 when the   0  
discharging interval begins,  

Vm  
 RLCe

we can find the average  
 L e
R C 1  e   sin   ......(5)
   
output voltage Vo(av) as  
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 OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
We can derive simpler explicit expressions for the ripple voltage in terms of the
capacitor value if we make the following assumptions:
(1) The charging time tc is small compared to the discharging time td i.e. td >> tc,
we can relate td to the period T of the input supply as
td = T/2 - tc ≈ T/2 = 1/2f
(2) Use Taylor series expansion of e−x ≈ 1 − x for a small value of x << 1,
assuming the capacitor doesn’t discharge much
td RLCe  td 
Vo (min)  Vm e  Vm 1   .....(7)
 RL Ce 
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 OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
The peak-to-peak ripple voltage Vr(pp) is:
td Vm
Vr ( pp )  Vm  Vo (min)  Vm  .........(8)
RL Ce 2 fRL Ce

The above expression can be used to find the value of capacitor Ce with a
reasonable accuracy for most practical purposes as long as the ripple factor (i.e.
Vr(pp)/2Vo(av)) is within 10%.
The ripple voltage depends inversely on the supply frequency f, the filter
capacitance Ce, and the load resistance RL.

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 OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
If we assume that the output voltage decreases linearly from Vo(max)(=Vm) to Vo(min)
during the discharging interval, the average output voltage can be found
approximately from

Vm  Vo (min) 1  td 
Vo ( av )   Vm  Vm 1    ....(9)
2 2  RL Ce 
Which after substituting td becomes
1  1   Vm  1 
Vo ( av )  Vm  Vm 1     2  R 2 fC  ..(10)
2  RL 2 fCe  2  L e 

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 OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
The ripple factor RF can be found from
Vr ( pp ) / 2 1
RF   .............(11)
Vo ( av ) 4 RL fCe  1

• The peak input voltage Vm is generally fixed by the supply, where the
minimum voltage Vo(min) can be varied from almost 0 to Vm by varying the
values of Ce and/or RL.
• Therefore, it is possible to design for an average output voltage Vo(dc) in the
range from 2Vm/π to Vm.

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 OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
In summary, expressions for Ripple Factor (RF), average output (dc)
voltage (Vo(av)) and filter capacitor Ce are related as:

1 Vm  1 
RF  Vo ( av )   2  R 2 fC 
4 RL fCe  1 2  L e 

1  1 
Ce  1  
4 fR  RF 
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OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE

Numerical Example:

A single-phase bridge-rectifier is supplied from a 120-V, 60-Hz

source. The load resistance is R = 500 Ω.
(a) Design a C filter so that the ripple factor of the output
voltage is less than 5%.
(b) With the value of capacitor C in part (a), calculate the
average load voltage Vdc.

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OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
Solution:
RF =5% =0.05 , Vm  120  2  169.7 V  169V

1  1  1  1 
(a) C  1   1    175 F
4 fR  RF  4  60  500  0.05 

Vm  1  169  1 
(b) Vo ( av )   2  R 2 fC   2  2  500  2  60  C   161V
2  L e   e 

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