Name:______________________ Student ID:

UoTripoli | EEE department EE234 | Fall2023-2024 | Date:27-03-2024

By: Hussain Said & Nuri Benbarka Total: 60Marks. Time: 2:30 Hours

Final Exam

Q1.a) Implement the function [4 marks]

𝑓(𝐴, 𝐵, 𝐶, 𝐷) = ∑(0, 2, 5, 8, 10, 14)

using a single 4*1 MUX and as few gates as possible.

Q1.b) Draw the logic diagram of a 2-to-4-line decoder using

NOR gates only. [4 marks]

Q1.c) For the circuit shown on the right, write down 𝑋(𝐴, 𝐵, 𝐶)
and 𝑌(𝐴, 𝐵, 𝐶) in the minimized form. [4 marks]
Q1.c

Q2) Consider an NB flip-flop with inputs N and B. This flip-flop can perform three operations:
1) It sets its state to 1 when both inputs are high. 2) It resets its state to 0 when both inputs are
low. 3) It toggles (or complements) its current state when the inputs differ.

a) Provide the state table for the NB flip-flop from the above description. [3 marks]
b) Provide the NB flip-flop's excitation table. [3 marks]
c) Show how to construct a JK flip-flop using the NB flip-flop. [3 marks]

Q3) Develop a one-input, one-output serial 2’s complementer that operates on a bit string
received at the input and produces the 2’s complement at the output.
a) Draw the state diagram for the serial 2’s complementer. [3 marks]
b) Write down the state table for the serial 2’s complementer. [4
marks]
c) Implement the circuit using T flip-flops. it should support asynchronous reset capability
for initiating and terminating the operation [3 marks]

Q4.a) Design a four‐bit shift register with parallel load using D flip‐flops. There are two control
inputs: shift and load. When shift = 1, the content of the register is shifted left by one position.
New data are transferred into the register when load = 1 and shift = 0. If both control inputs are
equal to 0, the content of the register does not change. [6
marks]

Q4.b) Using a 4-bit binary counter and logic gates, design a counter that counts 0, 1, 2, 3, 4, 5,
8, 9, 10, 11, 12, 13 and repeats. Note: Clear is an asynchronous input, and Load is a
synchronous input. [6 marks]
Q5) For the following state diagram:

a) Determine whether the state machine is a Mealy or a Moore machine. [1 mark]

b) Tabulate the state table. [5 marks]
c) Reduce the state table to a minimum number of states. [3 marks]
d) Draw the state diagram corresponding to the reduced state table. [3 marks]
e) Fill out the timing diagram assuming you are starting at state A & the circuit is positive
edge triggered. In the state row, write down which state the system is in. [5 marks]