Memories in microprocessor
systems
In this series of articles Alan Clements describes the characteristics of
memory components, their timing diagrams and the address decoding
circuits which link memory components to a microprocessor's address bus
This first article begins by defining some of the terms
found in literature dealing with memory components, and
then describes the characteristics of the most frequently
encountered memory components. The interpretation of
the timing diagram of a popular memory component is
examined together with the timing diagrams of a micro-
processor. The problems of matching the two timing
diagrams are illustrated by choosing a Texas Instrument's
memory and a Motorola 6800 microprocessor.
Before dealing with the types of memory c o m p o n e n t suitable
for a microprocessor memory system it is helpful to define a
few terms.
Memory cell
A memory cell is the smallest unit of information storage,
and can hold a single logical zero or logical one.
Access time
The access time is one of the most important parameters of
any memory component, and is the time taken to read data
from a given memory location, measured from the start of a
read cycle initiated by one or more of the memory
component's input lines changing logical state. The access
time is made up of two parts; the time taken to locate the
required memory cell (address decoding time} and the time
taken for the data to become available from the memory
cell. Because most semiconductor memories have identical
read and write access times, the access time of a memory
component is normally taken to mean the read or write
access time.
Random access
When a memory is configured so that the access, time of any
cell within it is constant (neglecting small variations caused
by propagation delays in the address d e c o d e r / a n d is
independent of the actual location of the cell, the memory
is said to be random access memory (RAM). In practice this
means that the CPU does not have to worry about the time
taken to read a word from memory (or write a word to
memory}, because all read/write cycles will have the same
duration. The term RAM is usually employed to describe
Department of Computer Science, Teesside Polytechnic,
Middlesbrough, Cleveland TS1 3BA, UK
vol 3 no 5june 79 0 1 4 1 - 9 3 3 1 / 7 9 / 0 5 0 2 2 7 - 0 9 $02.00 © IPC Business Press
read/write memory, where data may be read from or written
into the memory. This usage is incorrect because random
access indicates only the property of constant access time
and has nothing to do with the ability of the memory to
modify its data. In order to be consistent with other
literature, 'random access memory' means 'random access
read/write memory' throughout this article, unless other-
wise stated.
Serial access
In a serial access memory the time taken to access data is
dependent on the physical location of the data within the
memory. The data moves past some read/write device so
that in accessing any given memory cell, the waiting time
depends on how long that cell takes to move to the read/
write device. Examples of serial access memories are
magnetic tapes, magnetic discs, shift registers and magnetic
bubble memories.
Volatile memory
Volatile memory loses it contents when the source of
power is removed. This applies to most semiconductor
memory, where the data is stored as a charge on a capacitor
or as the state of a transigtor in a bistable circuit.
Read only memory (ROM)
A read only memory is such that its contents cannot be
altered under normal operating conditions. True read only
memories are by definition nonvolatile, but pseudo read only
memories may be realized by using a read/write memory
with the write function disabled. In popular usage 'read only
memory' has come to mean read only random access
memory. It is, of course, possible to have read only serial
access memories.
Static memory
Once data has been written into a static memory cell, it
remains there until altered by overwriting with new data or
if the memory is volatile by removing the power. Static
semiconductor memory cells usually employ crosscoupled
transistors to hold the data.
Dynamic memory
In a dynamic memory the data is stored in the form of a
charge on a capacitor. Because capacitors are not perfect,
227
 fcc (,5V) Electrically alterable read only memory (EA ROM)
The EAROM is a programmable read only memory which
can be programmed and erased electrically without
removing it from its normal location. The EAROM may be
Row thought of as a nonvolatile RAM, although the signal level
select requirements of an EAROM usually differ between read and
write operations, unlike those of a normal RAM.
,o=o v
I Gnd
I/O "I"
=

STATIC RANDOM ACCESS MEMORY

Figure 1. Static memory storage cell
tile charge gradually leaks away and the data is lost.
Additional circuitry is thus needed periodically to restore
the charge on the capacitors in an operation known as
memory refreshing.
Semistatic (edge-activated) memory
A semistatic memory array uses fully static memory cells
to store data, but has address decoding and control circuits
which operate in a dynamic mode. They are clocked by
their control inputs or by transitions on the address bus.
A semistatic memory consumes less power than a fully
static memory of the same size.
Programmable read only memory (PROM)
A programmable read only memory is a type of ROM which
can be programmed by the user (as opposed to the
manufacturer) once and once only.
Erasable programmable read only memory (EPROM)
An erasable programmable read only memory can be
programmed by the user, have its contents erased and then
be reprogrammed. The erasure of data from an EPROM
almost always necessitates its removal from the normal
circuit location.
In cases where a microprocessor system is used as a general
purpose digital computer, the bulk of the system memory is
likely to be either static or dynamic read/write random
access memory, because a wide variety of different programs
will be run on the computer. Where a microprocessor is used
in a dedicated application, e.g. a chemical process controller,
the bulk of the memory is more likely to be read only
memory because the program does not have to be changed.
Static RAM is widely employed in microprocessor
applications largely because it is very easily implemented.
Unlike dynamic memories, static memories do not require
any action to refresh their contents periodically. Figure 1
shows the circuit diagram of a typical NMOS static storage
cell. The most significant feature of this cell is that six
transistors are required to store each bit of data. Dynamic
memory cells store their data as a charge on the inter-
electrode capacitance of a single transistor, and therefore
require fewer transistors per cell. Because of this a dynamic
memory of a given chip size can always store more data than
a static memory of the same chip size. Furthermore the
average power per bit consumed by a dynamic memory is
less than that of an equivalent static memory.
From the above remarks it would appear that static
memories are inferior to dynamic memories. Although this
is often true for large memory systems, the extra cost and

Table 1. Characteristics of some static RAMs

Total Power (mW) Access

Static RAM type Arrangement Pins
bits typ max time (ns)

Intel 2102A 1024 1024 x 1 165 275 350 16

Intel 2101A 1024 256 x 4 175 275 350 22
Intel 21t 1A 1024 256 x 4 300 350 18
Intel 2114 4096 1024 x 4 710 450 18
Intel 2147 4096 4096 x 1 500 90 18
TI TMS4044-45 4096 4096 x 1 275 495 450 18
TI TMS40L45-45 4096 1024 x 4 250 370 450 18
Motorola MCM6810A 1024 128 x 8 350 450 24
AM1-34025-4 1024 1024 x 1 265 45 16
EMM/SEMI 35391 2048 256 x 8 394 400 22
Mostek MK4118-4 8192 1024 x 8 400 250 24

228 microprocessors and microsystems

complexity of dynamic memory refresh circuits make static
memory look much more attractive in small systems.
Static random access memory chips, built with NMOS
technology, are available in several configurations. As
semiconductor technology develops new memory chips with
greater capacities appear. This has the effect of reducing the
price of the o!der chips of lower capacity. In Table 1 several
static RAM chips are described in terms of the number of
bits per chip, the arrangement of the data as words x bits
per word, the number of pins, the access time and the
power dissipation.
Some chips have a common data input/output
arrangement while others have separate input and output
pins. A few chips have a power down facility which allows
the data to be retained if the power supply voltage falls to
not less than 2.4 V. Such an arrangement enables batteries
to provide the relatively low power needed to retain the
memory data during a temporary power failure. The
TMS4046 and TMS4047 chips take power conservation
during power down one step further. These chips have two
power supply pins, one for the address decoding, control
and buffer circuits, and one for the memory array itself.
Under power down or stand-by conditions only the power
supply to the memory array is required at Vcc ~ 2.4 V.
This reduces the power dissipation from 250 mW when
active to 12 mW when powered down.
The majority of memory chips have a single enable or
chip select input. This is used to switch on the three state
data buffers in a read cycle and to permit data to be stored
in the chip in a write cycle. The MC6810 is an unusual
memory component because it has six chip select inputs,
four of which are active low and two active high. This chip
has been designed to be used in circumstances where the
read/write memory requirements are low and memory
decoding circuits can be omitted by using the high order
address lines (Als, A14 • •. etc.) to select the RAM. The
subject of address decoding is dealt with in detail in the
second article in this series.
D Y N A M I C RANDOM ACCESS MEMORY
The dynamic memory cell uses a single transistor to store
data in the form of a charge on a capacitor. Figure 2
illustrates this basic simplicity. Because the charge on the
capacitor gradually leaks away, any data stored will be lost
after several milliseconds. Most dynamic memory chips have
a guaranteed data retention period of 2 ms. In order to avoid
loss of data the charge on the capacitor must periodically be
restored by rewriting the data into the memory cell in an
operation known as refreshing.
The majority of dynamic RAMs have been constructed so
that the memory refresh operation is relatively easy. The
dynamic memory chip is arranged as an array of rows and
columns, so that a typical 4k chip has 64 rows and 64
columns. It is not necessary to refresh each memory cell
individually; a whole row of memory cells is refreshed in a
single operation (refresh cycle). A typical memory refresh
cycle involves little more than a pseudo read cycle, i.e. a
read operation is executed while the chip is deselected.
vol 3 no 5 june 79
T
Row select
Bit line
Figure 2. Dynamic memory storage cell
To perform a refresh cycle, additional logic is usually
necessary to multiplex the address lines between the CPU
address bus and the refresh address counter, which must
cycle through the 64 row addresses. Further logic is
required to synchronize the refresh operation with the CPU,
either by slowing down or halting the CPU in a DMA type
operation or by executing a refresh cycle whenever the CPU
is not using the system bus. If tile memory refresh cyc!e
d o e s n o t involve the CPU, it is said to be transparent because
the dynamic memory appears to the CPU as static memory.
Just as there is a wide range of static memory chips,
dynamic memory chips are available in a variety of formats.
Popular dynamic memory sizes are 4k x 1 and 16k x '1
and the 64k x 1 chip is now becoming available. Because
much of the cost of a memory component is in the pack-
aging rather than the silicon chip itself, there has been a
tendency to put 4k and 16k dynamic memory chips in
16-pin DIL packages. Such a small package cannot accom-
modate all the address lines necessary to access a given
memory cell To get round this difficulty, the address lines
are multiplexed between the row and column addresses of
any memory cell. Two new pins are required to implement
the address multiplexing. These are the row address strobe
(RAS) and the column address strobe (CAS), which are used
to indicate that the address pins hold the address of a row
and a column of a cell in the memory array respectively.
The block diagram of a typical 4k dynamic RAM, the
2104A, is given in Figure 3.
A particular problem associated with dynamic memories
is that of power supplies. Not only do many dynamic RAMs
require three separate power supplies (12 V, 5 V and -5 V)
but the current requirements are transitory. The average
power consumed by a dynamic RAM is much lower than that
of a corresponding static RAM. However, during a memory
access cycle (read/write/refresh) the current requirement of
a dynamic RAM may increase by 60 mA in 5 - 1 0 ns. This
:urrent transient corresponds to a current demand increasino
at the rate of more than six million amps per second. A wel,
designed dynamic memory system requires careful attention
to the layout of the memory printed circuit board and the
selection and positioning of decoupling capacitors.
Dynamic memory components are best suited to large
memory systems where they are much more cost effective
because of their cost, package count, average power
consumption and access time. (Static RAMs can be
obtained with access times lower than dynamic RAMs,
but commonly available dynamic RAMs are often faster
229
 Write enable D Strobe
i I
-4 a __]_ Output
64 senseamplifiers•
C I
Ad~ore-'~s I/0 gating ~ latchand [
---64 -1
4096-: bit
storage array
I ~ q CIoCkno.
lgenerator [ not usually held in RaM because, unlike interpreters,
RAS
Figure 3.. Internal arrangement o f the 2104A 4096 x 1 bit
dynamic R A M
than commonly available static RAMs). In small systems or
systems constructed by the microprocessor enthusiast, the
problems associated with the refreshing of dynamic
memories plus their power supply requirements justify the
use of static memories.
The designers of dynamic memories have realized that if
they are to capture a share of the memory market for small
microprocessor systems, they must overcome some of these
limitations. Mostek has been one of the first companies to
produce a dynamic memory with the advantages of both
conventional static and dynamic memories. The MK4816(P)
series of dynamic memories is byte organized as 2048 x 8
bits, unlike most dynamic memories which are bit organized
as 4096 x 1 or 16384 x 1 bits. The MK4816-3 has an access
time of 200 ns, a cycle time of 360 ns and uses a single 5 V
power supply. Its power requirement is only 150 mW, and
it can be used in a power down mode where it needs only
25 mW to retain data. A special feature of the MK4816 is
that it can be refreshed in the normal way (128 refresh cycles
in 2 ms), or the system refresh logic can be eliminated by
using the MK4816's own internal refresh control logic.
READ ONLY MEMORY
Data in read only memories can be accessed in a read
operation but cannot be altered in a normal write cycle.
Although RaM is often regarded as a special type of RAM
where the data is frozen permanently in the memory cells,
or cannot be altered without physically removing the RaM
component from the memory system, an ordinary read/
write random access memory can be used as a RaM merely
by disabling the write function, or by generating an
interrupt whenever an attempt is made to write to a
protected area of RAM.
Read only memory has several applications in a micro-
pr~essor system. Some of the most important applications
are as follows:
230
-I ~ " • When a microprocessor is first supplied with power, it
Di. either executes a jump to a particular memory location,
or loads its program counter with the contents of a
particular memory location. For example, the MC6800,
when reset, loads its program counter with the contents
of locations FFFF and FFFE. Hence in an MC6800
system some memory must exist at FFFE/F (or at least
respond to these addresses). This memory usually holds
the system's monitor or operating system, which must
be retained after the power supply has been switched off.
Clearly what is required is nonvolatile memory, and RaM
is used because it is, by its very nature, nonvolatile.
• Programs which are not normally modified may be held
in RaM to save the time lost in loading them from paper
vBeC-SV) tape, cassette, or disc every time they are required. Such
VDO(*12V) programs may be part of the operating s'ystem itself or
Vcc(+5V) interpreters for languages like as BASIC. Compilers are
~'Gnd
they may be discarded after they have compiled a
program.
• In order to speed up mathematical computations, RaMs
are often used to hold the values of mathematical functions.
For example, a 1 k RaM can hold 1024 values of sin(x)
where x is in the range of 0 ° to 90 o giving a resolution
of approximately 0.1 o. Interpolation can be employed
to generate values of sin (x) for intermediate values o f x .
When used in this way the RaM becomes a function
generator with the address lines as the input and the data
lines as the output.
• A RaM is used in raster scan display systems to convert
the binary character code, usually ASCII, into a pattern
of dots which are displayed on a television screen.
• If a table of addresses of a 2 n word by m bit RaM is
drawn with the contents of the corresponding memory
locations written alongside the addresses, the result is the
truth table Of a logic element with n inputs and m outputs.
RaMs may therefore be used to replace T T L logic
elements in applications where complex logic functions
are required. High speed bipola'r RaMs are normally
found in this application.
Mask programmable R O M
Mask programmable RaM is programmed at the time of its
manufacture by modifying one of the masks used in the
photolithographic process by which LSI devices are made.
Floating Controlgate Silicondioxide
gate Si 02
(,n.,
~" "". . . . . . . . -~/A
p- fype substrate
, o.,)
p/,.~. . . . . ; .... I
Figure 4. EPROM m e m o r y cell structure
microprocessors and microsystems
Because of the great expense involved in making and testing
anew LSI device, the mask programmable ROM is cost
effective only when produced in large quantities. Mask
programmable ROMs are almost always byte oriented and
are available in sizes of 1 k bytes to 8k bytes.
Most of the applications involving a mask programmable
ROM are in high volume dedicated systems where the high
cost of developing and testing the ROM can be spread over
many systems. In small microprocessor systems used either
as development tools or as hobby computers, the mask
programmable ROM often appears in the form of a
monitor, which is the microprocessor's 'operating system',
and is used to load other programs, modify them (if
necessary) and then execute them. An example is Motorola's
MIKBUG, which, although developed for the MEK6800 DI
development system, has become a standard for most
MC6800-based hobby computers.
EPROM
A more useful type of ROM, from the small scale user's
point of view, is the erasable and programmable read only
memory (EPROM). This may be programmed, erased and
then reprogrammed by the user. Figure 4 illustrates the
basic principle of the EPROM memory cell, which consists
of a single field effect transistor whose gate is totally
isolated from the rest of the circuit by being embedded in
an insulating layer of silicon dioxide. The gate is then said to
be floating'. Above the floating gate is a second gate, the
control gate, which is connected to the row decoder
circuits in the memory array. The cell is programmed by
grounding source and substrate and applying a high voltage
(26 V) to the control gate. The potential difference
between the control gate and the substrate causes electrons
to be injected through the silicon dioxide and become
trapped on the floating gate. This device is remarkable
since the charge will remain on the floating gate for many
years because of the almost perfect insulating properties
of the silicon dioxide. The effect of the charge on the
floating gate is to inhibit the flow of current between
source and drain when the transistor is selected by the
appropriate column address. Thus the trapped charge
determines whether the transistor is in the on or off
state when selected, and hence whether a 0 or 1 is stored in
the cell.
The memory cell may be erased by illuminating it with
ultraviolet light, at a wavelength of 253.7 nm. The UV
radiation imparts sufficient photon energy to the trapped
electrons to enable th'em to escape through the silicon
dioxide to the substrate. There are three consequences of
this mode of erasure:
• to illuminate the cell with UV light, a quartz window
must be put in the package , directly above the chip.
This increases the cost of packaging
• 0ecause the whole chip is illuminated all cells are
simultaneously erased. It is not possible to modify an
EPROM selectively
• because UV light sources are expensive and bulky, it is
necessary to remove the EPROM from its normal place
vol 3 no 5 june 79
V¢¢
Row
Fu
Column
Figure 5. Fusible link FPROM ceil
in the microprocessor system and transport it to a UV
light eraser. After erasing the EPROM it must be
reprogrammed, an operation which is frequently carried
out in a special programming machine. It is possible to
program the EPROM in situ, but it is not usually worth
the effort of providing a programmer in every micro-
processor system
The early EPROM's (e.g. the 1702) were relatively small
(:256 bytes) and required several operating voltages. Currently
available EPROMs can be obtained in I k x 8, 2k x 8 and
4k x 8 configurations, and operate with a single 5 V supply.
Field programmable R O M
The field programmable read only memory (FPROM) is a
bipolar device which may be programmed only once by the
user. A typical FPROM (usually abbreviated to PROM) uses
a single bipolar transistor memory cell. In the emitter of the
transistor is a fuse consisting of a link made from one of
four materials, nichrome, polycrystalline silicon, platinum
silicide or titanium tungsten. A cell of a fusible link FPROM
is illustrated in Figure 5.
During programming the fuses are blown (made open
circuit) by passing a large current pulse through the transistor
by means of the row and column decoding circuitry. When a
memory cell is selected in a read cyclc~, the row input to the
transistor's base will turn it on, and the column line will be
pulled towards Vcc i f the fuse is intact, o r l e f t floating if the
fuse has been blown.
Bipolar FPROMs are often characterised by relatively few
bits per chip and very small access times (50 ns). The FPROM
is often used in conjunction with bit slice technologies where
very high speed processing is required. When FPROMs are
found in microprocessor systems they are frequently employed
as address decoders, where a single 16-pin 32 x 8 FPROM can
save several TTL packages.
TIMING DIAGRAMS
A glance at the data sheet of any memory component always
reveals one or more timing diagrams. A timing diagram shows
the temporal relationship between the events which take
place during a read'or write cycle. It can also be regarded as
a cause and effect diagram, where, for example, the arrival
231
 l¢(rd) are either semistatic or else have clocked latches which make

vaid
stringent demands on the timing arrangements.
In Figure 6 the timing diagram of the address bus appears
Address VIH~
VrL Address as two parallel lines which cross over at points A and B. The

Chip VIH
select
g
VlL
--~~ use of two parallel lines is a convention which means that
the logic levels may be either high or low. In the case of the
address bus, it is highly probable that some address lines are
in the logical one state while others are in the logical zero
Data VIH state.
output V~L I
It is not the actual state of the address bus that is of
interest, but the time at which the contents of the address
bus become stable for the duration of the current memory
Figure 6. Read cycle timing diagram of the TMS40L45
static RAM access cycle. At point A in Figure 6 the contents of the
address bus have bcome stable, and this point is used as a
of a new address is the cause and the output of new data is reference for some of the timing measurements. Because
the effect. Anyone contemplating connecting a particular logic transitions are never instantaneous, it is usual to
memory chip to a microprocessor system bus must first represent a change of state by a sloping line, and to mark
determine whether the timing requirements of the micro- the point (or points) from which measurements are made.
processor and memory are compatible. In most areas of digital electronics the reference points are
taken as 10% and 90% of the upper logic level~ Sometimes
Read cycle timing diagram the reference levels are taken as VIL and VIH on inputs, and
VOL and VOH on outputs.
AF! symbols and abbreviations in Figure 6, which shows the Between points A and B the address bus contains the
timing diagram for the read cycle of a TMS40L45 static address of the location in the RAM which is to be read.
RAM, are those used by Texas Instruments in their own
During this time the address must not ch.ange. The
literature. The values of the parameters defined in Figure 6 difference between points B and B' is that at B the
are listed in Table 2 for the 450 ns version of the RAM. contents of the address bus have started to change to the
It is most unfortunate that semiconductor manufacturers new values which will be used in the next cycle. It is not
use their own individual terminology in describing their until point B' that the new contents of the address bus
products: it is often a tedious task-to match up the timing become valid once more. The time between point A and
diagram of manufacturer A's microprocessor with the B' is the cycle time for a read operation, and is quoted as a
timing diagram of manufacturer B's peripheral. minimum of 450 ns. That is, a microprocessor must not
The specification of the TMS40L45 describes it as a initiate a second read cycle until at least 450 ns after the
fully static RAM requiring no clocks or timing strobe. This start of the current read cycle. The TMS40L45 has a R/W
is an important feature because some memory components input which does not appear in its read cycle timing
diagram. It must therefore be assumed that the R/W input
Table 2. Timing parameters of the TMS40L45 to the RAM is in the logical one state for the entire
duration of the read cycle.
Symbol Parameter Value (ns) Consider now the data o u t p u t of the TMS40L45. Up to
rain max point E, the contents of the data bus are represented as a
single line midway between the two logic levels. This
t c (rd) read cycle time 450 convention signifies that the data bus is floated, or in the
high impedance state. The internal data bus drivers of the
ta(s) access time from chip select 120 TMS40L45 are in the high impedance state until point E,
tpvz,5 output disable time after chip select high 100 which occurs t a (S) s after point C, at which the chip select
output data valid after address change 10 input becomes active. The time between points A and E is
tpvx
ta(A)s , and is the time taken from the point at which the
ta(A) access time from address valid 450 contents of the aci(tress bus are first stable to the time at
tc(wr) write cycle time 450 which the contents of the data bus first contain valid data.
ts. (A) address set up time 0 This time is quoted as having a maximum value of 450 ns.
That is, the data should be valid no later than 450 ns after
tw(W) write pulse width 200 the start of a read cycle. _
th(A) address hold time 20 The chip select input S , must make its active low
transition at least ta(S) s before the output data is required.
ts. (S) chip select set up time 200
The timing diagram says nothing about the relationship
tsu(D) data set up time 200 between point C and point A. This implies that S- can
th(D) data hold time O~ assume its active low state at any time, as long as the ta(S )
reqQirement is satisfied. This is a consequence of the static

232 microprocessors and microsystems

nature of this RAM, and implies that data is continually tc(wr) =.
being accessed from the RAM, and that all the chip select
input does (in a read cycle) is to enable the three state data AddressVIH 7 " ~ ' ~:,~//'//~y'//
output buffers. If S- goes low early in the read cycle, data VlL~-~JA~tsu(A) , t.(W) , th(A) "]B " "
will be put on the data bus no later than ta(5) s after the w~ v,. i'~-~"
active transition of S-. However, the data will not be valid enable Vl ~-- -- -~' TM

until ta(A ) s after the address has become stable (point A). • _J°
At the ei~d of the read cycle, point B, the contents of the v,. L /F
address bus are in the process of changing to their new
values. Because the memory dOes'not respond instantly to
Input VIH /
changes on the address bus, the contents of the data bus are data ViE y/',///////S///'//"~Data validH ~
still valid until point F, which occurs not less than tpvxs
after point B. This is often called the guaranteed data hold
Figure 7. Write cycle timing diagram of the TMS40L45
time of the memory. After point F, the data bus drivers
static RAM
are still in the low impedance state, but the data is no
longer valid. This situation is often indicated by shading the
region between the two logic levels.
At point D the chip select input makes its low to high Start of cycle [_ tcycle = IO00ns
transition, signalling that the chip's data bus drivers can
\
. . . . .

once more be switched into the high impedance state, It is ~1 0 4 V ~ v~-O 6v f

04V
not until point G, tpvz~ 5 s after point D, that the data bus
returns to its high impedance state, and the memory /
component is deselected.
24v --<<d/
Write cycle timing diagram R/~
_ tAD -
The write cycle timing diagram for a TMS40L45 static RAM
is given in Figure 7. This is a little more complex than the Address i ~I.~-<20V
tAH
from CPU # ' ~ 08V
corresponding read cycle timing diagram, because the action
of the write enable (W) input must also be considered. No
harm can be done to the stored data when W is high, as I ~,. tocc .~ tOSR ~ tH

reading a memory cell does not affect its contents, no I

matter how many times a read cycle takes place , but ifW Data from 2OV.~,~'~
=-7
goes low when the contents of the address bus or data bus memory O.8V~-- i Data valid

are not valid, there is a danger of writing erroneous data

into the memory.
Between points A and B, in Figure 7, the contents of the
address bus are stable. The duration AB is called the write
cycle time, tc(wr), and must not be less than 450 ns for a
TMS40L45. The write enable input to the RAM, W, makes
its high to low transition at point C. The time between the
point at which the address bus is stable (A) and the point at
which W goes low (C) is defined as tsu(A). The minimum
value of tsu(A) is quoted as 0 ns. At first sight this may
appear a little strange. What it really means is that W may
make its high to low transition only after the contents of
the address bus have become stable, and not before. In order
to successfully execute a write cycle, W must remain low
for a minimum of tw(W) s, the writa pulse width, before
rising to a logical one state at point D.
Point D is the time at which W has passed the 10% VOH
level and point D' is the time at whicb W has reached 90%
VOH level. It is important to note that D' must occur at
least th (A) s before the contents of the address bus begin to
change at point B. The time between D'and B th(A), is
known as the address hold time.
The active low transition of the chip select input_, S, must
occur at least tsu(S) s before the rising edge of the W input
at point D. The chip select input may make its low to high
Figure 8. Read cycle timing diagram of the MC6800 CPU
transition any time after it has satisfied the condition that
tsu(5 ) i> 200 ns. However, should S remain low while W is
high, a rea~l cycle will occur and the RAM's data bus drivers
will assume a low impedance state.
The system data bus must contain the contents of the
data to be written into the currently addressed memory cell
from point G to point H. Between G and H the data bus
must be stable. Point G must occur at least tsu (D) before
the low to high transition of W at G. This period is known
as the data set up time. After point D the data must be held
stable for another th(D) s, the data hold time.
Microprocessor timing diagram
The designer of a microprocessor system is not simply
interested in the timing diagrams of memory chips alone,
but in the relationship between them and the timing
diagrams of the microprocessor.read/write cycles. Figures 8
and 9 give the timing diagrams of the MC6800 read and
write cycles respectively, and Table 3 defines the symbols
used in these diagrams. Note that the style of these
diagrams differs slig.htly from those of Texas Instrument's

vo/ 3 no 5 june 79 233

 tocle = I 0 0 0 ~
VMA
Data
from
CPU -- - -- t D ~w Data val;d
Figure 9, Write cycle timing diagram of the MC6800 CPU
Table 3. Timing parameters of the MC6800 CPU
Symbol Parameter
tr clock pulse rise time
tA P address delay
tat t address hold time
tH data hold time
tuc c peripheral read access time
t [~.sR data set up time (read)
toDw data delay time (write)
RAM. Moreover Motorola and TI each use their own
symbols in their respective timing diagrams. The fact that
each semiconductor manufacturer describes its products in
its own way using its own terminology makes life very
difficult for the microprocessor systems designer.
In Figure 8 the read cycle timing diagram of a MC6800
CPU with a 1000 ns cycle time (fclock = 1 MHz) is given.
The CPU puts the values of R/W, the current address, and
VMA (valid memory address) on to the system bus no later
than tAD s (270 ns) after the start of a clock cycle. The
contents of all these lines remain constant until at least t.AHS'
(30 ns) after the end of a clock cycle, signified by the rising
edge of q~a. (To be precise, tAH is measured from the 0.4 V
point on the rising edge of ~1 to the 0.8 V or 2.0 V points
on the address lines which represent the maximum value of
VIL and the minimum value of VIH respectively). At the
start of 'a read cycle the data bus will be inahigh
impedance state, and remain in that state until the three
state data bus drivers in the memory are turned on. The
time at which this occurs is unimportant as long as valid
data is on the data bus no later than 530 ns (the maximum
value of the peripheral read access time tacc) after the
contents of the address bus have become stable. Of course,
the data at the input terminals to the CPU will not be valid
234
until the memory component has responded by outputting
data. The data must be valid no later than the maximum
value of tacc + tADS after the start of a cycle (i.e. 270 +
530 = 800 ns). Once the data from the memory has become
valid, the contents of the data bus must remain stable for
at least tDS R s, which is known as the data setup time. At
the end of a cycle the data must remain valid for a further
period of not less than t H s (the data hold time) after the
falling edge of ~b:. At the end of a write cycle, signified by
the falling edge of ~2, the CPU maintains the contents of
the data bus for at least a further t H s (the data hold time).
Combined timing diagram
In Figure 10 the read cycle timing diagrams of the MC6800
CPU and of the TMS40L45 static RAM are combined. The
job of the microprocessor systems designer is to determine
whether or not this timing diagram violates any of the
restrictions set out in the MC6800 and TMS40L45 data
sheets.
The start of a CPU memory access cycle begins at A, with
the rising edge of the q~ clock pulse. It is not until B, after a
Value (ns) delay of T 1 s, that the contents of the address bus first
become valid. In Figure 10 the values of VMA and R/~/
min max outputs of the MC6800 are identical. The address inputs to
100 the RAM do not become valid until point C, 73 s after point
270 B. This additional delay is because of the address buffers.
The address lines from the CPU are buffered onto the system
30 bus at the CPU card and buffered from the system bus at
10 the memory card. The worst case delay of two 74LS244
buffers in series is 40 ns.
530
The chip select input to the RAM, S, makes its high to
100 low transition at point D, Ts s after point C. The chip
225 select delay, Ts, is due to the address decoding circuit,
which generates S from the high order ~ddress lines (Als
to A12 for a 4k block of RAM). A typical value for Ts is
40 ns, but the actual value depends on the type of address
decoding circuitry used. Fortunately, the value of T5 is
unimportant in most applications because it is very much
shorter than the access time of the RAM. At point E the
effect of the active low transition on the RAM's chip
t cycle = I O00ns
\
/ \
Address
from CPU
Address
at memory
Chip select
at memory
Memory ddto
output
miTT~8@
d
Figure 10. Read cycle timing diagram of the MC6800 CPU
related to the TMS40L45 static RAM
microprocessors and microsystems
select input is to turn on its three state data bus drivers.
Although data has now been put onto the data bus, it is
not yet valid. The contents of the data bus first become
valid at point F, which occurs at T1 + T3 + T~ s after the
start of a clock cycle. Using the worst case values of TI,
7-3, 7-7, point F occurs no later than 270 + 40 + 450 =
760 ns after the start of a read cycle.
The MC6800 requires the contents of the data bus to be
valid for at least 100 ns (tosR) before the end of the ~2
active high clock phase. At a clock cycle time of 1000 ns,
the data (using the above figures) is valid approximately
240 ns before the rising edge of ~2 - The data set up time
requirement of t~he MC6800 is therefore satisfied by a wide
margin.
The only other critical timing requirement of an MC6800
reaa cycle Is that the data should remain valid for t H s (the
data hold time) after the falling edge of q~2. The value of
t n is given as not less than 10 ns. No problems are presented
here for the following reasons:
• The address of the CPU is held for T2 s(T2 = tAN) after
the rising edge of q~l- As the minimum value of T2 is
30 ns, the data cannot begin to change until after the
address has changed. That is, the data will be valid for.at
least 30 ns after the falling edge of ~2. Note that the
falling edge of ~2 occurs before the rising edge of q~l
• Although the address at the CPU begins to change at
point G, the address at the input to the RAM does not
change until at least 7-4 s later. 7-4 is the minimum delay
through the address buffers, and is not to be confused
with T3, which is the maximum delay through the
address buffers. Whether the maximum or the minimum
propagation delay through a buffer (or any other digital
circuit) is of interest depends on the effect of that delay
on the system. For example, at the beginning of a cycle
when the address first becomes valid the maximum
value of the delay is used because this give a worst case
result. At the end of the cycle when the address shodld
linger (to satisfy the address hold times of memory
components) the delay through the buffer can be
assumed to be at its minimum. The designer of any
system must assume that all components will, collectively,
act against him by being at the end of their tolerance
range which will cgause the most trouble. The designer
must therefore choose components which will still
vol 3 no 5 june 79
operate satisfactorily under these conditions.
• 1-he RAM has a data hold time of Ta (T8 = Tpvs) s
which is specified as not less than 10 ns.
Although the data remains valid until point I, which more
than satisfies the CPU's data hold time requirement, the data
bus is not floated again until point J. In a well designed
system, no other device will attempt to use the data bus
until after point J, otherwise a clash between two bus drivers
(in their low impendance states) occurs. Fortunately, many
6800-based systems use the active high phase of the ~2 clock
to control data bus drivers, which avoids any data bus
contention problems resulting from memory access cycles
extending into the first few ns of the following ~1 clock
phase.
In the above example delays due to data bus drivers have
not been considered in order to keep the complexity of
Figure 10 to an acceptable level. In practice Schottky TTL
bus drivers and receivers seldom cause problems in NMOS
microprocessor systems because the propagation delays
through these buffers are very much smaller than the clock
cycle times of the CPUs. Care must be taken, however, in
systems wher e several buffers are connected in series and
these buffers are controlled by combinational logic elements
which also introduce additional timing delays into the
system. The cumulative effect of these delays becomes
significant when the access time of the RAM is dangerously
close to the time for which the CPU maintains.a valid
memory address on its address bus.
Many 6800-based microprocessor systems require RAMs
with a considerably lower access time than the above
example would suggest. Although the CPU puts out an
address, VMA and R/~/ signals during the ~1 clock phase,
the address decoding arrangements are often designed to
employ ~2 as an enabling signal, reducing the time for
which the address is valid (i.e. at the input to the RAM) by
approximately 200 ns.
The above exercise must also be carried out with the
microprocessor and the RAM write timing diagrams to see
whether they too are compatible.
In next month's article the techniques which el~abl'e memory
components with a capacity of, say, 1 k bytes to be interfaced
with a microprocessor which has the ability to address 64k
locations willb~ discussed.
235