Name: Nehansh

Roll No: 220002050

Batch: E2
Experiment 6
Aim
To perform simulation and implementation of JK Flip-Flop, D Flip-Flop and T Flip-Flop using JK Flip-Flop
and Four-bit Ripple Counter on Xilinx Vivado and uploading onto FPGA boolean board.
Apparatus
Xilinx software, FPGA Boolean board and connecting cable
Vivado Simulation
1. JK Flip-Flop
Design Code: Testbench Code:

Output Waveform:

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2. D Flip-Flop using JK Flip-Flop:
Design Code: Testbench Code:

Output Waveform:

3. T Flip Flop using JK Flip Flop:

Design Code: Testbench Code:

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Output Waveform:

4. Serial Input Serial Output Shift Register:

Design Code: Testbench Code:

Output Waveform:

5. Four-bit Ripple Counter:

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Design code: Testbench code:

Output Waveform:

Conclusion:
We have successfully performed the simulation and implementation of JK Flip Flop, D Flip Flop
and T Flip Flop using JK Flip Flop and Four-bit Ripple Counter on Xilinx Vivado and FPGA
Boolean board.

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