EXPERIMENT- 2

VERILOG CODE for BASIC GATES , HALF ADDER AND FULL

ADDER CIRCUIT

Name: Nehansh Mankad

Roll no: 220002050

Batch: E2

Aim: Test and simulate the simple NOT, AND, OR, XOR gates ,half-adder and full-adder combinational
circuit using Verilog HDL.

Design code:

For NOT gate:

For AND gate:

 For OR gate:

For half adder:

For XOR GATE:

For full adder:
For NOT gate:

Test bench code

Input Output Waveform with time:

Schematic Diagram:
For AND gate:

TB code:
 For OR gate:

Input-Output Waveform with time:

Schematic diagram:
For XOR GATE:

TB Code:
For HALF ADDER:
For Full Adder:
Result: We have simulated the AND gate and half adder circuits and
verified with the truth table.
:
:
TRUTH TABLES:

AND gate:

A B A AND B
0 0 0
0 1 0
1 0 0
1 1 1

OR gate:

A B A OR B
0 0 0
0 1 1
1 0 1
1 1 1

NOT gate:

A NOT A
0 1
1 0

XOR gate:

A B A XOR B
0 0 0
0 1 1
1 0 1
1 1 0

HALF ADDER:

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
 A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1