Question

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Answer

Step 1 of 3
solution:-

From considering the following solution will be

Expalantion

Total length of low - threshold devices

m
= (50 × 10 )
6
logic transistors ×0.05 × 12λ × 0.025μ
λ

therefore 0.05 was 50μm length

and width was 12λ

of Low-VT devices
6
= 0.75 × 10 μm

Expalantion

therefore above was Low VT devices values

Step 2 of 3

Expalantion
Total length of high threshold devices

6 6
m
= (5010 logic)0.95 × 12λ + (950 × 10 )4λ × 0.025μ
λ

Expalantion

By above (950 × 10 was memory transistors

6
)

of high VT devices
6
= 109.25 × 10 μm

Expalantion

follow the above steps

Step 3 of 3

Expalantion

Also, half the transistors are off & contribute to sub threshold leakage

6 na 6 nA
(0.75 × 10 )100 + (109.25 × 10 )10
μm μm
Isub =
2
= 5.84mA

Expalantion

sub value was = 5.84mA

6 nA
(0.75 + 109.25) × 10 μm × 5
μm
Igate =
2

= 275mA

Expalantion

therefore the gate value was =275mA

Static Power Consumption:-

= (584mA + 275mA)(1v)

= 859mw

Expalantion

therefore static power consumption was =859mw

*** Followed from weste CMOS VLSI design book***

Final Answer
As per the question, the solution was explained in a step-by-step process with a clear
explanation.

Estimate the static power consumption was estimated