A Megawatt-Scale Medium-Voltage High
Efficiency High Power Density “SiC+Si” Hybrid
Three-Level ANPC Inverter for Aircraft Hybrid-
Electric Propulsion Systems
Di Zhang, Senior Member, IEEE, Jiangbiao He, Senior Member, IEEE, and Di Pan, Senior Member, IEEE
Abstract— Hybrid-electric propulsion system is an enabling
technology to make the aircrafts more fuel-saving, quieter, and
lower carbide emission. In this paper, a megawatt (MW) scale
power inverter based on a three-level active neutral-point-
clamped (3L-ANPC) topology will be developed. To achieve high
efficiency, the switching devices operating at carrier frequency
in the power converter are configured by the emerging Silicon
Carbide (SiC) Metal-Oxide Semiconductor Field-Effect
Transistors (MOSFETs), while the conventional Silicon (Si)
Insulated-Gate Bipolar Transistors (IGBTs) are selected for
switches operating at the fundamental output frequency. To
obtain high power density, dc-bus voltage is increased from the
conventional 270V to medium voltage of 2.4 kV to reduce cable
weight. Also, unlike the traditional 400 Hz dominated aircraft
ac systems, the rated fundamental output frequency here is
boosted to 1.4 kHz to drive the high-speed motor, which helps
further reduce the motor weight. Main hardware development
and control modulation strategies are presented. Experimental
results are presented to verify the performance of this MW-scale
medium-voltage “SiC+Si” hybrid 3L-ANPC inverter. It is
shown that the 1-MW 3L-ANPC inverter can achieve a high
efficiency of 99% and high power density of 12 kVA/kg.
Keywords—Silicon Carbide, ANPC inverter, high efficiency,
high power density, hybrid-electric propulsion systems.
I. INTRODUCTION
It is known that turboelectric or hybrid-electric propulsion
can increase aircraft energy conversion efficiency, reduce
carbon emissions, and decrease dependency on carbon-based
fuels [1]. To enable hybrid-electric propulsion technology, a
megawatt (MW)-scale high-efficiency high-power-density
electric power system will be of high necessity. To achieve
such objectives, the dc-bus voltage needs to be increased to a
much higher level than the conventional 270V to significantly
reduce the cable weight between power converters and
electric motors as well as decrease the system ohmic losses.
Also, to drive the high-speed motor, which has much higher
power density compared with conventional 400Hz low speed
motor, the output fundamental frequency of the power
inverter needs to be increased as well, e.g., above 1 kHz,
which correspondingly requires higher switching frequency
of the power inverter.
To meet such high switching frequency and high efficiency
targets of the power converters, Silicon Carbide (SiC) Metal-
Oxide-Semiconductor Field-Effect-Transistor (MOSFET) is
certainly the prior choice to its Silicon (Si) counterpart to be
considered for hybrid-electric propulsion applications, given
its superior low-loss switching performance and high-
This work was supported by U.S. National Aeronautics and Space
Administration (NASA) AATT Grant NNC15CA29C. J. He is with the
Electrical Engineering at the University of Kentucky, Lexington, KY, 40506.
(Email: jiangbiao@ieee.org). D. Zhang and D. Pan are with GE Global
Research, Niskayuna, NY, 12309 (Email: zhangd@ge.com, pan@ge.com).
Digital Object Identi er 10.1109/TIA.2019.2933513
0093-9994 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
temperature withstanding capability [2][3]. Besides, a three-
level power converter topology will be preferred rather than
a two-level topology, since it can operate at higher voltage
rating without switching devices serialization, better
harmonic performance to reduce filter weight, and lower
switching losses for high efficiency [4][5]. Additionally, to
minimize system component number for higher system
reliability, a few high-power high-current switching modules
are preferred in the hardware implementation of the converter,
instead of using numerous discrete switching devices. Thus,
to meet all these challenging matrices, a power converter
based on a three-level topology and high-power SiC
MOSFET modules will be the most suitable solution.
To develop such a MW-scale three-level power converter,
the foremost challenge is how to minimize the commutation
loop stray inductance of the converter. Otherwise, the fast
switching speed of SiC MOSFETs, which is the key to reduce
switching losses, has to be reduced due to the potential
pronounced voltage overshoots during switching. For
instance, if a commutation loop has a stay inductance of 50nH,
the switching voltage overshoot (‫ ݅݀ כ ܮ‬Τ݀‫ )ݐ‬can be as high as
1000V for a typical di/dt of 20 kA/ߤ‫ ݏ‬for SiC MSOFETs.
References [6]-[8] demonstrate the performance of SiC
three-level power converters, but those converters are based
on discrete SiC devices with relatively low power ratings, in
which low stray inductance in all commutation loops are
achievable. High-power SiC modules with extremely low
internal loop inductance are reported to build MW-scale
power converters [9][10], but those converters are based on
simple two-level topology, in which the current is always
commutated between two devices in the same half-bridge
module package, of which the internal commutation loop
inductance can be minimized to, e.g., less than 10nH.
However, constrained by the physical dimensions of the
power modules and complex structure of the three-level
converter topologies, when a commutation loop involves two
devices in different modules, i.e., large commutation loops, it
might be unrealistic to optimize the loop inductance to an
ideal level for SiC MOSFETs, e.g. less than 20nH. If large
commutation loop is leveraged in the classic three-level
converter topologies, such as neutral point clamped (NPC)
converters, flying capacitor converters (FCC) and active
neutral point clamped (ANPC) converter with traditional
modulators [11]-[13], the switching speed of the devices has
to be derated to achieve lower voltage overshoots during
switching, which will cause much higher switching losses.
Snubber circuits may effectively reduce voltage overshoots
at turn-off instants of switching devices, but snubber circuits
also cause substantial energy losses [14][15], especially when
the switching frequency is high. Moreover, complex snubber
circuits, which may perform well for Si IGBT based
multilevel converters [16]-[18], could become ineffective for
SiC converters due to the ultra-fast switching speed of SiC
MOSFETs. Thus, a snubber-circuit-less design is preferred.
In addition, there are other challenges for SiC MOSFETs
based three level converters. Firstly, the SiC MOSFET
modules are much more expensive than their Si counterparts
in the present market. It might be even worse for multilevel
converters due to the large quantity of switches required and
the intrinsic uneven loss distribution among the power
devices which constrains the power capability of SiC
MOSFETs from being fully utilized [4][19]. Secondly, SiC
MOSFETs has much weaker short-circuit capability
compared with Si IGBTs [20][21], since Si IGBTs saturate at
much lower current level and possess longer thermal time
constant due to lower current density. Thirdly, to avoid
device over voltage failure during unexpected controller
tripping, the devices in the three-level converters may need
to be turned off in a predefined switching sequence [22].
To address all these challenges mentioned above, a three-
level ANPC (3L-ANPC) converter based on a hybrid
utilization of SiC MOSFETs and Si IGBTs is proposed and
developed for MW-scale hybrid propulsion systems [23]. In
which, the load currents are switched only by SiC MOSFETs
in the same module to achieve low switching losses. In
addition, the utilization of Si IGBT modules helps reduce the
system cost significantly, in addition to limiting the short-
circuit current flowing through the SiC MOSFETs during
external short circuit fault to a safe level and avoiding any
over voltage risk due to improper shutdown sequence.
The remainder content of this paper is organized as
following: In Section II, the system topology, operation
principle and performance benefits of the hybrid 3L-ANPC
converter will be introduced. In Section III, the key hardware
development for the ANPC inverter including the inverter
construction, EMI filter, and ݀‫ ݒ‬Τ݀‫ ݐ‬filter designs will be
presented. In Section IV, the benefits of the hybrid 3L-ANPC
converter will be verified with experimental results. Finally,
conclusions are drawn in Section V.
II. THE PROPOSED “SIC+SI” THREE-LEVEL HYBRID
ANPC INVERTER TOPOLOGY
A. System Topology
The topology of the proposed three-phase “SiC+Si” hybrid
3L-ANPC converter is shown in Fig. 1. As can be seen, each
phase leg consists of six switching devices, i.e., four SiC
MOSFETs namely, ଵ ǡ ଶ , ଷ and ସ , and two Si IGBTs
namely, ହ and ଺ . D1 to D6 are the corresponding body
diodes for SiC MOSFETs and anti-parallel diodes for Si
IGBTs. To simplify the circuit diagrams, the diodes are not
labeled in all the other figures in this paper. The SiC
MOSFETs are connected across the dc bus, configuring the
dc-side switches of the three-level converter structure, and the
Si IGBTs are connected to configure the ac-side switches of
the converter. ଵ and ଶ , as well as ଷ and ସ , are
implemented as two SiC MOSFET half-bridge modules, and
ହ and ଺ are implemented as one Si IGBT half-bridge
module.
Fig. 1. Topology of the “SiC+Si” hybrid three-phase 3L-ANPC inverter.
+Vdc
S1
Small
loop
S2 S5
0V
large
S3 S6
loop
S4
-Vdc
Fig. 2. Commutation loops of the hybrid 3L-ANPC converter (one leg).
As in classic ANPC converters, there are four
commutation loops, including two small loops and two large
loops for each phase leg. Considering the circuit symmetry,
only one small loop and one large loop are shown in Fig. 2.
Due to the minimized commutation loop inductance between
two devices in each half-bridge module, the inductance in the
small loop can be less than 20nH in this case. However, the
inductance in the large commutation loop can be higher than
100 nH in this specific MW-scale ANPC inverter.
B. Operation Principle
An improved PWM modulator is proposed for this hybrid
3L-ANPC inverter [24][25]. In this PWM modulator, to
generate ac voltage, the SiC MOSFETs are operated at carrier
frequency to synthesize the output voltage, in which the
characteristic of low switching losses with the SiC MOSFETs
is fully utilized for high-frequency switching. On the contrary,
the Si IGBTs only need to switch when the output voltage
changes the polarity. In other words, the Si IGBTs are only
switched at the fundamental frequency of the ac voltage. In
addition, Si IGBTs are always soft-switched under zero
voltage or zero current conditions. Thus, the 3L-ANPC
converter dissipates very low switching losses, even though
part of the converter is configured by low-cost Si IGBTs.
To further explain the operation principle, five basic
switching states of the hybrid 3L-ANPC inverter are defined
as: positive state (P) to output a positive voltage of ൅ܸௗ௖ , P-
type zero state (PZ) to output a zero output voltage through
the upper bridge, N-type zero state (NZ) to output a zero
output voltage through the lower bridge, common zero state
(CZ) to output a zero output voltage by turning on all the
middle switches, and negative state (N) to output a negative
output voltage (െܸௗ௖ ሻ, which are all depicted in Figs. 3(a)-(e),
respectively. All the devices marked in red in Fig. 3 refer to
turn-on status.
 +Vdc +Vdc +Vdc
+Vdc
S1 S1 S1

S1
S2 S5 S2 S5 S2 S5
0V 0V 0V

S3 S6 S3 S3
S2 S5
S6 S6
0V
S4 S4 S4

-Vdc -Vdc -Vdc S3 S6 D6

(a) (b) (c)
+Vdc +Vdc
S4
S1 S1

S2 S5 S2 S5 -Vdc
0V 0V
Fig. 5. Positive zero (PZ) state in the classic modulator [11][12].
S3 S6 S3 S6
+Vdc +Vdc +Vdc
S4 S4
S1 S1 S1
-Vdc -Vdc
(d) (e) S2 S5 S2 S5 S2 S5
0V 0V 0V
Fig. 3. Various output voltage states of a hybrid ANPC inverter leg (a) P
state (b) PZ state (c) NZ state (d) CZ state (e) N state. S3 S3 S3
S6 S6 S6
+Vdc +Vdc
S4 S4 S4

S1 S1 -Vdc -Vdc -Vdc

S2 S2 Fig. 6. Commutation from a positive half cycle to a negative half cycle.

S5
0V 0V
S3 S6 S3
S4 S4
-Vdc
-Vdc
Fig. 4. Commutation in the positive voltage cycle of the ANPC inverter.
More specifically, at the positive half voltage cycle, the
commutations only involve the P state and PZ state, as
illustrated in Fig. 4. The duration of P state and PZ state in
each switching cycle can be controlled to output any positive
voltage between ൅ܸௗ௖ and 0. As in the traditional modulator,
ଷ is turned on in P state to clamp the voltage potential of the
bus between ଺ and ସ to 0V. Thus, the voltage across ଺ is
not higher than ൅ܸௗ௖ . However, in PZ state, ଷ can be kept on
or off [11-13]. In the modulator utilized in this work, ଷ is
turned off in the PZ state to force all the load current to only
flow through ଶ and ହ in PZ state, which will be commutated
from ଶ to ଵ in a small commutation loop during the
transition from PZ state to P state.
To be more specific, if ଷ is kept in turn-on status when ଶ
and ହ are on in the PZ state, part of the load current will flow
through ଷ and ଺ when the output current is positive, as
illustrated in Fig. 5. Thus, during the transition from the PZ
state to the P state, the load current flowing through ଶ will be
commutated to ଵ through a small commutation loop, but the
load current flowing through ଷ and ଺ will be commutated
to ଵ via a large commutation loop. Consequently, ଺ will
suffer from hard turned-off in the large commutation loop by
turning-on ଵ . Accordingly, large reverse recovery current
and over voltage across ଺ will occur, which not only
increases device losses, but could also damage ଺ . Such an
issue becomes much more severe when ଵ is turned on very
fast due to the inherent characteristic of the SiC MOSFET.
S5
With the developed PWM modulator in this paper, this
aforementioned issue of hard turn-off in ଺ is solved. The
S6
related risk is that the voltage potential of the bus between ଺
and ସ is not clamped to zero during the PZ state. However,
since the converter will only stay in the PZ state for a
maximum duration of 10 μs in this case before ଷ is turned on
again in the P state, the voltage potential of the bus will not
significantly drift away from 0V, which have been
experimentally verified in [25].
Furthermore, when the output voltage polarity changes
from positive to negative, the commutation sequence of the
ANPC inverter will be PZÆCZÆNZ, as illustrated in Fig. 6.
It should be noted that during the transition from the PZ state
to the CZ state, the turn-on of the switch ଷ and ଺ is zero-
current switching (ZCS) due to the on-state of its parallel
conduction path constituted by ଶ and ହ at the specific
instant. In the CZ state, there are two parallel conduction paths
sharing the load current, either through ଷ and ଺ , or through
ଶ and ହ , so the conduction loss in the switches can be
reduced. In the next transition, from the CZ state to the NZ
state, the turn-off of the switches ଶ and ହ is zero-voltage
switching (ZVS) due to the on-state of its parallel conduction
path constituted by ଷ and ଺ .
The analysis for the negative voltage state of the ANPC
inverter and the transition from the negative half cycle to the
positive half cycle is very similar to the prior analysis, and thus
will not be repeated here.
As discussed above, with the implemented PWM
modulator, the load current is always commutated in small
commutation loops by the SiC MOSFETs in all these voltage
state transitions, in which pronounced turn-off voltage spikes
will be avoided. Additionally, all the Si IGBTs are switched
under ZVS or ZCS conditions, with negligible switching
losses. As a result, the efficiency of the inverter is further
improved.
C. Intrinsic Safe Shutdown Sequence +Vdc +Vdc

Due to the unique 3L-ANPC converter topology, the S1 S1

devices close to the dc side (i.e., ଵ and ସ ) need to be turned
off before switching off the devices close to the ac side (i.e., S2 S5 S2 S5
ହ and ଺ ). Otherwise, if ହ is turned off when ଵ is still on, 0V 0V
the load current will be commutated to ସ and ଺ and the
whole dc bus voltage will be applied across ହ , as shown in S3 S6 S3 S6 D6
Fig. 7. Since ହ is only rated at half of the total dc bus voltage,
ହ will be damaged by over voltage in such a scenario. S4 S4 D4
In the proposed hybrid 3L-ANPC converter, the required
-Vdc -Vdc
shutdown sequence is realized by leveraging the intrinsic
switching speed difference between the Si IGBTs and SiC Fig. 7. Over voltage across ܵହ due to improper shutdown sequence.
MOSFETs. Since ହ and ଺ are implemented as Si IGBTs and
ଵ to ସ are SiC MOSFETs, ଵ to ସ are guaranteed to be +Vdc
turned off earlier than ହ and ଺ when the gate signals are
removed simultaneously by any unexpected operating
conditions such as nuisance controller tripping. SA1 SB1

D. Ride-Through Capability to External Short Circuit Fault

SA2 SA5 SB5 SB2
External line-to-line short circuit fault is one of the most
0V
severe faults that could occur to power converters. As shown 0V
in Fig. 8, the whole dc bus will be shorted during a line-to-line
fault, if Phase-A is in positive state while Phase-B is in SA3 SA6 SB6 SB3
negative state. There are other fault scenarios, but this case
shown in Fig. 8 is the worst case, since the whole dc link
voltage is shoot through which can cause high di/dt due to the SA4 SB4
rapid increase of the short circuit current.
-Vdc
Typically, with the same voltage and current ratings, the
SiC MOSFET will saturate at much higher current level Fig. 8. A dc-bus shoot through due to line-to-line short-circuit fault.
compared to Si IGBT. In addition, SiC MOSFET’s chip size
is much smaller than that of the Si IGBT, leading to shorter
short-circuit withstanding time. Thus, it is much more
challenging to protect SiC MOSFET under short circuit
condition in very short time (e.g., 1 μs). However, as shown
in Fig. 8, in the proposed hybrid ANPC configuration, the
short-circuit current will flow through the Si IGBTs (i.e., ହ
in Phase-A and ଺ in Phase-B), which will be significantly
constrained due to the lower saturated current level of the
IGBTs. Such constraints of the short-circuit current enable the
converter to ride through the line-to-line short-circuit fault.

III. HARDWARE IMPLEMENTATION OF THE THREE-PHASE

THREE-LEVEL HYBRID ANPC INVERTER
A. Power Stage
Based on the proposed hybrid converter topology, a three-
phase 3L-ANPC inverter with a nominal dc bus voltage of
2.4kV (േ1.2kV) and rated active power of 1MW has been
designed. For each phase of the 3L-ANPC inverter, two half-
bridge SiC MOSFET modules (GE 1700V/500A [26]) are
used on the inverter dc side (i.e., ଵ & ଶ , and ଷ & ସ )
switching at carrier frequency, and one half-bridge Si IGBT
module (Infineon FF600R17ME4, 1700V/600A [27]) is
employed on the inverter ac side (i.e., ହ & ଺ ) switching at
fundamental output frequency. Moreover, dc bus bars are
implemented by using laminated heavy-copper printed circuit
boards (PCB) which possess ultra-low stray inductance for the
converter commutation loops. All the semiconductor modules
are mounted on the cold plate in which the water is circulated
through the pipes to extract the heat dissipated from all the
semiconductor devices. The fully assembled converter power
stage is shown in Fig. 9.
Fig. 9. Power stage of the three-phase hybrid 3L-ANPC inverter.
B. EMI Filter
It is critical that the SiC inverter must provide reliable
operation under harsh environmental conditions. The system
must operate without causing unintentional electromagnetic
interference (EMI) to other nearby systems, and it must not
become corrupted or behave improperly due to the
electromagnetic environment created by other nearby systems
or from EMI energy created by the system itself. The EMI
requirements on the dc input side for this system are from DO-
160G [28]. This is used as the most suitable EMI standard
available, as there are no existing requirements for MW-scale
electric or hybrid-electric aircrafts. There are several
subcategories under the DO-160 standard, and the appropriate
one must be selected for the application.
In the aircraft hybrid-electric propulsion system, each
MW-scale power inverter is assumed to be fed by the dc bus,
the voltage or power of which is regulated by a dedicated
power source, namely, a MW-class generator/rectifier system.
Such dc bus is not shared with other electric loads. Thus, the
dc bus is treated as an interconnecting bundle. In addition, the
category L of the DO-160 standard is selected here, since the
electric machine and the inverter are located far from the
aircraft receiver antennas.
The EMI filter here needs to withstand both high current
(500A) and high voltage (2.4kV dc), and a customized filter is
developed to meet these requirements. The filter requires large
attenuation for both the common-mode and differential-mode
currents. The schematic of the EMI filter is shown Fig. 10.
Fig. 10. Topology of the dc-side EMI filter.
C. Output dv/dt Filter
High ݀‫ ݒ‬Τ݀‫ ݐ‬in the output voltages of the SiC power
converters coupled with the mismatch of the surge impedance
between power cables and electric motors can cause
significant surge voltage stress on the stator windings of the
motor, especially if there are long cables interconnected
between the inverter and the motor [29-31]. According to the
theories of transmission lines and traveling waves [29][30],
the critical cable length that could lead to pronounced voltage
spikes equal to one voltage step for a three-level converter,
resulting in 150% of the dc bus voltage across the motor stator Fig. 11. Topology of ݀‫ݒ‬Τ݀‫ ݐ‬filter.
windings, which can be estimated as follows:
݈௖ ൌ ‫ݒ‬଴ ή ሺ‫ݐ‬௥ Τʹሻ ൌ ሺͳΤξߤߝሻ ή ሺ‫ݐ‬௥ Τʹሻ (1)
where, ‫ݒ‬଴ is the propagation speed of the electromagnetic
wave transmitting in the power cables, ߤ and ߝ are
permeability and permittivity of the dielectric material
between conductors of the cables, respectively. Typically, ‫ݒ‬଴
is approximated as half of the speed of the light (i.e.,
ͳǤͷ ൈ ͳͲ଼ ݉Τ‫) ݏ‬. Also, ‫ݐ‬௥ is denoted as the rise time of the
PWM voltage pulses, which determines the value of the
݀‫ ݒ‬Τ݀‫ ݐ‬. Here, assuming the ‫ݐ‬௥ is 200 ݊‫ݏ‬, the cable critical
length ݈௖ will be only 15 meters according to (1). In other
words, for cable length above 15 meters, there will be surge
voltage stress of 150% of the dc-bus voltage across the motor
stator windings for the three-level converter. More severely,
such surge voltage stress will be mainly concentrated on the Fig. 12. The ݀‫ݒ‬Τ݀‫ ݐ‬of the line voltages before and after the ݀‫ݒ‬Τ݀‫ ݐ‬filter.
first few turns of the stator windings closer to the inverter side
that may cause interturn short-circuit fault [31]. Particularly,
1.5 kW, from a systematic performance perspective. Finally,
in aircraft hybrid propulsion systems, there is more stringent
requirement for achieving low ݀‫ ݒ‬Τ݀‫ ݐ‬in the line voltage on the filter inductance, capacitance, and the damping resistance
the machine side, considering the insulation stress and are sized as 1.5 uH, 33 nF, and 15 ȳ, respectively. Fig. 12
derating on the stator windings in the electric machines at high depicts the comparison of the simulated ݀‫ ݒ‬Τ݀‫ ݐ‬before and
altitude fields. Therefore, development of the ݀‫ ݒ‬Τ݀‫ ݐ‬filter for after the filter. It is shown that the ݀‫ ݒ‬Τ݀‫ ݐ‬is reduced from 10
the propulsion drive system becomes very critical to alleviate ܸ݇Ȁߤ‫ ݏ‬to 2.6 ܸ݇Ȁߤ‫ ݏ‬based on the customized filter, which
such voltage stress on the motor stator windings. meets the design requirements.
In this paper, a passive RLC filter is developed to mitigate
the ݀‫ ݒ‬Τ݀‫ ݐ‬in the line voltages applied on the machine IV. EXPERIMENTAL RESULTS
terminals, and the filter topology is shown in Fig. 11. The The fully assembled hybrid 3L-ANPC inverter is shown in
݀‫ ݒ‬Τ݀‫ ݐ‬filter consists of 3-phase inductors, damping resistors, Fig. 13. The total physical volume of the converter cabinet is
and film capacitors in wye connections with the neutral point 14.4 ݂‫ ݐ‬ଷ (i.e., 0.4 ݉ଷ ), with the physical dimensions of 2 ft×2
tied to the dc-bus middle point to further mitigate the ft× 3.6 ft, incorporating the power stage, EMI filter, ݀‫ ݒ‬Τ݀‫ݐ‬
common-mode ݀‫ ݒ‬Τ݀‫ݐ‬. filter, auxiliary power supplies, mechanical accessories, and
A few design constraints have been considered during the the dSPACE digital controller all integrated together. The
filter parameter specifications [32]. Specifically, the ݀‫ ݒ‬Τ݀‫ݐ‬ total weight of the ANPC converter is 98kg without
should be mitigated below 5ܸ݇Ȁߤ‫ ݏ‬considering the insulation accounting for the chassis weight of the dSPACE controller,
requirement of the motor stator windings. Also, the voltage as a custom digital controller is under development. The
drop across the inductors should be within 2%, and the weight breakdown of the whole 1-MW 3L-ANPC inverter
maximum total losses in the ݀‫ ݒ‬Τ݀‫ ݐ‬filter should be lower than system is shown in Fig. 14.
 Fig. 15. Circuit schematic of the three-phase power pump-back setup (the
middle points of the two converter are not connected here).
Fig. 13. Photo of the 1-MW 3-phase 3L-ANPC inverter.

Fig. 16. Three-phase ANPC converter pump-back setup in the laboratory.

Fig. 14. Weight breakdown of the 1-MW 3L-ANPC power inverter system.

To validate the developed hardware functionality and the

proposed PWM strategy, three-phase power pump-back tests
have been conducted in the laboratory. The circuit schematic
of the three-phase pump-back operation is shown in Fig. 15,
in which two units of the three-phase 3L-ANPC converters
are connected in a back-to-back configuration with ac side
coupled through load inductors. One converter unit is
operated as an inverter, and the other one is controlled as a
rectifier with the dc output feeding back to the common dc
source. Since these two converters are connected directly on Fig. 17. The measured line-to-line voltages and phase currents in three-
the dc side, an ac common mode inductor is inserted to limit phase power pump-back tests.
zero sequence current due to zero sequence voltage injection
for the implementation of the space vector modulation. The
related hardware setup is shown in Fig. 16.
The full power of the hybrid 3L-ANPC inverter is
examined through three-phase power pump-back tests under
the conditions of േͳǤʹ of dc-bus voltage, 20 kHz of the
switching frequency, and 1.4 kHz of the fundamental output
frequency. As shown in Fig. 17, about 1.2MVA/1MW is
circulated between the two converters at the rated output
voltages (1650V RMS line-to-line) and rated currents (430A
RMS). In Fig. 17, the waveforms from top to bottom are the
three-phase currents and line-to-line voltages, respectively.
Additionally, the measured top and bottom half dc-bus
voltages as well as the dc-bus neutral to the ground voltage at
the rated operating conditions are all shown in Fig. 18. It
shows that the dc-bus neutral point potential is regulated Fig. 18. The measured top and bottom half dc-bus voltage, and the dc-bus
within 25V, 1% of the rated dc-bus voltage. neutral to ground voltage at rated operating condition.
 The total loss of the 3-phase inverter is measured based on
the flow rate of the cooling water and the temperature rise
between the inlet and outlet water, which can be expressed as:
௏ሶ
ܳ ൌ ቀߩ ቁ ‫ܥ‬௉ ሺܶ௢௨௧ െ ܶ௜௡ ሻ (2)
଺଴଴଴଴
where, ܳ is the heat flow rate (J/s=Watt); ߩ is the coolant
density, ߩ=1000 ݇݃Ȁ݉ଷ ; Also, ܸሶ is the volumetric flow rate
of the water (in the unit of liters/min). ୔ is the heat capacity.
For distilled water, ୔ =4216 Ȁ‰Ԩ. ܶ௢௨௧ and ܶ௜௡ refer to the
temperature of the outlet and inlet water (Ԩ), respectively.
The measured total loss from the 3-phase 3L-ANPC
inverter is 9.6 kW at 1.2 MVA/1MW, which corresponds to
an inverter efficiency of 99% at the power factor of 0.83.
From the perspective of gravitational power density, with a
total weight of 98 kg of the present inverter design, the 3L-
ANPC inverter exhibits a power density of 12 ܸ݇‫ܣ‬Ȁ݇݃.
Additionally, based on the designed dc-side EMI filter, the Fig. 19. The measured conducted EMI based on the dc-side EMI filter.
3L-ANPC inverter system conducted EMI measurement is
shown in Fig. 19. Limited by the test equipment, the EMI test
was only performed at േ1kV dc. The preliminary results
demonstrated that the total conducted EMI (including both
the common-mode and differential-mode EMI) under this
specific condition is below the DO-160E limit line.
Furthermore, the mitigation of the ݀‫ ݒ‬Τ݀‫ ݐ‬in the line
voltages of the inverter with the designed ݀‫ ݒ‬Τ݀‫ ݐ‬filter is also
confirmed in the tests, and the comparison of the measured
݀‫ ݒ‬Τ݀‫ ݐ‬in the line-to-line voltage before and after the ݀‫ ݒ‬Τ݀‫ݐ‬
filter is shown in Fig. 20. As can be seen, the ݀‫ ݒ‬Τ݀‫ ݐ‬after the
RLC filter is reduced to 2.4 ܸ݇ Τߤ‫ݏ‬, which meets the system
design requirement of 5 ܸ݇Ȁߤ‫ݏ‬.
The converter was also tested under external line-to-line
Fig. 20. Measured dv/dt of the line voltages before and after the dv/dt filter.
short circuit condition to confirm its ride-through capability,
and the test results are shown in Fig. 21. The waveforms from
the top to bottom are the voltage across ଵ , the load current,
the gate signal of ହ and the voltage across ହ . The short
circuit current ramped up at t0 when the associated devices
are turned on (please refer to Fig. 8). At the time of t1, the
short circuit current is saturated at 3.3 kA due to the presence
of the IGBT ହ , which is further reduced when the IGBT
junction temperature is increased. The desaturation
protection function of the SiC MOSFET ଵ switched off the
device within 2 μs. Since the load current is limited by the
IGBT, the SiC MOSFET can ride through the fault very
easily at t2. After the SiC MOSFET was turned off, the short
circuit current will remain constant until the IGBT ହ was
also turned off at t3, about 8 μs after the short circuit occurred
as shown in Fig. 21. The switching waveforms of the SiC
MOSFETs and IGBTs under various commutation conditions Fig. 21. Measured SiC MOSFET and IGBT voltages and the load current of
are presented in [25], and thus will not be repeated here. the 3L-ANPC inverter in an external line-to-line short circuit test.

After being fully evaluated under three-phase pump-back
tests, the inverter was further tested with a 1-MW high speed
permanent magnet synchronous motor. The architecture of
the inverter-motor pump-back is illustrated in Fig. 22. As can
be seen, a total dc bus voltage of 2.4 kV is generated from the
480V grid and fed into the hybrid ANPC inverter. The
inverter will drive the high-speed motor with up to 1.4 kHz
of the fundamental output frequency and 1MW active power
based on the dyno. Finally, the power was sent back to the
grid through the control of the dyno drive.
In the tests, the proposed hybrid 3L-ANPC inverter has
successfully passed all the required operating points up to
450Arms/1.2MVA, including four hours of continuous
operation at 390Arms/1.0MVA. The measured converter
losses closely match the results acquired from the three-phase
converter pump-back test. The acquired line-to-line voltage
and current waveforms are shown in Fig. 23. Moreover, the
Total Harmonic Distortion (THD) in the measured phase
current is 4.6% at the rated operating condition (up to 50 th
harmonics), and the frequency spectrum is shown in Fig. 24.
 the hardware designs including the switching device selection,
input EMI filter, and output ݀‫ ݒ‬Τ݀‫ ݐ‬filter have been presented.
Due to the unique characteristics of the hybrid utilization of
the SiC MOSFETs and Si IGBTs as well as the improved
PWM strategy, this converter achieves a high efficiency of
99% and high power density of 12 kVA/kg at nominal
operating conditions. In addition, this proposed hybrid 3L-
ANPC converter possesses intrinsic safe shutdown sequence
in case of unexpected system tripping, in addition to ride-
through capability to external short-circuit faults. The
experimental results verified the performance benefits of this
hybrid 3L-ANPC converter.
ACKNOWLEDGMENT
Fig. 22. Block diagram of the inverter-motor pump-back test. The authors would like to express sincere thanks to the
U.S. National Aeronautics and Space Administration (NASA)
3000
and the Department of Energy (DOE) for their partial financial
2000 support (NASA Grant No. NNC15CA29C and DOE Grant
1000 No. DE-EE0007252) for the work presented in this paper.
Appreciation is also given to all the colleagues at GE Global
Vll [V]

0
Research and GE Aviation who provided much support in the
-1000
power converter tests.
-2000

-3000
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
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