Nyquist-Rate A/D Converters

David Johns and Ken Martin

University of Toronto
(johns@eecg.toronto.edu)
(martin@eecg.toronto.edu)

slide 1 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997

A/D Converter Basics

V in A/D
B out
V ref
–1 –2 –N
V ref ( b 1 2 + … + b N 2 ) = V in ± x
+ b2 2
1 1
where  – --- V LSB < x < --- V LSB (1)
 2 2 
• Range of valid input values produce the same
output signal — quantization error.
V LSB
B out ---------- = 1/4 = 1 LSB
V ref
11

10

01
V in
00 -------
-
0 1/4 1/2 3/4 1 V ref

slide 2 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997
 Analog to Digital Converters
Low-to-Medium Medium Speed, High Speed,
Speed, Medium Accuracy Low-to-Medium
High Accuracy Accuracy
Integrating Successive Flash
approximation
Oversampling Algorithmic Two-step
(not Nyquist-rate)
Interpolating
Folding
Pipelined
Time-interleaved

slide 3 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997

Integrating Converters
S
2 S
 1
 S 2
C1

–V S Comparator b
in 1 R 1
1 V
x b
Control 2
V
ref Counter b
logic 3

(Vin is held constant during conversion.) b

N

Clock

1 B
f = ----------- out
clk T
clk

• Low offset and gain errors for low-speed applications

• Small amount of circuitry
• Conversion speed is 2N+1 times 1/Tclk

slide 4 of 26
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© D.A. Johns, K. Martin, 1997
 Integrating Converters
V
x – V in3
Phase (I) Phase (II)
(Constant slope)

– V in2

– V in1

Time
T
1

T (Three values for three inputs)

2

• Count at end of T2 is digital output

• Does not depend on RC time-constant

slide 5 of 26
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© D.A. Johns, K. Martin, 1997

Integrating Converters
0

H(f) –20 dB/decade slope

–10
(dB)

–20

–30
Frequency (Hz)
10 60 100 120 180 240 300 (Log scale)

• Notches the input frequencies which are multiples of

1/T1

slide 6 of 26
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© D.A. Johns, K. Martin, 1997
 Successive-Approximation Converters
Start
Signed input

Sample V in, V D/A = 0, i = 1

• Makes use of binary search algorithm
• /Requires N steps for N-bit converter
V in >V D/A
No
• Successively “tunes” a signal until
within 1 LSB of input
Yes

bi = 1 bi = 0
• Medium speed
• Moderate accuracy
V D/A →V +V ⁄2D/A ref
i+1
V D/A → V – (V ⁄ 2 )
D/A ref
i+1

i →i+1

No
i ≥N
Yes

Stop

slide 7 of 26
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© D.A. Johns, K. Martin, 1997

DAC Based Successive-Approximation

V in
Successive-approximation register
S/H (SAR) and control logic

b1 b2 B
b out
N
D/A converter
V D/A V ref

• Adjust V D/A until within 1 LSB of V in

• Start with MSB and continue until LSB found
• D/A mainly determines overall accuracy
• Input S/H required

slide 8 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997
 Charge Redistribution A/D
s
V ≅0 2
x
SAR
16C 8C 4C 2C C C
b b b b b
1 2 3 4 5
s 3
1. Sample mode

s s
1 V = –V 2
V
in
V
ref
x in
16C 8C 4C 2C C C
b b b b b SAR
1 2 3 4 5
s 3

s
1
V ref V V 2. Hold mode
V x = – V in + ----------- s in ref
2
2
SAR
16C 8C 4C 2C C C
b b b b b
1 2 3 4 5
s 3

3. Bit cycling
s
1
V V
in ref

slide 9 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997

Charge Redistribution A/D

• McCreary, 75
• Combines S/H, D/A converter, and difference circuit
• Sample mode: Caps charged to V in , compar reset.
• Hold mode: Caps switched to gnd so V x = – V in
• Bit cycling: Cap switched to V ref . If V x < 0 cap left
connected to V ref and bit=1. Otherwise, cap back to
gnd and bit=0. Repeat N times
• Cap bottom plates connected to V ref side to minimize
parasitic capacitance at V x . Parasitic cap does not
cause conversion errors but it attenuates V x .

slide 10 of 26
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© D.A. Johns, K. Martin, 1997
 Algorithmic (or Cyclic) A/D Converter
Start
Signed input
• Operates similar to successive-
approx converter
Sample V = Vin, i = 1
• Successive-approx halves ref voltage
each cycle
No
V>0
• Algorithmic doubles error each cycle
Yes (leaving ref voltage unchanged)
bi = 1 bi = 0

V → 2(V – Vref /4) V → 2(V + Vref /4)

i →i+1

No
i>N

Yes

Stop

slide 11 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997

Ratio-Independent Algorithmic Converter

Out

Vin
S/H Cmp Shift register

Vref /4
X2 S/H
Gain amp –Vref /4

• McCharles, 77; Li, 84

• Small amount of circuitry — reuse cyclically in time
• Requires a high-precision multiply by 2 gain stage

slide 12 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997
 Ratio-Independent Algorithmic Converter
Q1

C2 C2
C1 C1
Verr Verr
Cmp Cmp
Q1 Q1

1. Sample remainder and cancel input-offset voltage. 2. Transfer charge Q1 from C1 to C2.
Q1

C2 C2
C1 C1
Verr Verr
Cmp Cmp
Q2
Q1+Q2 Vout = 2 Verr
3. Sample input signal with C1 again
after storing charge Q1 on C2. 4. Combine Q1 and Q2 on C1, and connect C1 to output.

• Does not rely on cap matching

• Sample input twice using C1; hold first charge in C2
and re-combine with first charge on C1

slide 13 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997

Flash (or Parallel) Converters

• Peetz, 86; Yoshii, 87; Hotta, 87; and Gendai, 91
Vref

Vin • High-speed
R
----
2 Over range
• Large size and power hungry
R
V r7
• 2N comparators
R V r6
• Speed bottleneck usually large cap
R V r5 load at input
(2N–1) to N N digital
R V r4 encoder outputs
• Thermometer code out of comps
R V r3
• Nands used for simpler decoding
R
V r2
and/or bubble error correction
R
V r1
• Use comp offset cancellation
R⁄2 Comparators

slide 14 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997
 Issues in Designing Flash A/D Converters
• Input Capacitive Loading — use interpolating arch.
• Resistor-String Bowing — Due to Iin of bipolar
comps — force center tap (or more) to be correct.
• Signal and/or Clock Delay — Small arrival diff in
clock or input cause errors. (250MHz 8-bit A/D needs
5ps matching for 1LSB) — route clock and Vin
together with the delays matched [Gendai, 1991].
Match capacitive loads
• Substrate and Power-Supply Noise — V ref = 2 V
and 8-bit, 7.8 mV of noise causes 1 LSB error —
shield clocks and use on-chip supply cap bypass
• Flashback — Glitch at input due to going from track
to latch mode — use preamps in comparators and
match input impedances

slide 15 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997

Flash Converters — Bubble Errors

• Thermometer code should be 1111110000
• Bubble error (noise, metastability)— 1111110100
• Usually occurs near transition point but can cause
gross errors depending on encoder
V
in
…
…
…
…

V (2N–1) to N N digital
ri
encoder outputs

[Steyaert, 93]
…
…
…

• Can allow errors in lower 2 LSB but have MSBs

encoder look at every 4th comp [Gendai, 91]
slide 16 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997
 Reduced Auto-Zeroing
• Tsukamoto et al, ISSCC/96
• Spalding et al, ISSCC/96
• Reduce the auto-zero portion of conversion
— auto zero when not performing conversion
— add one more comparator and ripple up auto-zero
Advantages
• Lower power — less current drawn from ref string
• More speed — more time for conversion
Disadvantage
• 1/f noise not rejected as much

slide 17 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997

Two-Step A/D Converters

V
in
V
4-bit 4-bit 1 V
q 4-bit
Vin MSB 16 LSB
D/A
A/D A/D
Gain amp

First 4 bits Lower 4 bits

(b , b , b , b ) (b , b , b , b )
1 2 3 4 5 6 7 8

• High-speed, medium accuracy (but 1 sample latency)

• Less area and power than flash
• Only 32 comparators in above 8-bit two-step
• Gain amp likely sets speed limit
• Without digital error correction, many blocks need at
least 8-bit accuracy

slide 18 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997
 Digital Error Correction
S/H2
(8-bit accurate) V
in
Gain amp
4-bit 4-bit
V
1 V
q
Vin S/H1 MSB D/A 8 S/H3
A/D
(8-bit accurate) (5-bit accurate)
(8-bit accurate)
(4-bit accurate)
5 bits
Digital delay

Error 5-bit
D correction LSB
4 bits
A/D

(5-bit accurate)

8 bits

• Relaxes requirements on input A/D

• Requires a 5-bit 2nd stage since Vq increased
• Example, see [Petschacher, 1990].

slide 19 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997

Interpolating A/D Converters

V
ref
= 1 V • Goodenough, 1989
V (Overflow) • Steyaert, 1993
V in 4
latch
16
R
latch
15
• Kusumoto, 1993
R 14
R latch
R 13 • Use input amps to
latch
V
3 R 12 amplify input around
latch
0.75 V
R 11 reference voltages
latch
b
R
R 10 1 • Latch thresholds less
R
latch
9
Digital b2
latch
logic critical
V R
2 latch
8
b3
0.5 V R 7 • Less cap on input (faster
V 2c
R
latch
b than flash)
V 2b 6 4
R latch
V 2a R 5

V R
latch • Match delays to latches
1 4
latch
0.25 V R 3 • Often combined with
latch
R
Input
amplifiers
R 2 folding architecture
latch
R 1
latch
R Latch
comparators

slide 20 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997
 Interpolating Converters
5.0 V2
V 2b
V 2c

V1
(Volts) Latch threshold

V 2a

V
0 in
0 0.25 0.5 0.75 1.0
(Volts)

I I I I
1 2a 2b 2

3 3 3 3
9 3 3 9

current interpolation
(Relative width sizing shown)
(All lengths same)

slide 21 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997

Folding A/D Converters

b
2-bit 1
MSB A/D
converter b Folding block responses
2
• Reduce number of
V ref = 1 V
1
V1 latches using folding
(Volts) Threshold
V
Folding 1
block Latch
0
• Save power and area
0 4
------
8
------
12
------
11 V
in
 4 8 12 16  (Volts)
V r =  ------, ------, ------, ------ 
 16 16 16 16  V2
16 16 16
• Similar concept to 2-step
V Threshold
in V
Folding
block
2 Latch
Digital
b
3 • Folding rate of 4 shown
logic
b 3
------ 7
------
11
------
15
------
V
in
for 4 bit converter
 3 7 11 15  4 16 16 16 16
V r =  ------, ------, ------, ------  V3
 16 16 16 16 
Threshold
V
Folding 3 Latch
block
2 6 10 14 V
 2 6 10 14 
------
16
------
16
------
16
------
16
in
V =  ------, ------, ------, ------ 
r
 16 16 16 16  V4
Threshold
V
Folding 4 Latch
block

1 5 9 13 V
 1 5 9 13 
------
16
------
16
------ ------
16
in
V r =  ------, ------, ------, ------  16
 16 16 16 16 

slide 22 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997
 Folding Circuit
V
CC
R R
1 1

V Q1 V
a b Q2

V out

V V V V
r1 r2 r3 r4

I I I I
b b b b
V
in
V EE
(a)
V out

V –V
CC BE

V –V –I R
CC BE b 1 V in
V r1 V r2 V r3 V r4

(b)

slide 23 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997

Folding with Interpolation

b
2-bit 1
MSB A/D
converter b Folding-block responses
2
V = 1 V V1
ref 1
V (Volts) Threshold • Folding usually used
V 1
4
R
Latch
0 V
in
with interpolation
0 4 8 12 1
------ ------ ------
R
V2
16 16 16 (Volts)
• Reduces input cap (
V V Threshold
in 2
Folding
block Latch
Digital
b3
V
• Without interp, same
logic in input cap as flash
3 7 11 15
b4 ------ ------ ------ ------
 3 7 11 15  16 16 16 16
V r =  ------, ------, ------, ------  R V3
 16 16 16 16  Threshold • [van Valburg, 1992]
V
3 Latch V
R 2 6 10 14
in • [van de Grift, 1987]
------ ------ ------ ------
16 16 16 16
V4
Threshold
• [Colleran, 1993]
V
Folding 4
block Latch
V4 V
V in
4 1 5 9 13
------ ------ ------ ------
16 16 16 16
 1 5 9 13 
V r =  ------, ------, ------, ------ 
 16 16 16 16 

slide 24 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997
 Pipelined A/D Converters
b 1

QN
DN
b

N – 1-bit shift register

2

QN-1 QN-1
DN-2 DN-2

b N–1

Q1 Q1 Q1
D1 D1 D1 b N

Vin 1-bit 1-bit 1-bit 1-bit

DAPRX DAPRX DAPRX DAPRX

(DAPRX - digital approximator)

Analog pipeline

bi

Vi–1 S/H Cmp

–Vref/4
2 Vi
Vref/4

slide 25 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997

Time-Interleaved A/D Converters [Black, 80]

f1

S/H N-bit A/D

f2

f0
S/H N-bit A/D
Digital
V output
in f3 Dig.
S/H mux

S/H N-bit A/D

f4

S/H N-bit A/D

• Use parallel A/Ds and multiplex them

• Tone occurs at fs/N for N converters if mismatched
• Input S/H critical, others not — perhaps different tech for input S/H

slide 26 of 26
University of Toronto
© D.A. Johns, K. Martin, 1997