4-4 Binary Adder-Subtractor

• Half adder
– 0+0=0 ; 0+1=1 ; 1+0=1 ; 1+1=10
– two input variables: x, y
– two output variables: C (carry), S (sum)
– truth table x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
 S = x'y+xy'
C = xy
the flexibility for implementation
S=x⊕y
S = (x+y)(x'+y')
S' = xy+x'y'
S = (C+x'y')'
C = xy = (x'+y')'
 x y z C S
• Full-Adder
0 0 0 0 0
– The arithmetic sum of three 0 0 1 0 1
input bits 0 1 0 0 1
– three input bits 0 1 1 1 0
• x, y: two significant bits 1 0 0 0 1
• z: the carry bit from the 1 0 1 1 0
previous lower significant bit 1 1 0 1 0
– Two output bits: C, S 1 1 1 1 1
C
S = x'y'z+x'yz'+ xy'z'+xyz
C = xy + xz + yz
S = z⊕ (x⊕y)
= z'(xy'+x'y)+z(xy'+x'y)'
= z'xy'+z'x'y+z((x'+y)(x+y'))
= xy'z'+x'yz'+xyz+x'y'z
C = z(xy'+x'y)+xy
= xy'z+x'yz+ xy
Binary adder - Ripple-Carry Adder
 tadder = (N-1)tcarry + tsum
• Carry propagation
– when the correct outputs are available
– the critical path counts (the worst case)
– (A00,B0,C0) > C1 > C2 > C3 > (C4,S3)
– > 8 gate levels
 Carry-Bypass Adder
P0 G1 P0 G1 P2 G2 P3 G3 Also called
Carry-Skip
Ci,0 C o,0 C o,1 Co,2 Co,3
FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2

Multiplexer
FA FA FA FA
Co,3

Idea: If (P0 and P1 and P2 and P3 = 1)

then Co3 = C0, else “kill” or “generate”.
 Carry-Bypass Adder (cont.)
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
Setup tsetup Setup Setup Setup
tbypass

Carry Carry Carry Carry

propagation propagation propagation propagation

Sum Sum Sum tsum Sum

M bits

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

• Reduce the carry propagation delay
– employ faster gates
– look-ahead carry (more complex mechanism, yet faster)
– carry propagate: Pi = Ai⊕Bi
– carry generate: Gi = AiBi
– sum: Si = Pi⊕Ci
– carry: Ci+1 = Gi+PiCi
– C1 = G0+P0C0
– C2 = G1+P1C1 = G1+P1(G0+P0C0)
= G1+P1G0+P1P0C0
– C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0
PS MODIFIKOVANE ARHITEKTURE

g i = a i ⋅ bi p i = a i + bi

si = pi ⋅ g i ⊕ ci c i +1 = p i ⋅ ( g i + c i )
 LookAhead - Basic Idea
A0, B0 A1, B1 ••• AN-1, BN-1

Ci,0 P0 Ci,1 P1
Ci, N-1 PN-1

S0 S1 ••• SN-1

C o, k = f (A k, B k, Co , k – 1 ) = Gk + P k Co , k – 1
 Look-Ahead: Topology

Expanding Lookahead equations: VDD

C o, k = Gk + Pk (Gk – 1 + Pk – 1 Co , k – 2 ) G3

G2

G1
All the way:
G0
C o, k = Gk + Pk ( Gk – 1 + P k – 1( … + P1 ( G0 + P0 Ci , 0 ) ) )
Ci,0
Co,3

P0

P1

P2

P3
– Logic diagram
• 4-bit carry-look ahead adder
– propagation delay
ČETVOROBITNI SABIRAČ SA CLA
(PARALELNIM PRENOSOM)
 Binary subtractor
• A-B = A+(2’s complement of B)
• 4-bit Adder-subtractor
– M=0, A+B; M=1, A+B’+1
• Overflow
– The storage is limited
– Add two positive numbers and obtain a
negative number
– Add two negative numbers and obtain a
positive number
– V=0, no overflow; V=1, overflow
 4-5 Decimal Adder
• Add two BCD's
– 9 inputs: two BCD's and one carry-in
– 5 outputs: one BCD and one carry-out
• Design approaches
– A truth table with 2^9 entries
– use binary full Adders
• the sum <= 9+9+1 = 19
• binary to BCD
• The truth table
• Modifications are needed if the sum > 9
–C=1
• K=1
• Z8Z4 = 1
• Z8Z2 = 1
– modification: -(10)d or +6
• Block diagram
AKUMULACIONI SABIRAČ

AKUMULATOR R.
FUNKCIJE ARITMETIČKO-LOGIČKE
JEDINICE (ALU SN74181
LOGIČKA ŠEMA ALU SN74181
Multipliers
 Binary Multiplier
• Partial products – AND operations
• 4-bit by 3-bit binary multiplier
The Binary Multiplication
M+ N– 1
Z ·· × Y
X Zk 2
k
= =
∑
k=0
⎛M – 1 ⎞⎛N – 1 ⎞
⎜ i⎟⎜ j⎟
X i2 ⎟⎜ ∑ Yj2
⎜ ∑
= ⎜ ⎟
⎟⎜ ⎟
⎝ i=0 ⎠⎝ j = 0 ⎠
M – 1⎛ N – 1 ⎞
⎜ i + j⎟
=
∑ ⎜
⎜
∑ Xi Yj2 ⎟
⎟
⎝
i=0 j= 0 ⎠

with
M –1
i
X =
∑ Xi 2
i=0
N– 1
j
Y =
∑ Y j2
j= 0
 The Binary Multiplication

1 0 1 0 1 0 Multiplicand
x 1 0 1 1 Multiplier
1 0 1 0 1 0
1 0 1 0 1 0

0 0 0 0 0 0 Partial products

+ 1 0 1 0 1 0

1 1 1 0 0 1 1 1 0 Result
 The Array Multiplier
X3 X2 X1 X0 Y0

X3 X2 X1 X0 Y1 Z0

HA FA FA HA

X3 X2 X1 X0 Y2 Z1

FA FA FA HA

X3 X2 X1 X0 Y3 Z2

FA FA FA HA

Z7 Z6 Z5 Z4 Z3
 The MxN Array Multiplier
— Critical Path
HA FA FA HA

FA FA FA HA Critical Path 1
Critical Path 2

Critical Path 1 & 2

FA FA FA HA
 Carry-Save Multiplier
HA HA HA HA

HA FA FA FA

HA FA FA FA

HA FA FA HA

Vector Merging Adder

 Multiplier Floorplan
X3 X2 X1 X0

Y0
Y1 HA Multiplier Cell
C S C S C S C S
Z0

FA Multiplier Cell
Y2
C S C S C S C S
Z1 Vector Merging Cell

Y3
C S C S C S C S X and Y signals are broadcasted
Z2 through the complete array.
( )

C C C C
S S S S

Z7 Z6 Z5 Z4 Z3
 Wallace-Tree Multiplier
Partial products First stage
6 5 4 3 2 1 0 6 5 4 3 2 1 0 Bit position

(a) (b)

Second stage Final adder

6 5 4 3 2 1 0 6 5 4 3 2 1 0

FA HA
(c) (d)
 Wallace-Tree Multiplier
x3y2 x2y2 x3y1 x1y2 x3y0 x1y1 x2y0 x0y1
Partial products x3y3 x2y3 x1y3 x0y3 x2y1 x0y2 x1y0 x0y0

First stage
HA HA

Second stage FA FA FA FA

Final adder
z7 z6 z5 z4 z3 z2 z1 z0
 Wallace-Tree Multiplier
y0 y1
y2

y 0 y 1 y2 y3 y4 y5
Ci-1
FA

y3
FA FA
Ci Ci Ci-1
Ci-1
FA Ci Ci-1

y4
FA
Ci Ci-1 Ci Ci-1
FA

y5

Ci FA
FA

C S
C S
 Multipliers —Summary
• Optimization Goals Different Vs Binary Adder

• Once Again: Identify Critical Path

• Other possible techniques

- Logarithmic versus Linear (Wallace Tree Mult)
- Data encoding (Booth)
- Pipelining
FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION
 TABLICA MNOŽENJA U ROM-u
M3N=P
n3 a7 d7 p7
n2 a6 d6 p6
N n1 a5 d5 p5
n0 a4
ROM d4 p4
m3 a3 d3 p3 P
m2 a2 256*8 d2 p2
M m1 a1 d1 p1
m0 a0 d0 p0

Za tablicu množenja dva 8-o bitna broja potreban je ROM kapaciteta 64K*16
Za tablicu množenja dva 16-o bitna broja potreban je ROM kapaciteta 4G*32
 Table Lookup Arithmetic Def’n
• Given an m-variable function
f(xm-1, xm-2, …, x1, x0)
the table lookup evaluation of f requires the
construction of a 2u x n table that holds, for each
combination of input values (needing a total of u-
bits to represent), the desired n-bit result.

• The u-bit string is obtained by concatenating the input

values to form the table address.
• The n-bit value is the content of the table
corresponding to that address.
 Arithmetic by Table Lookup
• Advantages
– memory is denser and can be made more robust
than random logic
– reduces the cost of hardware development
– more flexible (allows last minute design changes)
– reduces the number of building blocks
• Disadvantages
– slow for large tables
– table size grows exponentially in input size
 Direct Table Lookup
2u x n
Operand(s)
Table
u bits
(ROM or RAM)

Result(s)
n bits

• Unary (single variable) functions (1/x, ln x, x2)

limited to 12 to 16 bits of operand precision (212
to 216 table)
• Binary functions (xy, x/y, xy) limited to 8 bits of
operand precision (28+8=16 table)
 Indirect Table Lookup
• One way to reduce the table size is to see if the binary
function can be converted into a unary function
(requires pre- and postprocessing logic)

processing Smaller
Operand(s) Logic
Pre-

Table(s)
u bits
(ROM or RAM)

Postprocessing
Much smaller Logic
than u !
Result(s)
n bits
Constructing Big Mult’s from Small
• Can synthesize a 2b x 2b multiplier from
four b x b multipliers and a three operand
addition operation
AH AL

BH BL

AL BL

3b bits AL BH b bits AL BH

AH BL AH BH AL BL

AH BH AH BL

4b product
Množač 8-o bitnih brojeva realizovan 4-o
bitnim tablicama množenja i sabiračima
 Indirect Table Lookup Example
• Pre- and postprocessing hardware should be
simple and fast
• Consider the multiplication identity that
converts the problem to one of squaring
X * Y = ¼ [(X + Y)2 – (X – Y)2]

– Preprocessing does X+Y and X-Y

– Two tables to lookup (X+Y)2 and (X-Y)2
– Postprocessing does subtract and 2-bit right shift
 Indirect Multiplication
X (n-bits)
Adder 2** ROM 2n+1addr
(X+Y)2 bits
2n
content
2** ROM
Y (n-bits) Subtractor bits
(X-Y)2

Subtractor
n +1 bits
Right shifter (¼)

X*Y (2n-bits)
 Množač realizovan
akumulacionim sabiranjem
Redno-paralelni množač
Četvorobitni redno-paralelni množač
Sekvenca rada registara množača
Generator kontrolnih signala
prethodnog množača
Kolo za deljenje binarnih brojeva A/B
Primer deljenja binarnih brojeva
1010000 / 0100
Primer deljenja binarnih brojeva
101 / 1000