R

Clock Buffers/Multiplexers

I
O
IB
UG331_c4_04_080906

Inputs Outputs
I IB O
0 0 -
0 1 0
1 0 1
1 1 -

Notes:
1. The dash (-) means no change.

Figure 2-4: IBUFGDS Component and Truth Table

The default IBUFGDS I/O standard is LVDS_25.

Clock Buffers/Multiplexers
Clock buffers/multiplexers either drive clock input signals directly onto a clock line
(BUFG) or optionally provide a multiplexer to switch between two unrelated, possibly
asynchronous clock signals (BUFGMUX).
Each BUFGMUX element, shown in Figure 2-5, is a 2-to-1 multiplexer. The select line, S,
chooses which of the two inputs, I0 or I1, drives the BUFGMUX output signal, O, as
described in Table 2-5. As specified in each data sheet’s “DC and Switching
Characteristics” section, the S input has a setup time requirement. It also has
programmable polarity.

BUFGMUX

I0
O

I1

S
UG331_c4_05_080906

Figure 2-5: BUFGMUX Clock Multiplexer

Table 2-5: BUFGMUX Select Mechanism

S Input O Output
0 I0 Input
1 I1 Input

Spartan-3 Generation FPGA User Guide www.xilinx.com 53

UG331 (v1.8) June 13, 2011