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Chapter 3: Using Digital Clock Managers (DCMs)

Table 3-18: Extended Spartan-3A Family: Direct Input Connections and Optional External DCM Feedback
I/O Bank 0
Differential Pair Differential Pair Differential Pair Differential Pair
N P N P N P N P
Package Pin Number for Single-Ended Input Pin Number for Single-Ended Input
VQ100 P90 N/A P89 P88 P86 P85 P84 P83
TQ144 P132 P130 P131 P129 P127 P125 P126 P124
FT256 B8 A8 D8 C8 A9 C9 D9 C10
FG320 C8 B8 B7 A8 B9 A10 C9 B10
FG400 A8 A9 E10 D10 C10 A10 E11 D11
CS484 B8 A8 E11 F10 B9 A9 F11 E12
FG484 E11 D11 C11 B11 A11 A12 E12 C12
FG676 C13 B13 G13 F13 A14 B14 J14 K14
    Associated Global Buffers    
GCLK11 GCLK10 GCLK9 GCLK8 BUFGMUX_X1Y10 GCLK7 GCLK6 GCLK5 GCLK4

BUFGMUX_X2Y10
BUFGMUX_X1Y11

BUFGMUX_X2Y11
Top Left DCM Top Right DCM
XC3S50A: DCM_X0Y0 XC3S50A: DCM_X1Y0
XC3S200A, XC3S400A: DCM_X0Y1 XC3S200A, XC3S400A: DCM_X1Y1
XC3S700A/1400A, Spartan-3A DSP XC3S700A/1400A, Spartan-3A DSP
FPGA: DCM_X1Y3 FPGA: DCM_X2Y3
   
H G F E
Global Clock Line
D C B A
   
Bottom Left DCM Bottom Right DCM
BUFGMUX_X1Y0

BUFGMUX_X1Y1

BUFGMUX_X2Y0

BUFGMUX_X2Y1

XC3S50A: N/A XC3S50A: N/A

XC3S200A, XC3S400A: DCM_X0Y0 XC3S200A, XC3S400A: DCM_X1Y0
XC3S700A/1400A, Spartan-3A DSP XC3S700A/1400A, Spartan-3A DSP
FPGA: DCM_X1Y0 FPGA: DCM_X2Y0
GCLK12 GCLK13 GCLK14 GCLK15 GCLK0 GCLK1 GCLK2 GCLK3
    Associated Global Buffers    
Differential Pair Differential Pair Differential Pair Differential Pair
Package P N P N P N P N
Pin Number for Single-Ended Input Pin Number for Single-Ended Input
VQ100 N/A N/A P40 P41 P43 P44 N/A N/A
TQ144 N/A N/A P54 P55 P57 P59 P58 P60
FT256 R7(1) T7(1) P8 T8 N9 P9 R9 T9
FG320 U8 V8 U9 V9 U10 T10 V11 U11
FG400 W9 Y9 V10 W10 Y11 V11 U11 V12
CS484 Y11 Y10 AA12 AB12 U12 V12 AB13 AA14
FG484 U11 V11 W12 Y12 AA12 AB12 V12 U12
FG676 AA13 Y13 AF13 AE13 Y14 AA14 AF14 AE14
I/O Bank 2
1. N/A in XC3S50A

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UG331 (v1.8) June 13, 2011