R

Other Information

unavailable in the bottom left quadrant. However, the top left (TL) quadrant clock A can
still solely use the output from either BUFGMUX_X2Y1 or BUFGMUX_X0Y2 as the source.
To estimate the quadrant location for a particular I/O, see the footprint diagrams in the
device data sheets. For exact quadrant locations, use the PlanAhead floorplanning tool. In
the QFP packages the quadrant borders fall in the middle of each side of the package, at a
GND pin. The clock inputs fall on the quadrant boundaries, as shown in Table 2-8.

Table 2-8: Clock Quadrant Locations

Clock Pins Quadrant
GCLK[3:0] BR
GCLK[7:4] TR
GCLK[11:8] TL
GCLK[15:12] BL
RHCLK[3:0] BR
RHCLK[7:4] TR
LHCLK[3:0] TL
LHCLK[7:4] BL

Choosing Top/Bottom and Left-/Right-Half Global Buffers

The software generally use the top/bottom global buffers as the first choice for high-fanout
clock signals. If there are more than eight clocks in a design, the left-/right-half buffers can
be used. Floorplanning is recommended for designs requiring more than eight clocks,
since the loads on the left-/right-half buffers must be restricted to one half of the device, or
restricted to one quadrant to allow the most freedom for the global input using the same
routing resource.

Spartan-3 FPGA Global Clock Routing

The Spartan-3 FPGA BUFGMUX drives the vertical global clock spine belonging to the
same side of the die — top or bottom — as the BUFGMUX element in use. The two spines
— top and bottom — each comprise four vertical clock lines, each running from one of the
BUFGMUX elements on the same side towards the center of the die. At the center of the
die, clock signals reach the eight-line horizontal spine, which spans the width of the die. In
turn, the horizontal spine branches out into a subsidiary clock interconnect that accesses
the CLBs, IOBs, block RAM, and multipliers. For more details, see the Spartan-3 Family
Data Sheet.

Other Information

Clock Power Consumption

Dynamic power dissipation can be reduced through optimization of the clocks used in a
design.
To minimize the dynamic power dissipation of the clock network, the Xilinx development
software automatically disables all clock segments not in use. To take full advantage of

Spartan-3 Generation FPGA User Guide www.xilinx.com 61

UG331 (v1.8) June 13, 2011