R

Chapter 2: Using Global Clock Resources

BUFGCE and BUFGCE_1

The BUFGCE primitive creates an enabled clock buffer using the BUFGMUX select
mechanism. BUFGCE is a global clock buffer with a single gated input. Its O output is "0"
when clock enable (CE) is Low (inactive). When clock enable (CE) is High, the I input is
transferred to the O output.

BUFGCE
CE

I O

UG331_c4_08_080906

Inputs Outputs
I CE O
X 0 0
I 1 I

Figure 2-9: BUFGCE Component and Truth Table

The BUFGCE is built from the BUFGMUX by multiplexing a fixed value for one input. The
default value is Low when disabled. The BUFGCE_1 primitive is similar with VCC
connected to I1, making the output High when disabled. It also uses the BUFGMUX_1
primitive to guarantee there are no glitches during the transition between inputs.
Figure 2-10 shows the equivalent functionality, although the library component truly is a
primitive. The CE inversion is built into the BUFGMUX functionality. The "0" source can be
fed from any convenient unused LUT.

BUFGMUX
I0
O

O
XGND I1

CE_IN S
INV
GND UG331_c4_09_080906

Figure 2-10: Equivalent Functionality of BUFGCE

XST Synthesis of Clock Buffers

XST automatically infers clock buffers on the highest fanout clock nets up to the device or
user limits, but synthesis constraints can be used to control the usage of clock buffers.
BUFFER_TYPE selects the type of buffer to be inserted on the input port. The default is
BUFGP, which is equivalent to a BUFG.
NET “signal_name” buffer_type={bufgdll|ibufg|bufgp|ibuf|bufr|none};
The BUFFER_TYPE parameter can be used on a generic input to make sure that the global
clock buffer is used (= BUFGP). It can also be set to NONE to prevent the automatic usage
of a global clock buffer. This replaces the older constraint CLOCK_BUFFER, which should
not be used in new designs.

56 www.xilinx.com Spartan-3 Generation FPGA User Guide

UG331 (v1.8) June 13, 2011