R

Chapter 3: Using Digital Clock Managers (DCMs)

Symbol
Spartan-3 FPGA: DCM
Spartan-3E/3A/3AN/3A DSP FPGAs: DCM_SP
CLKIN CLK0
CLKFB CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX

RST CLKFX180

PSEN STATUS[7:0]
PSINCDEC LOCKED
PSCLK PSDONE
UG331_c3_01_011008

Figure 3-4: DCM Design Primitive

Connection Ports
Table 3-6 lists the various connection ports to the Digital Clock Manager. Each port
connection has a brief description, which includes the signal direction, and which DCM
function units require the connection. Table 3-5 provides the abbreviated name for each
function unit used in Table 3-6.

Table 3-5: Functional Unit Abbreviations for Table 3-6

Abbreviation Functional Unit
DLL Delay-Locked Loop
PS Phase Shifter
DFS Digital Frequency Synthesizer

72 www.xilinx.com Spartan-3 Generation FPGA User Guide

UG331 (v1.8) June 13, 2011