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Chapter 3: Using Digital Clock Managers (DCMs)

Table 3-6: DCM Connection Ports (Cont’d)

Functional Unit
Port Direction Description
DLL PS DFS
LOCKED Output All DCM features have locked onto the CLKIN frequency. Clock   
outputs are now valid, assuming CLKIN is within specified limits
(as described in “DCM Clock Requirements”). See “Frequency
Synthesizer (CLKFX, CLKFX180).”

0 DCM is attempting to lock onto CLKIN frequency.

DCM clock outputs are not valid.
1 DCM is locked onto CLKIN frequency. DCM clock
outputs are valid.
1-to-0 DCM lost lock. Reset DCM.

PSDONE Output Variable Phase Shift operation complete. See “Variable Fine Phase 
Shifting,” page 123.

0 No phase shift operation is active or phase shift

operation is in progress.
1 Requested phase shift operation is complete. Output
High for one PSCLK cycle. Okay to provide next
Variable Phase Shift operation.

Attributes, Properties, or Constraints

Table 3-7 lists the various attributes for the Digital Clock Manager. All attributes are set at
design time and programmed during configuration. Most, except for the Dynamic Fine
Phase Shift function, cannot be changed by the FPGA application at run-time. To set an
attribute, set <ATTRIBUTE>=<SETTING> as appropriate for the design entry tool.

76 www.xilinx.com Spartan-3 Generation FPGA User Guide

UG331 (v1.8) June 13, 2011