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    Datasheet (1) (d421000c

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    Datasheet (1) (d421000c

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    Datasheet (1) (d421000c

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    NEC NEC Electronics Inc. BBE D MM G427525 0032028 4 MENECE APPLICATION NOTE 53 uPD421000/1PD421001/uPD421002 1-MEGABIT DYNAMIC RAMs TeHH-23-03 Description NEC's uPD421000, wPD421001, and yPDs2I002 are ‘-megabitéynamic RAMs (ORAMs) manufactured with the CMOS ‘um fine-pattarn process and configured 8s 1,048,876 x1 bit Ae shown In table 1 this family of RAMS has boon dveloped inavatety of speeds and packages, The package pin layouts appoar in igure 1. Configurations “Tho wPD421000, uPD421001, and yPD421002(tigures2, 8, and 4) consist of memory cell arrays, input and ‘Output buffers, clock generators, refresh addross ‘counters, and row and column decoders ‘The basic layout ofthe chip is shown Inflgura 6. As be seen from the diagram, the whole memary cell Memory Coll Structure Dynamic RAMs generally feature one-transistor ‘memory col, which equi ‘area used by four-tran lop) memory cals In translator eal! provi ‘hip size, data must be row Intervals for proper data stra ‘capacitor. A cross-sectional view of ‘one-transistor memory coll used in the uPD¢21000- series DRAM is shown in figure 6 ‘This tronch design uses theee-dimensional rather than planar capacitors, thereby a the thickness of the Insulating ‘errors caused by a-particles, an effective capacitance In excess of $0 femtotarads ((F) is used in tho {NPDAZI000, uPD421001, and wPO4ZI002 Figure 1. Pin Layouts geesese 5. Ereaeieres, oa WE € ELECTRONICS INC "BE D eua7S25 0032025 b MMNECE uPD421000-SERIES DRAMs NEC TF Y6-23-03- Table 11,048,576 x 1-51 DRAM Family kes owt aa one res) Tove) ot ae ae ta C= SOF mare ee Veaapnguse ae ae ee ee isa paes Pe —— i a ae ia Sas i it ion Tt Figure 2, uPD421000 Block Diagram == | severe i 278 NE C ELECTRONICS INC NEG ~38E D mm Gu27525 GO32030 2 MMNECE #PD421000-SERIES DRAMs F40-23-03 = iS a on 7 een = ARB cock — Biches ogee =| = =e = a)" = 7 [Er = ee foe si) . I i ez WE C ELECTRONICS INC 38E D MM bY27525 0032031 4 MANECE #PD421000-SERIES DRAMs NEC OO 0 2528 ‘Figure 8. Chip Layout of wPD421000-Serles RAMS : all ele BEAHEE iil EET TT NE C ELECTRONICS INC 38E D MM 6427525 0032032 & MMNECE NEC #PD421000-SERIES DRAMs T-Y4-23-03 12 Opera ‘memory calls, and then amplified. At the same time, eee tho original data is rewritten to memory cals Csi, Indynamic RAMs, changes init tine potential caused Co ene a een en cate by the minute charging and discharging of memory “Goluinn address, and the Cs data on tho Bly line Is ‘cali are amplified by a sense amplifior to be road as Fasged via the /0 bus and ¢ data ampli to Gxternal ‘olther tor 0. Memory call and sense amplifier equiva- — Ereuite, See ‘Write and read operations are identical, up to ampli- Toread the data trom storage coll si, therowaddress fiction and rewriting of momory col data selected by & selects word line Wy, and data from memory cols row address, After being passedto the bitlinoselected Cou. Csay.« «Cant connectedto WLiis passedio by the column address, write data is writen Into a bit lines BLi, Bla, « -. Blo, These data signals are target memory cll euch as Cay), Sines the number of passed to the sense amplifiers, where they first yelsory cole selected by ene vow adareen in the ‘are compared with data from dumey ce Cont, Com devices Is 2048, 2048 momory colls aro ref Cont. connected simultaneously with the simultaneously n each memory or rettesh cyclo 10d Figure Z_Memory Cell and Sonse Ampllia Equivalent Clreults ows om wy Mma Cas Lest _ 4 m Fis fen Pa = ca ea es hfe me fiers For a a Fic fi Pe + ? + FL cou HL [AL on i hina fF oe = Pies fis, Fes + t ? joe yee oon Worn >} Serta CorsctrOvmy Cn xe edhe 6-261 NE C ELECTRONICS INC uPD421000-SERIES DRAMs Pin Functions ‘WAS and AS (or G3}, Tho PD421000-sries DRAM Include two chip activator Inputs: RAS and CAS (or G8), row address strobe and column addres strobe (or chip solec). In addition to ‘addresses Aa through Aa, selecting ther line, and activating the sonse amplifiors for read ang ‘write operation, the RAS input also refreshes the 2048 bite selected by row addrotses Aq through Ap, The GAS input latches In column addresses (on the ‘uPD421000 and the uPD42100%) and connects the Chip’ Internal /O busto tho once ampliies activated by the FAS clook, thereby executing data Input or ‘output operations. ‘Apthrough As. Solection of an individual 1048 576-word x t-blt memory cell 20-bit addross input. The three devices all feature an tchod Into memory ledge ofthe RAS clock. After an Internal timing the column address input crcults become. active, Flow-through latohes (voltage-level activated, not dgo-tiggered) for column addresses ar onabled on ‘the nPD421000 or wPDs21001, and tho column tly begin propagating through t latches to the column decoders. A calum ‘on the wD421002, the column address input ‘ircultryisnoteontroled by CS, and column addresses ‘must be hold valid untl data read out Setup times (asa a tas) and hol i tou foradcess input ie defined oatoneh o tho falling edges of AAS and GAS (08 or ‘yea on tha wPO421000) In aca operation, 0 row hates te poco bets to RAS inputs eolvatess ‘noe in arene hus eiiches to column auresses EAS or GS ett. WE (wre Enable} Road and write cytes are executed by activating the BAS and GAS (or G8) inputs and eontrolingWE. Anes write cycles executagit WE {atvate botorethofalingedge of AS (or C8) during Avrtecyco,andatatowrteead-modly-wre) jae ‘Is executed if the WE input is activated later, 6-202 BSE D M™ 6427525 0032033 8 MENECE NEG T-¥e-23-03 Read and Write Cycles FAStothacolorm addracs less thantnnp er) Toe AS (or CS) soces tine of eng eval Wt Clay from HAS to GAS (or CS) i roar han tao imax) andthe delay from the column address toCAS (or CS) is reser then go (mer) Theadsressaccoss tm of tnalsvalil hedolay trom ASto the column ecarss irate then tga en, and he daly om te colar acrarsto GRE or G8) islas tan ag ax) utput esta ls hold vad unt GAS for C8) becomes Inactive again (igure 8). Wie gles are executed by ctvatng tho FAS, CRS a WE inate, Wete dat a atoned By the 19 go of CAS (or) or WE, whichever agers ‘AWE Input applied botore the TAS (or TS) input Inates'an early wit oye, whereby welt cata a ited by fing wdge ot CXS or 6) Conversely, aWE input applies after the CRS (or 5) Input iniais a lato wie cycle (e8d-modly-wite yee), whereby wre daa latched into the chip by the fling edge of WE. The slats af Dour la not gugranioes ints cay ot opndson he ing at with respect to RAS and GAS (or CS). If WE is acti- vated at eet toy altar the OAS (or C8) Input, and at Teast tayo alter the BAS Input write operation 1s abled Inthe same memory eyla during wen the ‘ead datas Rotresh Cycles ‘The process of rewriting data held in @ memory col, refreshing, ls performed by a sense smpilir Inthe ‘uPD421000-series DRAMs. Tho threo devices are Capable of executing tho same RAS-only and CAS (ores). Telresh cycles as ao executed In ther conventional, gor ‘ms period. Since in image memory applications, row addresses ‘Aa through Ag afo read or writen sequentially within, ‘ms, the accessing iteet initiates reteshing and 0 ‘dettiona etresh cycles are required NE € ELECTRONICS INC 38E D M™ b427525 0032034 T MENECE NE ‘¢ uPD421000-SERIES DRAMs 70-23-03 Figure 8. Access Timing WE € ELECTRONICS INC BBE D uPD421000-SERIES DRAMs FAS-only Roltesh Cycle. FAS-only refreshing is ‘executed slmply By leaving the CAS (or G8) input Inactive (high level) during a RAS clock cycle. This ‘yele uses the 612 lower addressos specified by row refreshed ina singio ‘TAS for BS} Bet fefreshing I exeoUted using the addresses generated by the chip's Internal address counter when. CAS {or 6S) is activated (low level) In advance of the RAS input (igure 10). Figure 9._RAS-Only Refresh Cycle WH Gu27se5 0032035 1 MBNECE NEC T-4b-23-03 ven in systems without an address output trom the betore-RAS refreshing allows ‘ecomplihed with @ minimum of peripheral circu (figure. High-Speed Accoss Cycl Im addition to being capable of stand: 5, the ‘uPD&2I000 Is equipped with fest-page access, the {uPO421001 wit bbteaccess, andthe zPO421002 with Statleccolumn access (table 2). Tio ee at uaa oti ‘riot iat woo Figure 10. TAS (or CS)-Betor erat) 6-204 NE € ELECTRONICS INC BSE D Mi b427525 0032036 3 MMNECE NEG #PD421000-SERIES DRAMs T-Yo-23-03 Figure 1. Address Multiplexing Sony Retesh + seuss feo y| ‘eon St. eae Same oa eons sera tow atten hs a Table 2,_ Major Characteristic of Fast-Page, Nibble, and Statl-Column Modes Tn es Tat) ce Tin) ar ie Wiad PORT oe ‘av ap Tandon sess on ano oe a Gane ul cel accessed yo bough hp. : co nom page 2 om Pao one Tow Cuno at ‘Sting ean tr nee mad aces av: fw aston Raa serv nora Gwe vul cel acess etd by Bough Ag 208 NE C ELECTRONICS INC aE D #PD421000-SERIES DRAMs Fast-Page Mode, Fast;page mode makes It possible to randomly access datain the samerow adéross(igures ‘Zand 13). The 1024 bits of memory are obtained from the combinations of column address Inputs Agthrough ‘Ag within one row address n the PD421000. Up to mm .u27525 0032037 5 MMNECE NEC T= 46-23-03 1998 continuous accesses can bs {0srs voraion beter the maxim (100 2) Is reached “The to cy time for andom fat cyolas oquvalnt to tons top 2h Figure 12. Memory Coll/Sense Amplifir Block ofthe uPD421000 16) a 1S LL 1S 7 = ° cs iS io i : C= 5 iS 6-206 © teeryent NE C ELECTRONICS INC Figure 19,_Fast-Page Timing «38E D MM GH27S25 0032038 7? MENECE #PD421000-SERIES DRAMs T Ye" 23-03 G NE C ELECTRONICS INC #PD421000-SERIES DRAMs INibbte Mode, In nibble-made cycles, the fret data location i spectied by row and column addresses Ay through Ap during a read or writo cycle (tabla 2 and figures 14 and 18). When the PD421001 Internally sequences the wo higheet-ord Ing thenext CAS clock cycle, readand writocyeles can bo executed in le time than in fast-page operation. ‘Figure 14._Nibblo-tode Block Diagram and Examplo of Accoss Sequence RAE Dm bW27525 0032039 9 MENECE NEC TFYe 23-03 addresses (Aa) dur roy eeren ‘war 6-288 ona tepwoupe NE € ELECTRONICS INC BBE D MB G427525 0032040 S MENECE NEC uPD421000-SERIES DRAMs T= Y¥6-23-03 Figure 18._Nibble-ttode Timing apt betas f sawn TX = Kem XT TTTTITTLLLLLLLT LLL LL TILL. 7 7 _ _ -—t te 1 fe 55) ow 777K XXX ENTRAN ah TI BS] = ZZZZ/Z2X XTX IK XTX ow “fom bE 6-209 NE C ELECTRONICS INC 38E D MM GY27525 OO3Z04% 7 MMNECE #PD421000-SERIES DRAMs For the 80-n8 version, the a 198 cycle time perbitin nibble mode's 70ns, when bits are accessed duringa Tong tas cycle (igure 18)-By using multiplesPD42t00t Figure 16._ Average Dé NEC TFC 2303 dices, high-speed cache and frame butter applica- lions ar possible (figure 17). Pitenaiedd 6-200 NE C ELECTRONICS INC B8E D m™ G427525 CO3Z042 9 MENECE NEC #PD421000-SERIES DRAMs T0-23-03 ‘Figure 1% High-Speed Data Accoss Using Nibble Mode ty ee Boom HEI NEC ELECTRONICS INC uPD421000-SERIES DRAMs Statle-Column Mode. Row and column addresses are functionally equval access, The avallable number of continuous accesses fon one row, and the eycte timing, are also similar to fast-page operation. Figure 18._Statle-Column Timing BOE D m™ G427525 0032043 0 MANECE NEG FWo-23-03 Ina statle-column device, there are no setup oF hold timing roqulrements for ead addresses, CS may bs held low continuously in the ON-stale. To alow this. feature, the column addresses must be maintained as valid inputs forthe duration of each cycle. There are Tow other restrictions on timing (gure 18). fee i. +» LIL = XULK === XULK = MLK 2X 6-202 NE C ELECTRONICS INC NEC BSE D M™ 427525 OO32044 2 MMNECE F¥623-03 uPD421000-SERIES DRAMs Precautions Precautions when using the uPD421000, uPD421001, ‘uPD421002, and other DRANS should be carefully ‘observed in the areas listed below ‘© Power-on and initialization ‘Supply voltage fluctuations causedby peak currents * Relationships between addross/data inputs and divers + FAS and ORS (or 78) generation Power-On and Initialization. Dynamic RAMS operate by the charging and discharging of gato and internal circuit capacitances. Theretore, dummy RAS clock aycles must be executed to charge internal potentials {othe preseribed levels when powers applied, Dummy RAS cycles ae also necossary when there has been no ‘accassing (reading, writing, or refreshing) for periods longer than the refresh interval (igure 18). ‘To control transistor threshold voltages and decrease Internal stray capacitance, DRAMs are uevally equipped with a substrate voltage generator eit to supply tho chip's interior with negative voltage, Approximately 100 us is required to generate an ‘adequate negative voltage level after power i applied and Voo= 48. When the power ie suwitohed on, a peak current dependent on the levels of RAS, CAS (or GS), and WE is reached during the rising of Veo. This peak ‘current—maximum when RAS and CAG (or CS) are ‘active and WE is inactve—can be minimized by using lock input pullups on RAS and GAS (or CS) so that their rise times correspond to the riso time of the power supply. Supply Voltage Fluctuations. Since 1 and 0 logic (storage) operations are executed by the charging ang discharging of capacitances, including the memory ‘ells, the peak currant goneratod is dependent on ‘charge and discharge timing. ‘This poak current Is concentrated just ater RAS and {GAS (or CS) transition intervals (igure20) with peak value of about 129A, Since this currents source of folse (voltage drop) in the memory eystem supply voltage, decoupling by multilayer coramie capacitors with excellent frequency response fs necessary. Ifthe fayerage of the 120-mA peak current pulse asta about ‘s00ns, the capacitance required tokeap the drop inthe supply voltage line at about 04 V wil be caleulated as follows: 120 (mA) x 100 (os) 01 Therefore, when designing the memory board, keep the power and groundieadsas shorts possibleforlow Inductance. Decoupling capacitors of about 02 must be inserted between the power supply lines for ‘each memory devies. With careful board layout, the se of fever but larger capacitor Is possible. Capac tors usedinoneot every wo memory device locations, with a value of perhaps 0.83 uF, can provide elisa tery decoupling in many cases. Figure 18._Dummy Cycles etter Power le Applied Pacing og | dy They, tne See er | one Se | wus 6.298, uPD421000-SERIES DRAMs ‘Addross/Data Inputs and Drivers. Probably the most In adgrese-multiplexed DRAMS such a the WPDAZIO00, 4PD&RI001, and 4PD421002 (where row fand column addresses’ ro supplied as two sets of Inputs), addresses supplied externally have to be switched by a multiplexer. “The sequence of ths timing must be designed very 0 starts with the setting of thespectied hold time for row addressos is met, the addresses_are switehed to got up column address input. Once CAS {or CS) falls, the pacified hold time for column Aaddrossos must be satltied, Wen GAS (or) is activated within thotime specified {or taco (max), the setup time for column adresses is more dificult to quarantes than when taap is longer than taco (ex), Because one external address driver has to arive moro than one address pin in an array of DRAMs, The address multiplexers delay time Is Ineceased by load capacitances larger than the typical value. For illustration, measurements of output delay times for certain drivo load capacttances are shown in igure a. 2ign of high-density memory boards having Tiumber of memory devices, partitioning of ocomes necessary because of wiring and betaken ‘data may be destroyed even itnothing is writen. ‘FAS and CAS (or C8) Generation, in addi reading the address {generate the basi timing forall DRAM circult opera tions, The intonal ting generators are connected in al fgahion, and are completely controled by the basic RAS and CAS (or CS) inputs. Because of this. ‘control. the memory syetom design must prevent aos Sltches from being generated in the BAS and CAS {or€3) inputs. [BAS and GAS (or C5) timing is spectied In terms of ‘minimum values. High o loW-evel pulses that do not these minimum values oen result In Incorrect ‘output data (because thore Is Insufilent time for Senze amplifier operation), and can also lea destruction of write data. Therefore, the prevention of noise glitches must be carefully considered in logic ‘and circuit design. e204 Bee DME Gu27S25 OOSEONS 4 MENECE NEG Fle-23-03 gure 21. fect of Load Copctonce on TTL (7408) Output Deny nd Wanton Tn cu=209F NE C ELECTRONICS INC NEG BOE D MM 6427525 OO3Z04L & MMNECE FYb-23-03 #PD421000-SERIES DRAMs V40™ MICROPROCESSOR APPLICATION Features The 4PD70208 (also known as V40) fg a high-pertor= mance 8-bit CMOS microprocessor featuring 16-bit architecture in the GPU, and including s number ‘of other peripheral devioos within the same ehip. The CPUisequipped witha powertulsotot instructions that ‘cover bitprocessing and multiple-ength, packed-8CD ‘operations, high-speed multiplications and divisions, 1nd varlabie‘ength bit and field manipulations, ‘This device combines high-speed processing with flexibiity in @ varlety of applications. The on-chip peripherals Include a clock generator with a timer” ‘counter and programmable walt contro, refresh con- {rol serial conto, interrupt control and DMA control nits In addition'to allowing moro compact rmlero- computer systems, the V40 has a simplified system design. ‘When connected to the 4PD421000-serles DRAM the 40 does not require an external refresh timor or 18 big reduction In the required. Memory Mapping In the V40, memories of up to 1 megaword can be Accessed using adress Information (Ag through Ao) ‘output from the 20-bit address bus (igure 22) ‘The first 1024 bytes, O through SFFH, are allocated to Interrupt vectors (although aroas that cannot be used by tho system can be used eleewhore). Addresses FFFFOH through FFFFBH aro used for stating and Fesoting purposes; FFFFCH through FFFFFH ar Teserved for future use and cannot be used here. The femaining address space, 400H through FFFEFH, Is ‘not allocated and may be used as desired ‘As shown in figure 23, with a data bus width of @ bits In the V40, GPU connections to the memory require ‘only that tho 20-bit addross output from the GPU. ‘accepted in the t-mogabyta address space. Byte data Iseccessed in one buscyce,and word datals accessed Intwo bus eyetes, Because ofthis simple connection requiroment itis ‘only necessary to allocate the system control ROM to addresses of atleast FFFFOHand disable the ROM-area RAM (since 1 megabyte is alady taken up by eight ‘megabit DRAM). The mothod used may inv ‘lther deselecting the ROM-area RAM by adecodsr, or ‘executing bank itching to use the ontirearea as RAR area. The exemple included for this epplication shows the former method because itis simpler. ‘Figure 22._V40 Memory Mspping Figure 23._V40 Memory Intertace a Baa 6-205, NE C ELECTRONICS INC BBE D HPD421000-SERIES DRAMs Hardware Configuration Since refresh addrossos andthe timing contol outputs can bo supparted by programming an-ohip circuits, ‘the generation of RAS and CAS (or CS) timing Ist nly major DRAM support not provided directly bythe a0 (igure 24). Memory Access Timing Generation ‘Although V40 memory access timing can be generated {rom either thebus status or MW/R/MAO, the uPO71088 system bus controller Is used in this application ample to enable connections to slightly slower: ged memories. The RAS and GAS (or CS) signals aro thus generated by decoding the bus status. mi 6427525 0032047 & MMNECE atoris shown ntigure igure 26 To gonerato timing ‘th this system controler, bus status signal Ba sample by tho CPU clock output (our) atthe ising odgo of the Toyo, and RAS is {onorted trom FF at the fling edge of our at the nd of Tt. The multiplex control egnal (MPR) used in Atddrese switching during memory eycles a generated by RAS. Alter RAS la gonaratd, tls delayed bythe ring odgo of the wxtrnal 6-Mttz clock to create PX, thigh fe then paseod tothe data selector input. As can be sen trom figure 26, memory acces time it02/(@our)~(leox-+ TTLdalay time). Event al clock of 18 Miz ie used, a2 dovce Is Sutficlont (RAS access time In the-t2 dvi is 120 ns). Figure 24. Hardware Configuration forthe Uso of 1 DRAME at | = 6-296 NE C ELECTRONICS INC BBE D MM b427525 0032048 T MBNECE NE' ¢ #PD421000-SERIES DRAMs Tb 23-03 ‘igure 28. ‘TAS and AS (or 8) Timing Generator Fes feemer Loan aie e207 NE C ELECTRONICS INC ABE D MM G427525 UO3Z049 1 BENECE 4PD421000-SERIES DRAMs NE ¢ FV 6- 23-03 ‘igure 26. HAS and GAS (or G8) Timing Sequence Tor ia FeBoum mace ‘rare, 6-208 NE € ELECTRONICS INC NEC 38E D M™ 6427525 0032050 8 MENECE T-Yb-23-03 uPD421000-SERIES DRAMs Rotresh Timing Generation Refreshing for the 4PD421000, uPO421001, and {4PD421002 Is executed by selecting 612 linas In 8 ms Inthe V40, memory refreshing can be handled easly by outputting the REFRG control signal and the Aa {through Ag refresh addresses, Thoso signals ara con- trolled by programming the eetreah contol register (RFC), allocated to 0 address FFF2H (igure 27), Figure 27_ Programming of Retrosh Control Register wor 8 ery frowae re Tie tire tosh inn 85H eck Tne 6-200 NE C ELECTRONICS INC BBE D uPD421000-SERIES DRAMs “This function generates the REFRG contra signal in 2coordanoe with the programmed Interval. tn this pplication example, REFRis vse sae gon. tian ofthe GAS (or GS) clock uring retresh oy thoreby nitating BAS-only ofeshing Figures 28 2B show how o gener memory addresses and ow fo contol dala Input and. guput by using contol Sonate gneratedby the RAE and CAS or ing erator, Figure 20. shows the timing for V4O- Generated trash addresses. ‘Tha programmed values or the control register sppear In figure 27 {also tofer to the 4P070208/uP070216 User's Marval). 5 ‘Authorization forthe P070208/,070216 refresh con- {ral unit to use the memory bus can bo sat elthor to top priory orlowest prot, depending on thehnold status tthe refresh request. Top priory Issetifsoven refresh quests ara baing held, and refreshing Is executed consecutively until the numbor of requests is reduced totnvee, ‘Although a wait interval of maximum duration (the ‘looks i Inserted by the bult-in walt contol unt, ta eset input le applied ator power Is eppied, interval need beinserted actual applications. Ther fore, tho walt control register has o be resot wien the a0 Is used at 8 tH, Wilt control registers WOY2 (FFFGH), WY! (FFFSH), land WMG (FFF4H) writs program data at these /O ‘8ddressos using an VO wrto instruction (igure 31). 6300 mm £427525 0032051 T MENECE NEG T° We 23-03 - Figure 28._ Memory Access Generation Figure 29. Data Input end Output Controt A uss —p>—| owen

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