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21EC023 SV Project File
21EC023 SV Project File
Project File
For
EC322 System Verilog Programming
Prepared by
Pruthviraj Mohite (21EC023)
Submitted to
Submitted at
DEPARTMENT OF ELECTRONICS & COMMUNICATION
Faculty of Technology & Engineering, CHARUSAT
module tb_top;
always begin
#5ns clk = ~clk;
end
initial begin
t1.run();
#150ns $finish;
end
endmodule
adder_desing.sv
module adder(
input clk ,
input reset,
input [3:0] a ,
input [3:0] b ,
input valid,
output [4:0] c );
//Reset
always @(posedge reset)
tmp_c <= 0;
// Waddition operation
always @(posedge clk)
if (valid) tmp_c <= a + b;
assign c = tmp_c;
endmodule
interface.sv
interface adder_if(input clk, reset);
logic [3:0] a, b;
logic [4:0] c;
logic valid;
endinterface
transaction.sv
class packet;
bit[3:0] a = 4'b0101;
bit[3:0] b = 4'b1000;
bit[4:0] c;
endclass
configuration.sv
class configuration;
static int pkt_num = 5;
endclass
generator.sv
class generator;
configuration cfg;
packet pkt;
mailbox mgen;
function new(mailbox GEN2DRV);
mgen = GEN2DRV;
endfunction
task run();
repeat(cfg.pkt_num) begin
pkt = new();
pkt.randomize();
mgen.put(pkt);
$display("pkt from generator");
pkt.print();
end
endtask
endclass
monitor.sv
class monitor;
mailbox mmon;
packet pkt;
configuration cfg;
virtual adder_if vif;
function new (mailbox MON2SCB, virtual adder_if VIF);
mmon = MON2SCB;
vif = VIF;
endfunction
task run();
//for(int i=0; i<cfg.pkt_num; i++) begin
repeat(cfg.pkt_num) begin
pkt = new();
@(posedge vif.clk);
if(vif.valid) begin
pkt.a = vif.a;
pkt.b = vif.b;
@(posedge vif.clk);
pkt.c = vif.c;
@(posedge vif.clk);
mmon.put(pkt);
$display("pkt from monitor");
pkt.print();
end
//else
// i--;
end
endtask
endclass
scoreboard.sv
class scoreboard;
mailbox mscb;
packet pkt;
configuration cfg;
function new (mailbox MON2SCB);
mscb = MON2SCB;
endfunction
task run();
repeat(cfg.pkt_num) begin
//pkt = new();
mscb.get(pkt);
if(pkt.a + pkt.b == pkt.c) begin
$display("-----------PASS-------");
end
else begin
$error("Packet failed ");
$display("Failed pkt from scoreboard");
pkt.print();
end
end
endtask
endclass
driver.sv
class driver;
packet pkt;
mailbox mdrv;
configuration cfg;
virtual adder_if vif;
task run();
repeat(cfg.pkt_num) begin
mdrv.get(pkt);
@(negedge vif.clk);
vif.a = pkt.a;
vif.b = pkt.b;
vif.valid = 1;
@(negedge vif.clk);
vif.valid = 0;
@(posedge vif.clk);
@(posedge vif.clk);
$display("pkt is driven on interface from driver");
pkt.print();
end
endtask
endclass
agent.sv
class agent;
mailbox gen2drv;
mailbox mon2scb;
generator gen;
monitor mon;
scoreboard scb;
driver drv;
task run();
fork
begin
gen.run();
end
begin
drv.run();
end
begin
mon.run();
end
begin
scb.run();
end
join
endtask
endclass
environment.sv
class environment;
agent agt;
function new(virtual adder_if vif);
agt = new(vif);
endfunction
task run();
agt.run();
endtask
endclass
test.sv
class test;
environment env;
task run();
env.run();
endtask
endclass
Output: