Microprocessor Engineering

Lecture:

Basics of Instruction Execution

Von Neumann Stored Program Principle
(Both for Memory & I/O Device)
Von Neumann Stored Program Principle
Application Specific Integrated Circuit (ASIC)
Interfacing Memory and I/O
 n:2^n decoder for address locations

and

K bit registers connecting k-bit data bus

 e.g. 3 GHz

f = 1/t

so, T = 0.33 nS is one clock cycle

The compromise is
between
Cost Vs Speed
 e.g. if I have 4GB of
memory with 8 bit of
data bus
then
The address bus will
be 32 bit (i.e. 2^32)

So, if I have 4GB of memory with 16 bit

of data bus then
The address bus will be 31 bit (i.e. 2^31)
and with 32 bit data bus, the address
bus will be of 30 bit (i.e. 2^30).
Practice Question
Practice Question

1 Byte : 4,194,304 bits => 2^22 bit

2 Byte : 2,097,152 bits => 2^21 bit

4 Byte : 1,048,576 bits => 2^20 bit

 HEX

Adr Bus = 1 2
12 bit
(2^12 = 4K)
Fetch Exec
Data Bus =
T1 T2 T3 T1 T2 T3
16 bit

3 4
1: READ/LOAD

5: ADD T1 T2 T3 T1 T2 T3 T4

2: WRITE/STORE

5 6

T1 T2 T3 T1 T2
 HEX

Adr Bus = 1 2
12 bit
(2^12 = 4K)
Fetch Exec
Data Bus =
T1 T2 T3 T1 T2 T3
16 bit

3 4
1: READ/LOAD

5: ADD T1 T2 T3 T1 T2 T3 T4

2: WRITE/STORE

5 6

T1 T2 T3 T1 T2
Accumulator based processor
(3T + 3T) + (3T + 4T) + (3T + 2T) = 18 T x (1/ 2 GHz) = 9 nS