Sampre Soro Tion Birla Institute of Technology and Science, Pilani, Hyderabad Campus Comprehensive Examination Second Semester, 2022-23 Microprocessor Programming and Interfacing Time: 3 hours Date: 08-05-2023 Code: ECE/EEE F241 Max. Marks: 120 ‘Name (in CAPS): ID Number (in CAPS): Recheck Request (Question Number only) For Part B Only Question No. Marks Awarded ‘After Recheck L Total 15 18 Signature of ExaminerInstructions General Instructions Rough work can be done in the given main answer booklet ‘The main answer booklet will not be evaluated. Final answer should be written in the mentioned space. In case of change of pen ink colour, get it endorsed by the invigilator. Answers in pencil will not be evaluated. Overwritten or tampered answer seripts will not be considered for a recheck. Usage of white ink or a correction pen is strictly prohibited. If done, it will be considered as a wrong answer. Usage of any electronic gadget is strictly prohibited. Usage of a non-programmable scientific calculator is allowed. (0. Don’t take out any pages out of this booklet. In case of missing pages, report to the invigilator. 11, Usage of any unfair means will lead to strict disciplinary actions as per the institute rules. 12, Formula-cum-data sheet is included at the last of this booklet, For Part A 1. Fill-up the circle completely only with a blue or black colour pen. 2. Partial bubbling/ multiple bubblings! circling/ tick marks! tampered OMR sheet will be considered as wrong answers. ‘There is no option to change the bubbling. Once done it can’t be changed. Only one OMR sheet will be provided to each student. ‘This OMR has to be submitted within 1 hour positively. Each question carries 3 marks for correct and -1 mark for incorrect. In case of your option is not matching, choose the closest one. For Part B 1. For Part B, final answer has to be written in the given space in this booklet. 2. Answers written anywhere else will not be evaluated. 3. There is no negative marking in Part B. Page 2 of 14Part-. Attempt all the questions, Choose the correct option for the following question: Consider the instruction: MOV AX, [1238H). This instruction is an example of, addressing mode. [3 marks /-1 mark] A. Immediate BO Direct CC. Indirect D. Register Assume that, SS = 2344H, DS = 4022H, BX = 0200H, BP = 1806H, SI = 1429H. If the following code is executed, what will be the contents (in hex) of AX, BX, and the effective address given by SO[SI|[BP]? Assume all uninitialized memory locations to contain the value zero. The answer in each option is given in the same order. [3 marks /-1 mark] MoV AX, 0223H Mov 50[ST] [BP], AX MOV BX, 51[(ST] [BP] XOR AX, BK VAC 0221 B. 0223 Cc. 0221 D. 0221 0002 0002 0002 0002, 2C7F 2C62 2F6E 1562 Which of the 8086 pins act both as address and data bus? [3 marks /-1 mark} V& AD ADs B. ADyADio GC. ADrADs DADs ADao. ‘You may replace the following code snippet with the single instruction: . [3 marks /-1 mark] PUSHF MOV BP, SP OR WORD PTR[BP+0], 0001 POPF wo STC B. CLD c. str D. CLI After executing the last line of the following code snippet interrupt occurs, [3 marks /-1 mark] MOV AX, TFEFH MOV BX, 1H ADD AX, BX INTO A. No B. Type-3 Ve Type-4 D. Type-S Page 3 of 146. The beginning and end address of INT 10is_28 Hand_28_H. [3 marks /-1 mark] ‘A. 0040,0043—B.0064,0067 ve 0028,0028 D000, 0041 7. The content of AX after executing the following code snippet is [3 marks /-1 mark] = DAT LIST DB OOH, 02H, O4H, OGH, O8H, OAK - CODE cic MoV AX, 81H RCL Al,1 MOV BX, OFFSET LIST Ll: XLAT SUB AX, 4 MOL AL ‘A. Garbage value v& 00008 C. 0004H D. 0010H 8. If A,,A,4A,;is used as the chip select logic of a 4 KB RAM in an 8086 system (where Ais to ‘Aie= 1), then its total memory range will be Hto H. [3 marks /-1 mark] A £8000, F9FFF —B. 08000, 09FFF C. 06000, 07FFF —D. F600, FTFFF 9. Consider the instruction: ROR BYTE PTR [2035H], Cx. Compute the duration (in us) of the complete bus cycle for the given instruction in 8086. Assume the clock frequency is 9 MHz and three wait states are inserted in each machine cycle. Also let CX has a count of 3. [3 marks /-1 mark] A. 07 B. 176 E21 D. 3 10. The opcode of a certain 8086 instruction is stored in the memory ftom the physical address 47F3Ah onwards, When the first byte of this instruction is to be read from the memory into the instruction queue, it is known that the offset address used by the BIU is D3SAh. Then, the (required segment register, content of that segment register) is - The answer in each, ‘option are in the same order. [3 marks /-1 mark] \& (CS,3ABEH) ~—-B. (CS,BE3AH) C. (DS,3ABEH) —D. (DS, BEIAH) 11. Which of the following is not a feature of 8086? [3 marks /-1 mark] 1AM Ithas 512 vectored interrupts. B. The size of instruction queue is 6-bytes. CC. buses 2 stages of pipelining. D. thas 20 address lines. Page 4 of 1412, Suppose that an external device utilizes the NMI pin to interrupt an x86-based system while it is executing the ISR corresponding to a Type-150 interrupt. Suppose that within the ISR of NMI is an instruction “INT 2H” before the “IRET” instruction, Assume that the Type-150 interrupt had occurred while the x86-based system was executing the main program. Further, assume that each ISR being executed unmasks all interrupts at the very beginning. Lastly, assume that the x86-based system is not interrupted by any other interrupt(s) of any kind than the ones mentioned above, at any point of time. Then, the order in which the execution of various programs/ISRs is completed, is [3 marks /-1 mark] A. ISR of INT 2H, ISR of NMI, ISR of Type-150 interrupt, main program. B._ ISR of Type-150 interrupt, ISR of NMI, ISR of INT 2H, main program. C._ ISR of NMI, ISR of INT 2H, ISR of Type-150 interrupt, main program. VI The main program never completes its execution. 13. Consider the following code snippet along with the machine cycles for each instruction provided as comments for that instruction. For branch instructions, the statement “a (or b) machine cycles” is to be interpreted as “a machine cycles, if branching occurs, and b machine cycles, if not.” Then, the total number of machine cycles (in decimal) required to execute the given code snippet when N= 3FEH and M= 78H is approximately [3 marks /-1 mark] MoV BX, N ;4 machine cycles UP: MOV CX, M 74 machine cycles HERE: LOOP HERE ;17 (or 5) machine cycles DEC BX 72 machine cycles NZ UP 716 (or 4) machine cycles AL 7x 10° WO 2x 10° Cc. 7x10" D. 2x 10° 14. Consider the address decoding circuit for an 8255 chip as shown below. The address for Port Ais H and for control register is. H. The answer in each option is in the same order, [3 marks /-1 mark] AS . 3D Lida, 8 ad) * 6 Q oO Ae A 119 B. 51,59 Le 99, 93 D. BB, E9 15, Consider an 8284 which is interfaced with 8086 to provide clock (CLK) signal. If the 8284 is connected with an 18 MHz crystal oscillator with proper configuration, what should be the frequency of the clock signal (in MHz)? [3 marks /-1 mark] Va 6 MHz B. 0.6MHz Cc, 3MHz D. 0.3 MHz Page Sof 14Part-B jempt all the ques a. Suppose you are given a 32-bit x86 microprocessor that does not support direct ‘multiplication operation. However, it supports only shifting and addition operations. The following code has been written to multiply 123 and 36. You need to complete the code to get the desired result. Note that the numbers are in decimal. [1x 7=7 Marks] 5 Mov BAX, [RIB FAX #36 = EAx 9 (25424) = SEA e254 Bax 42% Mov EBX, [IBAXINGr 123 = EAx #32 + EAX #09” ee ee = EAR #82 4 BAX #4 BSeB esx, (a b. Complete the following blanks to implement the following pseudocode in assembly language. Assume that the processor is 32-bit and *X’ is a 32-bit variable. [0.5 x 6 =3 Marks} Pseudocode: if( EBX > ECX ) OR ( EBX > vall ) Kel else x=2 Equivalent Assembly Language Code: OUR ==, Ee JA LA (GE ex, vali JA LL x,2 (DUP Next 11: (SUN x, 1 Next: Page 6 of 14‘A bubble sort compares pairs of array values, beginning with positions 0 and 1 of the array. If the compared values are in reverse order than what is required, they are exchanged. After one pass, the array is sill not sorted, but the largest value is now in the highest index position. The ‘outer loop starts another pass through the array. After (n-1) passes, the array is guaranteed to be sorted, Its useful to create a simplified version of the bubble sort, using pseudocode that is similar to assembly language. We will use N to represent the size of the array, ex to represent the outer loop counter, and ex2 to represent the inner loop counter. Mechanical concerns, such as saving and restoring the outer loop counter, have purposely been left out. Note that the inner loop count (ex2) is based on the current value of the outer loop count (ex1), which in tum decreases with each pass through the array. Pseudocode: cxlL=N-1 while(cxl > 0 ) { ESI = addr (array) x2 = cxl while( cx2 > 0) ( if( array(ESI]) > array[ESI+4] ) EXCHANGE (array [ESI], array(ESI+4] ADD ESI, 4 DEC cx2 DEC cx1 Fill in the blanks for the given assembly code to implement the pseudocode in a 32-bit processor. [1x 10=10 Marks} BubbleSort PROC USES EAX ECX ESI, pArray:PTR DHORD, 3 Pointer to array, Count : DHORD > Array Size MOV ECX, Count WIE ecx ; Decrement count byt. Ll: PUSH BCX 5 Save outer loop oumt Mov EST, —BIARPAYE 5 Point to first value n2: Mov EBARM, [EST] 5 Get arugy value MOURNE (s1+4),NBVARN , compar a pair of valusn ue us 5 Te Lest] ¢ LesT+4], no exchang. iene Bax, fsx), 5 Exchamge the pair Nov BES, 22x 13 ESI,4 Move both pointers forward. Page 7 of 14tor 12 3 Inner leep PoP [BGR 3 Retrive outer loop Count LOOP b1 ; Else repeat outer loop: L4: RET BubbleSort ENDP ‘When storage space is ata premium, system-level software often packs multiple data fields into asingle integer. To uncover this data, applications often need to extract sequences of bits called bit strings. For example, in real-address mode, MS-DOS function 57h returns the date stamp of a file in DX. (The date stamp shows the date on which the file was last modified.) Bits 0 through 4 represent a day number between | and 31, bits 5 through 8 are the month number, and bits 9 through 15 hold the year number. Ifa file was last modified on March 10, 1999, the file’s date stamp would appear as follows in the DX register (the year number is relative to 1980): bit bu 7 FF 1 Doroo110 01 to1010 J LJ L__ Fil: Yeur ‘Month Day imambers 9.15, 58 os To extract a single bit string, shift its bits into the lowest part of a register and clear the irrelevant bit positions. The following code example extracts the day number field of a date stamp integer by making a copy of DL and masking off bits not belonging to the field. To extract the month umber field, we shift bits 5 through 8 into the low part of AL before masking off all other bits. AL is then copied into a variable. The year number (bits 9 through 15) field is completely within the DH register. We copy it to AL and shift right by 1 bit. ‘Complete the code with the given information. Assume that the code is written in a 32-bit x86 processor. [1 13= 13 Marks) Mov AL, EDI 5 Make a copy of DL WAND) aL, EER! 5 clear bib 5-4 Nov pay, [AIBN ; Save in day Mov BBRE,DX 5 Make a coby ef “DX ax, BE 5 Shift right 5 bi AND AL, OPMMH 5 Cleary bin 4-¥ Mov MONTH, | 5 Save in Month MOV AL,DH , Make a copy of DH. Page 8 of 14ESHRE At, BAM, sWijt right one posiow Mov aK, MOM , Clean AH +o Xonos ADD AX, (WSK 5 Yean % relative to 1980 Mov YEAR,aAX 3 Sawe Yn Year 4, A256KB RAM memory is composed of eight 32 KB RAMS, We have got only one 3:8 decoder circuit Fill in the grey colour boxes for the given circuit diagram. The starting eddress of the RAM is 00000H and all the addresses for RAMS are sequentially mapped. The answer should follow the given format. Any other format will lead to zero marks. [0.5 x 10=5 Marks} RAM no with address Address Pin No. Format: RAMO [00000H-XXXXXH] Ae A Y,P——* RAMO [00000 H- OF FFF H] A, ——>B Y,p———> RAMI [og000H - OF FFF HK] Ag ——C Y,p——> RAM2 [10000H-IFFFFH] Y, P+ Ram3 [18000H - 1 FFFFH] y, > RAM P2OOCOH 2a Fra] 74LS138 y,p——+| RAM [280000 - 2FFFEH] eal >——+| Rae [30000H~ 34 FFFH) b——+| RAM [ 38000H - SFFFFH) — 1] |¢4 a, Se] ——m/10 G2A Aw Note! RAM numbering you can start from 4h imlead e¢ 0- Aig amd Arq cambe interchamged. D4 interchanged » then Ne Will Showkd be cennected to RAMO. LD Page 9 of 145. Consider the following figure. The 8255 in the figure is configured in Mode 0, Port A as input, Port B as output, PCo— PC; as input while, PC;~ PC? as output. The base address of 8255 is taken to be 40 H. An 8-bit ADC (ADC 0804), is connected as per the diagram. Port C is used to generate the RD and WR inputs of the 0804, and to read the end of the conversion status. The 741 op-amp converts a bipolar +/- input voltage swing in to a unipolar 0-5 V signal that can be digitized by 0804. To start a conversion, the 0804's WR line must be pulled low and. then made high. This will force the INT output to remain high until the conversion is complete. ‘When INT goes low, the converted output from 0804 can be read by pulling the RD input low and reading the Port A. The RD signal is then made high after Port A is read. ‘The following subroutine is called to initialize 8255 (to operate as mentioned above), perform a single conversion, display the result on the LEDs (to give a visual indication that everything is working properly) and store the converted value in the AH register. Fill in the blanks to complete the code. Note that the unit of resistance shown in the figure below is ohms. [2x 9=18 Marks} "Use 150 in all positions Page 10 of 14‘SUBROUTINE VCON PROC FAR MOV AL,—IGOMEH 5 start a conversion by pulling WR low. our (ABM, an Mov AL,—§S6MH 5 now pull WR high our BAQEB, an MOV AL, 90H OUT 42H, AL in AL, ABN 5" read porte - tent bit-o (INT) wait fer end of conversion. AND AL,1 gz EOC enable RD our 42H, (A IN AL, } read the O804 oy pork A our 41H, aL 3 echo data in port & vov MW, aL 5 return result in AK Mov AL, 90H 5 gtk RD back to Normal. our 42H, AL RET VCON ENDP Page 11 of 146. Consider the following diagram indicating the interfacing between 8254 and 8088 2MHz i | 47 KO CuK D Gate| _/A\—as5V IORC RD Out, | lowe. wR CLK, 47kQ }A/\-a45V }———> To Interrupt Ae—| Circuit A—{ >— Answer the following questions. a. The 8254 is interfaced with an 8088 processor that is operating in (eee arimUAA mode. [Mark] (8088 maximum mede! indicated by TORC ome Towe sign). b. Write the port addresses and control word address for the given circuitry. [1x 4=4 Marks} ‘Counter? CWR “Address in Hex Counter 0 Counter 1 Counter 2 Control Word Register t ; a ae 4wo 8-i/p NAND qa in tee pork - addres decoder. Map tar 8254 inte four T/o locatiom, CeBOH +o CcBSH. Page 12 of 14c. A2MHz clock is avaitable for timing in a system that needs to be interrupted once in every 4 seconds. The figure indicates the used hardware configuration. Complete the code to achieve the mentioned problem statement. [1x 8=8 marks} Exp. The figure show how crumberd and Mov Dx, (OGeSS HII: counter | ane connected to implement _ tae 0°25 Hz (Vac) interrupt clock. Mov AL, [ll The 2MHa clk connected to CLIKO WA OUT Dx, AL creali ofp pulnes on OUTO, Wraw cour 2» programmel in mode 2. These Mov AL, [ll mi O/P pulser serve on tm CLK fer counlat in mede 2). Dividi coma (alno programmed in aoa 2QMHz by O25Hz gives 8,000,000. Thin Mov Dx, [MOCESONNNNH the count thar munt be simulated by both counteu. Mamy schemus oe , (56000 , A ails as possible. ne such scheme w to load ovr rx, aL coumter 0 With 50,060 and counterL wath leo resulting the product to be vov at, il 8,000,000. OUT DX, AL Coumter 6 will output one pune in, every 50,000 CLRO puleer wile coumtin 1 ane! i ANE, oe Wik o/p one pune for every 60 cle’ Mov AL, [i6O) anna our Dx, AL 4. Complete the code if we want to progran Counter 2 for binary counting in mode 1 with an initial count of AOH? Mov Mov ofp control word —» our Mov Dx, AL, Dx, Dx, MOV AL, O/p initial count» OUT DX, ESs2wey ies ; (mesons) Formula-cum-data shee 1086: [1x 6=6 Marks} The centro! word reauired b 92H. Becauwe the count reginter ir cleaned ren te Counter b programmed, writing AOH to the lower halt Teoults in an initial coumt o COACH. Notice that the control word indicates that only the lower B bi am needed to load the Counter. Bi 15 141312 11109 6l7 6 5 4 3 214 ol Page 13 of 14DM7ALS138 ete le fe te fs Ie le ee] oe ou tee eo L x x]x]x) H | H) a/R] H]AA) Inte 82542 Control Word Format Dy__Ds__Ds__Dy_Ds_Dp_ Dy Dp 3c: [Score [wo [we [wr [wo [Bo scSelect Counter wos eat Se nt ai iio cnet ooara et] OE Toe naa aT] af csr a nickel cancion oc 1a) pe ck conmand epee {600 Ficad Operations) 7 ° ° Mode 4 a —Reaatte en 0 | © |Countor Latch Command (soe Road oo a 0 [Bin Gonior 16s © | 1 [Read/Write least significant byte onty| 1 Binary Coded Decimal (BCD) Counter aa {4 Decades) © [Roadie os sips xo 17] [Renate site br [then most significant byte. acre Sofa sp) tb wae cone wih rs al pro. Intel 8255: Control Word Format crsrerkteterery nee ee ma in Sees e —| re — Se aa a |—_—_ Ee Page 14 of 14